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5
Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 Greatorex
|
44f0cd871d | ||
|
Greatorex
|
e09b4a0f7e | ||
|
Greatorex
|
7db428b827 | ||
|
Greatorex
|
ba17fc0d1b | ||
|
Greatorex
|
fbcd679b4c |
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@@ -131,18 +131,18 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
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sigbuf_1output<12> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
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// Acknowledgment
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OR2_X1 ack_readwrite(.a = _in_a_write,.b = _in_a_read,.y = _in_a_temp,.vdd = supply.vdd,.vss = supply.vss);
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OR2_X1 ack_readwrite(.a = _in_a_write,.b = _in_a_read,.y = _in_a_temp,.vdd = supply.vdd,.vss = supply.vss);
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sigbuf_1output<12> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
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// WRITE
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// Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active)
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bool _in_v_temp_write;
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AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f, .y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
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AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f,.y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
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delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply);
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INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
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sigbuf<nw> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
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sigbuf<nw> clk_X(.in = _clock_temp_inv, .out = _clock,.supply = supply);
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sigbuf<wl> clock_buffer[nw];
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bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
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// Sending back to the ackowledge
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// Sending back to the acknowledge
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bool _in_a_write_temp;
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delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply);
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AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss);
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@@ -154,7 +154,6 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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ortree<nw> bitselector_f[wl];
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AND2_X1 word_selector_t[nw*wl];
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AND2_X1 word_selector_f[nw*wl];
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bool _out_word_to_read[2*nw*wl];
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buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B);
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AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw];
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// Outputting the address if the read is true
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@@ -186,6 +185,11 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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// Creating the different flip flop arrays
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bool _out_encoder[nw];
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DFFQ_R_X1 ff[nw*wl];
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AND2_X1 val_chck[nw*wl];
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bool _val_chck_out[nw*wl];
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bool _in_v_temp_buf[nw*wl];
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sigbuf<nw*wl> v_buf(.in = _in_v_temp,.out = _in_v_temp_buf,.supply = supply);
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// For loop for assigning the different components
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pint bitval;
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(k:nw:atree[k].supply = supply;)
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@@ -221,9 +225,13 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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word_to_read_X[word_idx].supply = supply;
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(bit_idx:wl:
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// Describing all the FF and their connection
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val_chck[bit_idx].a = _in_v_temp_buf[word_idx+bit_idx];
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val_chck[bit_idx].b = in.d.d[bit_idx].t;
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val_chck[bit_idx].y = _val_chck_out[bit_idx];
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val_chck[bit_idx].vdd = supply.vdd;
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val_chck[bit_idx].vss = supply.vss;
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ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
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ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
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ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
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@@ -231,11 +239,11 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
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ff[bit_idx+word_idx*(wl)].vss = supply.vss;
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// READ: creating the selectors for propagating the right word
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word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+word_idx*(wl)].a;
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word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+word_idx*(wl)].a;
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word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q;
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word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+(word_idx*(wl))].a;
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word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+(word_idx*(wl))].a;
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word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q;
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word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx];
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word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q_B;
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word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+(word_idx*(wl))].q_B;
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word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx];
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bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t;
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bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f;
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@@ -246,7 +254,5 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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}
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}}
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@@ -1,57 +1,49 @@
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t.ff._mqib t.clk t.d t.q t.ff._sqib t.ff._sqi t.ff.__clk t.ff._mqi t.ff._clk
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t.ff.__clk_B t.ff._clk_B t.d t.clk
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[0] start test
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1 Reset : 0
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1 t.clk : 0
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1 t.d : 0
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3 t.ff._mqib : 1 [by t.d:=0]
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4756 t.ff._mqi : 0 [by t.ff._mqib:=1]
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5893 t.ff._sqib : 1 [by t.ff._mqi:=0]
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6007 t.ff._sqi : 0 [by t.ff._sqib:=1]
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7093 t._reset_B : 1 [by Reset:=0]
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10468 t.ff._clk : 1 [by t.clk:=0]
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12194 t.ff.__clk : 0 [by t.ff._clk:=1]
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71259 t.q : 0 [by t.ff._sqib:=1]
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61021 Reset : 0
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61021 t.clk : 1
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61021 t.d : 0
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61022 t.ff._clk_B : 0 [by t.clk:=1]
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61023 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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65875 t._reset_B : 1 [by Reset:=0]
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[1] reset completed
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71259 t.clk : 1
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71298 t.ff._clk : 0 [by t.clk:=1]
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71313 t.ff.__clk : 1 [by t.ff._clk:=0]
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[2] tested d = 0, clk rise
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71313 t.clk : 0
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71804 t.ff._clk : 1 [by t.clk:=0]
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71817 t.ff.__clk : 0 [by t.ff._clk:=1]
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71817 t.d : 1
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71817 t.clk : 1
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71857 t.ff._clk : 0 [by t.clk:=1]
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72272 t.ff.__clk : 1 [by t.ff._clk:=0]
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72292 t.ff._mqib : 0 [by t.ff.__clk:=1]
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78353 t.ff._mqi : 1 [by t.ff._mqib:=0]
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78353 t.d : 0
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78353 t.clk : 0
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WARNING: unstable `t.ff._mqib'+
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>> cause: t.ff._clk (val: 1)
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78369 t.ff._clk : 1 [by t.clk:=0]
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WARNING: weak-interference `t.ff._mqi'
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>> cause: t.ff._mqib (val: X)
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>> time: 78400
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78400 t.ff._mqib : X [by t.ff._clk:=1]
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78404 t.ff._mqib : 0 [by t.ff._clk:=1]
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WARNING: weak-unstable `t.ff._sqib'-
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>> cause: t.ff._mqi (val: X)
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>> time: 87529
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87529 t.ff._mqi : X [by t.ff._mqib:=0]
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87544 t.ff._mqi : 1 [by t.ff._mqib:=0]
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WARNING: weak-interference `t.ff._sqi'
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>> cause: t.ff._sqib (val: X)
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>> time: 92093
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WARNING: weak-interference `t.q'
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>> cause: t.ff._sqib (val: X)
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>> time: 92093
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92093 t.ff._sqib : X [by t.ff._mqi:=1]
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92148 t.q : X [by t.ff._sqib:=X]
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122467 t.ff.__clk : 0 [by t.ff._clk:=1]
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129024 t.ff._sqi : X [by t.ff._sqib:=X]
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135341 t.ff._sqib : 0 [by t.ff._mqi:=1]
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165121 t.q : 1 [by t.ff._sqib:=0]
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186994 t.ff._sqi : 1 [by t.ff._sqib:=0]
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65875 t.clk : 0
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65875 t.d : 1
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84773 t.ff._mqib : 0 [by t.d:=1]
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85476 t.ff._mqi : 1 [by t.ff._mqib:=0]
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96922 t.ff._clk_B : 1 [by t.clk:=0]
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97123 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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107244 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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107250 t.ff._sqi : 1 [by t.ff._sqib:=0]
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110736 t.q : 1 [by t.ff._sqib:=0]
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110738 t.ff.q_B : 0 [by t.q:=1]
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110738 t.clk : 1
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113054 t.ff._clk_B : 0 [by t.clk:=1]
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113104 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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113104 t.d : 0
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114289 t.ff._mqib : 1 [by t.d:=0]
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137967 t.ff._mqi : 0 [by t.ff._mqib:=1]
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137967 t.clk : 0
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137992 t.ff._clk_B : 1 [by t.clk:=0]
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138009 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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138073 t.ff._sqib : 1 [by t.ff.__clk_B:=0]
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138074 t.q : 0 [by t.ff._sqib:=1]
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138478 t.ff._sqi : 0 [by t.ff._sqib:=1]
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203221 t.ff.q_B : 1 [by t.q:=0]
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203221 t.d : 1
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203221 t.clk : 1
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203222 t.ff._clk_B : 0 [by t.clk:=1]
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214646 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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227406 t.ff._mqib : 0 [by t.ff.__clk_B:=1]
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227582 t.ff._mqi : 1 [by t.ff._mqib:=0]
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[3] tested d = 1, clk rise and fall
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227582 t.clk : 0
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227583 t.ff._clk_B : 1 [by t.clk:=0]
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227590 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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227593 t.q : 1 [by t.ff._sqib:=0]
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234776 t.ff.q_B : 0 [by t.q:=1]
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241004 t.ff._sqi : 1 [by t.ff._sqib:=0]
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278221 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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278221 t.d : 0
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@@ -4,22 +4,24 @@
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"Reset"->"t._reset_B"-
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~("Reset")->"t._reset_B"+
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= "t._reset_B" "t.ff.reset_B"
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"t.ff.clk"->"t.ff._clk"-
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~("t.ff.clk")->"t.ff._clk"+
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"t.ff._clk"->"t.ff.__clk"-
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~("t.ff._clk")->"t.ff.__clk"+
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~"t.ff.d"&~"t.ff._clk"|~"t.ff.reset_B"|~"t.ff.__clk"&~"t.ff._mqi"->"t.ff._mqib"+
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"t.ff.d"&"t.ff.__clk"|"t.ff.reset_B"&"t.ff._mqi"&"t.ff._clk"->"t.ff._mqib"-
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"t.ff.clk_B"->"t.ff._clk_B"-
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~("t.ff.clk_B")->"t.ff._clk_B"+
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"t.ff._clk_B"->"t.ff.__clk_B"-
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~("t.ff._clk_B")->"t.ff.__clk_B"+
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~"t.ff.d"&~"t.ff._clk_B"|~"t.ff.reset_B"|~"t.ff.__clk_B"&~"t.ff._mqi"->"t.ff._mqib"+
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("t.ff.d"&"t.ff.__clk_B"|"t.ff._mqi"&"t.ff._clk_B")&"t.ff.reset_B"->"t.ff._mqib"-
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"t.ff._mqib"->"t.ff._mqi"-
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~("t.ff._mqib")->"t.ff._mqi"+
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~"t.ff._mqi"&~"t.ff.__clk"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk"->"t.ff._sqib"+
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"t.ff._mqi"&"t.ff._clk"|"t.ff._sqi"&"t.ff.__clk"&"t.ff.reset_B"->"t.ff._sqib"-
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~"t.ff._mqi"&~"t.ff.__clk_B"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk_B"->"t.ff._sqib"+
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("t.ff._mqi"&"t.ff._clk_B"|"t.ff._sqi"&"t.ff.__clk_B")&"t.ff.reset_B"->"t.ff._sqib"-
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"t.ff._sqib"->"t.ff._sqi"-
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~("t.ff._sqib")->"t.ff._sqi"+
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"t.ff._sqib"->"t.ff.q"-
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~("t.ff._sqib")->"t.ff.q"+
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"t.ff.q"->"t.ff.q_B"-
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~("t.ff.q")->"t.ff.q_B"+
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= "Vdd" "t.ff.vdd"
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= "GND" "t.ff.vss"
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= "t.q" "t.ff.q"
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= "t.clk" "t.ff.clk"
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= "t.clk" "t.ff.clk_B"
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= "t.d" "t.ff.d"
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@@ -33,7 +33,7 @@ open tmpl::dataflow_neuro;
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defproc flipflop_test (bool! q; bool? d,clk){
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DFFQ_R_X1 ff(.d=d,.clk = clk, .q = q);
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DFFQ_R_X1 ff(.d=d,.clk_B = clk, .q = q);
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//Low active Reset
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bool _reset_B;
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prs {
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@@ -1,29 +1,51 @@
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watchall
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system "echo '[0] start test'"
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set Reset 0
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set t.d 0
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set t.clk 0
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set t.clk 1
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cycle
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status X
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mode run
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assert t.q 0
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cycle
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assert t.q 0
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system "echo '[1] reset completed'"
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set t.clk 1
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cycle
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assert t.q 0
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system "echo '[2] tested d = 0, clk rise'"
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set t.clk 0
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set t.d 1
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cycle
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set t.clk 1
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cycle
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set t.d 0
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cycle
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assert t.q 1
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set t.clk 0
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cycle
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assert t.q 0
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set t.d 0
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set t.clk 0
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cycle
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assert t.q 0
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set t.d 1
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cycle
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set t.clk 1
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cycle
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set t.d 0
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assert t.q 0
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system "echo '[3] tested d = 1, clk rise and fall'"
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set t.d 1
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cycle
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set t.clk 0
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cycle
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set t.d 0
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cycle
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assert t.q 1
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system "echo '[3] tested d = 1, clk rise and fall'"
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@@ -1,149 +1,2 @@
|
||||
t.registers.read_write_demux.vc.ct.in[0] t.registers.read_write_demux._en2_X_t[0] t.in.d.d[1].f t.registers.read_write_demux._c_f_buf[0] t.registers.read_write_demux.out2_a_B_buf_t.buf1._y t.registers.read_write_demux._out1_a_BX_f[0] t.in.d.d[3].t t.registers._in_read.v t.registers.read_write_demux._in_v t.in.d.d[1].t t.registers.read_write_demux._c_v t.in.d.d[0].t t.registers.read_write_demux._en1_X_f[0] t.in.d.d[4].f t.registers.read_write_demux.out1_en_buf_f.buf1._y t.in.d.d[0].f t.registers.read_write_demux.vc.ct.tmp[5] t.in.d.d[2].f t.registers.read_write_demux._out2_a_BX_t[0] t.in.d.d[3].f t.registers.read_write_demux._c_t_buf[0] t.registers.read_write_demux.vc.ct.C2Els[0]._y t.registers.read_write_demux._out1_a_BX_t[0] t.in.v t.registers.read_write_demux._en t.registers.read_write_demux._out1_a_B t.registers.read_write_demux._out2_a_BX_f[0] t.in.d.d[4].t t.registers.read_write_demux.c_buf_f.buf1._y t.registers.read_write_demux._en2_X_f[0] t.registers.read_write_demux._en1_X_t[0] t.registers.read_write_demux.out1_a_B_buf_t.buf1._y t.registers.read_write_demux.out2_en_buf_f.buf1._y t.registers.read_write_demux._out2_a_B t.registers.read_write_demux.vc.ct.tmp[4] t.registers.read_write_demux.vc.ct.in[2] t.registers.read_write_demux._in_c_v_ t.registers.read_write_demux.out2_en_buf_t.buf1._y t.registers._in_read.a t.in.d.d[2].t t.registers.read_write_demux.out2_a_B_buf_f.buf1._y t.registers.read_write_demux.vc.ct.in[1] t.registers.read_write_demux.c_buf_t.buf1._y t.registers.read_write_demux.c_f_c_t_or._y t.registers.read_write_demux._out_v t.registers._in_write.a t.registers._in_write.v t.registers.read_write_demux.in_v_buf._y t.registers.read_write_demux.out1_a_B_buf_f.buf1._y t.registers.read_write_demux.out1_en_buf_t.buf1._y t.registers.read_write_demux.vc.ct.in[3] t.registers.read_write_demux.vc.OR2_tf[1]._y t.registers.read_write_demux.c_el._y t.registers.read_write_demux.out_or._y t.registers.read_write_demux.vc.OR2_tf[2]._y t.registers.read_write_demux.vc.ct.C2Els[1]._y t.registers.read_write_demux.vc.OR2_tf[0]._y t.registers.read_write_demux.vc.ct.C2Els[2]._y t.registers.read_write_demux.vc.OR2_tf[3]._y
|
||||
t.registers.ff[4].clk_B t.registers._clock_word_temp[0] t.in.d.d[1].f t.registers._clock_temp t.registers.ack_dly._a[1] t.registers.ff[0].clk_B t.registers._clock t.dly_cfg[1] t.registers.ff[0].d t.registers.ack_dly.dly[1].__y t.registers.clk_dly.and2[0]._y t.registers.val_input.ct.in[1] t.in.d.d[4].f t.registers._clock_word_temp[2] t.registers.ff[5].__clk_B t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.registers.ff[4]._clk_B t.registers._out_encoder[3] t.registers.clock_buffer[1].buf1._y t.registers.ff[6].clk_B t.registers.atree[2].in[1] t.dly_cfg[0] t.registers._in_v_temp t.registers._out_encoder[2] t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.atree[0].in[0] t.registers.ack_dly.dly[2]._y t.registers.val_input.ct.in[0] t.registers._in_a_temp t.in.d.d[0].f t.in.v t.registers.clk_dly.dly[1].y t.registers.ff[3]._clk_B t.in.d.d[4].t t.registers.clk_dly.dly[2].y t.registers.clk_dly.dly[1].a t.registers._clock_word_temp[3] t.registers.ack_dly.dly[0].___y t.registers.val_input.ct.in[3] t.registers.ff[1].d t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.atree[1].in[0] t.registers.ack_dly.dly[2].___y t.registers.ack_dly.mu2[0]._y t.registers.atree[1].and2s[0]._y t.registers.clk_dly._a[1] t.registers.atree[0].in[1] t.registers.ff[2].__clk_B t.registers.val_input.ct.in[4] t.registers.val_input.OR2_tf[3]._y t.registers.clk_X.buf1._y t.registers.ff[7].__clk_B t.registers._clock_word_temp[1] t.registers.and_encoder[2]._y t.registers.clk_dly.dly[0].___y t.registers._clock_temp_inv t.registers.ff[7]._clk_B t.registers.clk_dly.dly[1].___y t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[1]._clk_B t.registers.clk_dly.dly[0]._y t.registers.val_input.ct.in[2] t.registers.val_input.OR2_tf[2]._y t.registers.val_input.ct.tmp[6] t.registers.clk_dly.dly[1]._y t.registers.ack_dly.dly[2].y t.registers.atree[0].and2s[0]._y t.registers.clk_dly.mu2[1]._y t.registers.clk_dly.mu2[0]._s t.registers.ack_dly.dly[0]._y t.registers.clk_dly.dly[0].a t.registers.ack_dly.dly[0].a t.registers.ff[0]._clk_B t.registers.clock_buffer[2].buf1._y t.registers.clk_dly.dly[1].__y t.registers.ff[2].clk_B t.registers.ff[6]._clk_B t.registers.clk_dly.dly[0].y t.registers.clk_dly.mu2[0]._y t.registers.clock_buffer[3].buf1._y t.registers.val_input.ct.tmp[5] t.registers.ack_dly.dly[1]._y t.registers.and_encoder[0]._y t.registers.val_input.ct.C2Els[1]._y t.registers.ack_dly.dly[1].y t.registers.ack_dly.and2[1]._y t.registers.val_input.OR2_tf[1]._y t.registers.clk_dly.dly[0].__y t.registers.ff[3].__clk_B t.registers.ack_dly.dly[0].y t.registers.clk_dly.dly[2].__y t.registers.atree[3].and2s[0]._y t.registers.ff[6].__clk_B t.registers.ack_dly.dly[1].a t.registers.ff[4].__clk_B t.registers.atree[2].and2s[0]._y t.registers.ff[1].__clk_B t.registers.val_input_X.buf1._y t.registers.ack_dly.dly[2].__y t.registers.val_input.OR2_tf[0]._y t.registers.ff[0].__clk_B t.registers.ff[5]._clk_B t.registers.and_encoder[1]._y t.registers.ack_dly.and2[0]._y t.registers.ack_dly.mu2[1]._s t.registers.clk_dly.dly[2].___y t.registers.val_input.OR2_tf[4]._y t.registers.ack_input_X.buf1._y t.registers.val_input.ct.C2Els[0]._y t.registers.ack_dly.mu2[1]._y t.registers.val_input.ct.C3Els[0]._y t.registers.ack_dly.dly[0].__y t.registers.and_encoder[3]._y t.registers.ff[2]._clk_B t.registers.ack_dly.mu2[0]._s
|
||||
[0] start test
|
||||
Node `t._in_write.d.d[0].f' not found
|
||||
Node `t._in_read.d.d[0].f' not found
|
||||
106506 t.in.d.d[0].f : 0
|
||||
106506 Reset : 0
|
||||
106506 t.registers._in_read.v : 0
|
||||
106506 t.in.d.d[1].f : 0
|
||||
106506 t.registers._in_write.v : 0
|
||||
106506 t.registers._in_read.a : 0
|
||||
106506 t.in.d.d[3].f : 0
|
||||
106506 t.registers._in_write.a : 0
|
||||
106506 t.data[1].d[1] : 0
|
||||
106506 t.in.d.d[2].t : 0
|
||||
106506 t.data[1].d[0] : 0
|
||||
106506 t.data[0].d[1] : 0
|
||||
106506 t.in.d.d[0].t : 0
|
||||
106506 t.in.d.d[2].f : 0
|
||||
106506 t.data[0].d[0] : 0
|
||||
106506 t.in.d.d[4].t : 0
|
||||
106506 t.in.d.d[1].t : 0
|
||||
106506 t.in.d.d[4].f : 0
|
||||
106506 t.in.d.d[3].t : 0
|
||||
106524 t.registers.read_write_demux.c_buf_t.buf1._y : 1 [by t.in.d.d[4].t:=0]
|
||||
107057 t._reset_B : 1 [by Reset:=0]
|
||||
107460 t.registers.read_write_demux._out2_a_B : 1 [by t.registers._in_read.a:=0]
|
||||
107488 t.registers.read_write_demux.vc.OR2_tf[2]._y : 1 [by t.in.d.d[2].f:=0]
|
||||
107559 t.registers.read_write_demux.reset_buf._y : 0 [by t._reset_B:=1]
|
||||
107577 t.registers.read_write_demux.out_or._y : 1 [by t.registers._in_write.v:=0]
|
||||
107587 t.registers.read_write_demux._out1_a_B : 1 [by t.registers._in_write.a:=0]
|
||||
107598 t.registers.read_write_demux.out1_a_B_buf_f.buf1._y : 0 [by t.registers.read_write_demux._out1_a_B:=1]
|
||||
107627 t.registers.read_write_demux.vc.ct.in[2] : 0 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=1]
|
||||
107646 t.registers.read_write_demux._out_v : 0 [by t.registers.read_write_demux.out_or._y:=1]
|
||||
107661 t.registers.read_write_demux._en : 1 [by t.registers.read_write_demux._out_v:=0]
|
||||
107662 t.registers.read_write_demux.out2_en_buf_f.buf1._y : 0 [by t.registers.read_write_demux._en:=1]
|
||||
107663 t.registers.read_write_demux.out2_a_B_buf_t.buf1._y : 0 [by t.registers.read_write_demux._out2_a_B:=1]
|
||||
107698 t.registers.read_write_demux.out1_en_buf_t.buf1._y : 0 [by t.registers.read_write_demux._en:=1]
|
||||
107703 t.registers.read_write_demux._out2_a_BX_f[0] : 1 [by t.registers.read_write_demux.out2_a_B_buf_t.buf1._y:=0]
|
||||
107773 t.registers.read_write_demux.out1_en_buf_f.buf1._y : 0 [by t.registers.read_write_demux._en:=1]
|
||||
107802 t.registers.read_write_demux._out1_a_BX_t[0] : 1 [by t.registers.read_write_demux.out1_a_B_buf_f.buf1._y:=0]
|
||||
107860 t.registers.read_write_demux._en1_X_f[0] : 1 [by t.registers.read_write_demux.out1_en_buf_f.buf1._y:=0]
|
||||
107955 t.registers.read_write_demux._en1_X_t[0] : 1 [by t.registers.read_write_demux.out1_en_buf_t.buf1._y:=0]
|
||||
108400 t.registers.read_write_demux.out2_en_buf_t.buf1._y : 0 [by t.registers.read_write_demux._en:=1]
|
||||
108694 t.registers.read_write_demux._en2_X_t[0] : 1 [by t.registers.read_write_demux.out2_en_buf_t.buf1._y:=0]
|
||||
109314 t.registers.read_write_demux.out2_a_B_buf_f.buf1._y : 0 [by t.registers.read_write_demux._out2_a_B:=1]
|
||||
109315 t.registers.read_write_demux._out2_a_BX_t[0] : 1 [by t.registers.read_write_demux.out2_a_B_buf_f.buf1._y:=0]
|
||||
110509 t.registers.read_write_demux.c_f_c_t_or._y : 1 [by t.in.d.d[4].f:=0]
|
||||
110519 t.registers.read_write_demux.vc.OR2_tf[1]._y : 1 [by t.in.d.d[1].t:=0]
|
||||
111284 t.registers.read_write_demux._c_t_buf[0] : 0 [by t.registers.read_write_demux.c_buf_t.buf1._y:=1]
|
||||
112315 t.registers.read_write_demux._c_v : 0 [by t.registers.read_write_demux.c_f_c_t_or._y:=1]
|
||||
112526 t.registers.read_write_demux.vc.ct.in[1] : 0 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=1]
|
||||
128090 t.registers.read_write_demux.vc.OR2_tf[3]._y : 1 [by t.in.d.d[3].t:=0]
|
||||
129299 t.registers.read_write_demux.vc.ct.in[3] : 0 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=1]
|
||||
129889 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 1 [by t.registers.read_write_demux.vc.ct.in[3]:=0]
|
||||
130067 t.registers.read_write_demux.vc.ct.tmp[5] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=1]
|
||||
143905 t.registers.read_write_demux._reset_BX : 1 [by t.registers.read_write_demux.reset_buf._y:=0]
|
||||
144708 t.registers.read_write_demux.reset_bufarray.buf3._y : 0 [by t.registers.read_write_demux._reset_BX:=1]
|
||||
144872 t.registers.read_write_demux._reset_BXX[0] : 1 [by t.registers.read_write_demux.reset_bufarray.buf3._y:=0]
|
||||
151407 t.registers.read_write_demux.c_buf_f.buf1._y : 1 [by t.in.d.d[4].f:=0]
|
||||
153602 t.registers.read_write_demux._c_f_buf[0] : 0 [by t.registers.read_write_demux.c_buf_f.buf1._y:=1]
|
||||
155174 t.registers.read_write_demux._en2_X_f[0] : 1 [by t.registers.read_write_demux.out2_en_buf_f.buf1._y:=0]
|
||||
159373 t.registers.read_write_demux.out1_a_B_buf_t.buf1._y : 0 [by t.registers.read_write_demux._out1_a_B:=1]
|
||||
159395 t.registers.read_write_demux._out1_a_BX_f[0] : 1 [by t.registers.read_write_demux.out1_a_B_buf_t.buf1._y:=0]
|
||||
160976 t.registers.read_write_demux.vc.OR2_tf[0]._y : 1 [by t.in.d.d[0].t:=0]
|
||||
161823 t.registers.read_write_demux.vc.ct.in[0] : 0 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=1]
|
||||
191951 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 1 [by t.registers.read_write_demux.vc.ct.in[0]:=0]
|
||||
192084 t.registers.read_write_demux.vc.ct.tmp[4] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=1]
|
||||
207746 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 1 [by t.registers.read_write_demux.vc.ct.tmp[4]:=0]
|
||||
208105 t.registers.read_write_demux._in_v : 0 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=1]
|
||||
208326 t.registers.read_write_demux.c_el._y : 1 [by t.registers.read_write_demux._in_v:=0]
|
||||
208333 t.registers.read_write_demux._in_c_v_ : 0 [by t.registers.read_write_demux.c_el._y:=1]
|
||||
222221 t.registers.read_write_demux.in_v_buf._y : 1 [by t.registers.read_write_demux._in_v:=0]
|
||||
222251 t.in.v : 0 [by t.registers.read_write_demux.in_v_buf._y:=1]
|
||||
|
||||
[1] reset completed
|
||||
222251 t.dly_cfg[0] : 1
|
||||
222251 t.dly_cfg[1] : 1
|
||||
[2] delay line set
|
||||
222251 t.in.d.d[0].t : 1
|
||||
222251 t.in.d.d[4].t : 1
|
||||
222251 t.in.d.d[2].f : 1
|
||||
222251 t.in.d.d[1].t : 1
|
||||
222251 t.in.d.d[3].f : 1
|
||||
222258 t.registers.read_write_demux.vc.OR2_tf[1]._y : 0 [by t.in.d.d[1].t:=1]
|
||||
222342 t.registers.read_write_demux.c_f_c_t_or._y : 0 [by t.in.d.d[4].t:=1]
|
||||
222364 t.registers.read_write_demux.vc.ct.in[1] : 1 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=0]
|
||||
222420 t.registers.read_write_demux._c_v : 1 [by t.registers.read_write_demux.c_f_c_t_or._y:=0]
|
||||
224440 t.registers.read_write_demux.vc.OR2_tf[2]._y : 0 [by t.in.d.d[2].f:=1]
|
||||
224715 t.registers.read_write_demux.vc.ct.in[2] : 1 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=0]
|
||||
225038 t.registers.read_write_demux.vc.OR2_tf[3]._y : 0 [by t.in.d.d[3].f:=1]
|
||||
228964 t.registers.read_write_demux.vc.OR2_tf[0]._y : 0 [by t.in.d.d[0].t:=1]
|
||||
229419 t.registers.read_write_demux.vc.ct.in[0] : 1 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=0]
|
||||
229431 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 0 [by t.registers.read_write_demux.vc.ct.in[0]:=1]
|
||||
229835 t.registers.read_write_demux.vc.ct.tmp[4] : 1 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=0]
|
||||
244034 t.registers.read_write_demux.vc.ct.in[3] : 1 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=0]
|
||||
244046 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 0 [by t.registers.read_write_demux.vc.ct.in[3]:=1]
|
||||
249962 t.registers.read_write_demux.vc.ct.tmp[5] : 1 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=0]
|
||||
254238 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 0 [by t.registers.read_write_demux.vc.ct.tmp[5]:=1]
|
||||
257137 t.registers.read_write_demux._in_v : 1 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=0]
|
||||
257139 t.registers.read_write_demux.c_el._y : 0 [by t.registers.read_write_demux._in_v:=1]
|
||||
261432 t.registers.read_write_demux.in_v_buf._y : 0 [by t.registers.read_write_demux._in_v:=1]
|
||||
261674 t.registers.read_write_demux._in_c_v_ : 1 [by t.registers.read_write_demux.c_el._y:=0]
|
||||
262681 t.in.v : 1 [by t.registers.read_write_demux.in_v_buf._y:=0]
|
||||
279712 t.registers.read_write_demux.c_buf_t.buf1._y : 0 [by t.in.d.d[4].t:=1]
|
||||
283211 t.registers.read_write_demux._c_t_buf[0] : 1 [by t.registers.read_write_demux.c_buf_t.buf1._y:=0]
|
||||
283286 t.registers.read_write_demux.out1_f_buf_func[3]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
|
||||
283349 t.registers.read_write_demux.out1_t_buf_func[1]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
|
||||
283351 t.registers.read_write_demux.out1_t_buf_func[1].y : 1 [by t.registers.read_write_demux.out1_t_buf_func[1]._y:=0]
|
||||
283377 t.registers.read_write_demux.out1_f_buf_func[2]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
|
||||
283556 t.registers.read_write_demux.out1_t_buf_func[0]._y : 0 [by t.registers.read_write_demux._c_t_buf[0]:=1]
|
||||
283557 t.registers.read_write_demux.out1_t_buf_func[0].y : 1 [by t.registers.read_write_demux.out1_t_buf_func[0]._y:=0]
|
||||
288549 t.registers.read_write_demux.out1_f_buf_func[3].y : 1 [by t.registers.read_write_demux.out1_f_buf_func[3]._y:=0]
|
||||
327294 t.registers.read_write_demux.out1_f_buf_func[2].y : 1 [by t.registers.read_write_demux.out1_f_buf_func[2]._y:=0]
|
||||
Node `t.registers._clock' not found
|
||||
Node `t.registers._out_encoder[0]' not found
|
||||
Node `t.registers._out_encoder[1]' not found
|
||||
Node `t.registers._out_encoder[2]' not found
|
||||
Node `t.registers._out_encoder[3]' not found
|
||||
327294 t.in.d.d[0].t : 0
|
||||
327294 t.in.d.d[4].t : 0
|
||||
327294 t.in.d.d[2].f : 0
|
||||
327294 t.in.d.d[1].t : 0
|
||||
327294 t.in.d.d[3].f : 0
|
||||
327305 t.registers.read_write_demux.c_buf_t.buf1._y : 1 [by t.in.d.d[4].t:=0]
|
||||
327310 t.registers.read_write_demux.vc.OR2_tf[3]._y : 1 [by t.in.d.d[3].f:=0]
|
||||
327361 t.registers.read_write_demux.vc.OR2_tf[2]._y : 1 [by t.in.d.d[2].f:=0]
|
||||
327664 t.registers.read_write_demux.c_f_c_t_or._y : 1 [by t.in.d.d[4].t:=0]
|
||||
327838 t.registers.read_write_demux.vc.ct.in[3] : 0 [by t.registers.read_write_demux.vc.OR2_tf[3]._y:=1]
|
||||
327842 t.registers.read_write_demux.vc.OR2_tf[0]._y : 1 [by t.in.d.d[0].t:=0]
|
||||
329796 t.registers.read_write_demux.vc.ct.in[2] : 0 [by t.registers.read_write_demux.vc.OR2_tf[2]._y:=1]
|
||||
329935 t.registers.read_write_demux.vc.OR2_tf[1]._y : 1 [by t.in.d.d[1].t:=0]
|
||||
329937 t.registers.read_write_demux.vc.ct.in[1] : 0 [by t.registers.read_write_demux.vc.OR2_tf[1]._y:=1]
|
||||
331867 t.registers.read_write_demux._c_t_buf[0] : 0 [by t.registers.read_write_demux.c_buf_t.buf1._y:=1]
|
||||
342837 t.registers.read_write_demux.vc.ct.C2Els[1]._y : 1 [by t.registers.read_write_demux.vc.ct.in[2]:=0]
|
||||
351767 t.registers.read_write_demux.vc.ct.in[0] : 0 [by t.registers.read_write_demux.vc.OR2_tf[0]._y:=1]
|
||||
351770 t.registers.read_write_demux.vc.ct.C2Els[0]._y : 1 [by t.registers.read_write_demux.vc.ct.in[0]:=0]
|
||||
351799 t.registers.read_write_demux.vc.ct.tmp[4] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[0]._y:=1]
|
||||
354544 t.registers.read_write_demux._c_v : 0 [by t.registers.read_write_demux.c_f_c_t_or._y:=1]
|
||||
403795 t.registers.read_write_demux.vc.ct.tmp[5] : 0 [by t.registers.read_write_demux.vc.ct.C2Els[1]._y:=1]
|
||||
404112 t.registers.read_write_demux.vc.ct.C2Els[2]._y : 1 [by t.registers.read_write_demux.vc.ct.tmp[5]:=0]
|
||||
405713 t.registers.read_write_demux._in_v : 0 [by t.registers.read_write_demux.vc.ct.C2Els[2]._y:=1]
|
||||
405757 t.registers.read_write_demux.c_el._y : 1 [by t.registers.read_write_demux._in_v:=0]
|
||||
405866 t.registers.read_write_demux.in_v_buf._y : 1 [by t.registers.read_write_demux._in_v:=0]
|
||||
408518 t.registers.read_write_demux._in_c_v_ : 0 [by t.registers.read_write_demux.c_el._y:=1]
|
||||
419549 t.in.v : 0 [by t.registers.read_write_demux.in_v_buf._y:=1]
|
||||
[3] clock checked
|
||||
Node `t.registers._clock' not found
|
||||
Node `t.registers.ff[0].q' not found
|
||||
Node `t.registers.ff[1].q' not found
|
||||
File diff suppressed because it is too large.
Load diff
@@ -33,7 +33,7 @@ open tmpl::dataflow_neuro;
|
||||
// 2 bits encoder, 2 bits long words, 2 delays????
|
||||
defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[1<<2]; bool? dly_cfg[2]){
|
||||
|
||||
register_rw_v2<2,2,2> registers(.in=in,.data = data);
|
||||
register_w<2,2,2> registers(.in=in,.data = data);
|
||||
//Low active Reset
|
||||
bool _reset_B;
|
||||
power _supply;
|
||||
|
||||
@@ -2,12 +2,12 @@ watchall
|
||||
system "echo '[0] start test'"
|
||||
|
||||
set-qdi-channel-neutral "t.in" 5
|
||||
set-qdi-channel-neutral "t._in_write" 5
|
||||
set-qdi-channel-neutral "t._in_read" 5
|
||||
|
||||
set t.data[0].d[0] 0
|
||||
set t.data[0].d[1] 0
|
||||
set t.data[1].d[0] 0
|
||||
set t.data[1].d[1] 0
|
||||
|
||||
set t.registers._in_write.a 0
|
||||
set t.registers._in_read.a 0
|
||||
set t.registers._in_write.v 0
|
||||
|
||||
@@ -1,816 +1,28 @@
|
||||
0 GND : 0
|
||||
0 Reset : 1
|
||||
0 Vdd : 1
|
||||
1 t._reset_B : 0 [by Reset:=1]
|
||||
3 t.registers.reset_buf_BXX._y : 1 [by t._reset_B:=0]
|
||||
4756 t.registers._reset_mem_BX : 0 [by t.registers.reset_buf_BXX._y:=1]
|
||||
5893 t.registers.reset_bufarray.buf3._y : 1 [by t.registers._reset_mem_BX:=0]
|
||||
6007 t.registers._reset_mem_BXX[0] : 0 [by t.registers.reset_bufarray.buf3._y:=1]
|
||||
6011 t.registers.ff[0]._mqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
6020 t.registers.ff[5]._sqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
6022 t.registers.ff[6]._sqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
6023 t.registers.ff[2]._sqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
6026 t.registers.ff[0]._mqi : 0 [by t.registers.ff[0]._mqib:=1]
|
||||
6027 t.registers.ff[3]._mqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
6046 t.registers.ff[6]._mqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
6047 t.registers.ff[4]._mqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
6054 t.registers.ff[2]._mqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
6077 t.registers.ff[6]._sqi : 0 [by t.registers.ff[6]._sqib:=1]
|
||||
6422 t.registers.ff[4]._sqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
6423 t.registers.ff[4]._sqi : 0 [by t.registers.ff[4]._sqib:=1]
|
||||
6423 t.data[2].d[0] : 0 [by t.registers.ff[4]._sqib:=1]
|
||||
6469 t.registers.ff[4]._mqi : 0 [by t.registers.ff[4]._mqib:=1]
|
||||
6498 t.registers.ff[5]._mqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
6705 t.registers.ff[4].q_B : 1 [by t.data[2].d[0]:=0]
|
||||
7093 t.registers.reset_buf_BX._y : 1 [by t._reset_B:=0]
|
||||
7096 t.registers._reset_BX : 0 [by t.registers.reset_buf_BX._y:=1]
|
||||
7266 t.registers.ff[5]._mqi : 0 [by t.registers.ff[5]._mqib:=1]
|
||||
7733 t.registers.ff[7]._sqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
8284 t.data[3].d[1] : 0 [by t.registers.ff[7]._sqib:=1]
|
||||
9238 t.registers.ff[7].q_B : 1 [by t.data[3].d[1]:=0]
|
||||
9355 t.registers.word_selector_t[7]._y : 1 [by t.data[3].d[1]:=0]
|
||||
10436 t.registers.word_selector_t[7].y : 0 [by t.registers.word_selector_t[7]._y:=1]
|
||||
10468 t.registers.output_buf.reset_buf._y : 1 [by t._reset_B:=0]
|
||||
12068 t.registers.ff[3]._sqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
12086 t.data[1].d[1] : 0 [by t.registers.ff[3]._sqib:=1]
|
||||
13050 t.registers.ff[3]._sqi : 0 [by t.registers.ff[3]._sqib:=1]
|
||||
15136 t.registers.ff[0]._sqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
16089 t.registers.ff[3].q_B : 1 [by t.data[1].d[1]:=0]
|
||||
16099 t.registers.word_selector_t[3]._y : 1 [by t.data[1].d[1]:=0]
|
||||
19731 t.registers.ff[1]._sqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
19872 t.data[1].d[0] : 0 [by t.registers.ff[2]._sqib:=1]
|
||||
19934 t.data[0].d[1] : 0 [by t.registers.ff[1]._sqib:=1]
|
||||
20003 t.registers.ff[1].q_B : 1 [by t.data[0].d[1]:=0]
|
||||
20011 t.registers.ff[2].q_B : 1 [by t.data[1].d[0]:=0]
|
||||
20233 t.registers.ff[1]._sqi : 0 [by t.registers.ff[1]._sqib:=1]
|
||||
20389 t.registers.ff[6]._mqi : 0 [by t.registers.ff[6]._mqib:=1]
|
||||
20859 t.registers.word_selector_t[3].y : 0 [by t.registers.word_selector_t[3]._y:=1]
|
||||
21726 t.registers.word_selector_t[2]._y : 1 [by t.data[1].d[0]:=0]
|
||||
21737 t.registers.word_selector_t[2].y : 0 [by t.registers.word_selector_t[2]._y:=1]
|
||||
26628 t.registers.word_selector_t[4]._y : 1 [by t.data[2].d[0]:=0]
|
||||
30174 t.registers.ff[7]._sqi : 0 [by t.registers.ff[7]._sqib:=1]
|
||||
30839 t.registers.ff[3]._mqi : 0 [by t.registers.ff[3]._mqib:=1]
|
||||
35803 t.registers.ff[2]._sqi : 0 [by t.registers.ff[2]._sqib:=1]
|
||||
36720 t.data[0].d[0] : 0 [by t.registers.ff[0]._sqib:=1]
|
||||
36735 t.registers.ff[0].q_B : 1 [by t.data[0].d[0]:=0]
|
||||
36924 t.registers.word_selector_t[0]._y : 1 [by t.data[0].d[0]:=0]
|
||||
36925 t.registers.word_selector_t[0].y : 0 [by t.registers.word_selector_t[0]._y:=1]
|
||||
36962 t.registers.bitselector_t[0].or2s[0]._y : 1 [by t.registers.word_selector_t[0].y:=0]
|
||||
37701 t.registers.bitselector_t[0].tmp[4] : 0 [by t.registers.bitselector_t[0].or2s[0]._y:=1]
|
||||
42951 t.data[2].d[1] : 0 [by t.registers.ff[5]._sqib:=1]
|
||||
43063 t.registers.word_selector_t[5]._y : 1 [by t.data[2].d[1]:=0]
|
||||
43103 t.registers.word_selector_t[5].y : 0 [by t.registers.word_selector_t[5]._y:=1]
|
||||
43360 t.registers.bitselector_t[1].or2s[1]._y : 1 [by t.registers.word_selector_t[5].y:=0]
|
||||
43447 t.registers.bitselector_t[1].tmp[5] : 0 [by t.registers.bitselector_t[1].or2s[1]._y:=1]
|
||||
49268 t.registers.ff[5]._sqi : 0 [by t.registers.ff[5]._sqib:=1]
|
||||
50105 t.registers.ff[1]._mqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
50399 t.registers.ff[1]._mqi : 0 [by t.registers.ff[1]._mqib:=1]
|
||||
54768 t.registers.ff[2]._mqi : 0 [by t.registers.ff[2]._mqib:=1]
|
||||
56280 t.registers.word_selector_t[1]._y : 1 [by t.data[0].d[1]:=0]
|
||||
56281 t.registers.word_selector_t[1].y : 0 [by t.registers.word_selector_t[1]._y:=1]
|
||||
57675 t.data[3].d[0] : 0 [by t.registers.ff[6]._sqib:=1]
|
||||
58087 t.registers.bitselector_t[1].or2s[0]._y : 1 [by t.registers.word_selector_t[1].y:=0]
|
||||
58677 t.registers.bitselector_t[1].tmp[4] : 0 [by t.registers.bitselector_t[1].or2s[0]._y:=1]
|
||||
58855 t.registers.bitselector_t[1].or2s[2]._y : 1 [by t.registers.bitselector_t[1].tmp[4]:=0]
|
||||
58884 t.registers.ff[6].q_B : 1 [by t.data[3].d[0]:=0]
|
||||
59658 t.registers.bitselector_t[1].out : 0 [by t.registers.bitselector_t[1].or2s[2]._y:=1]
|
||||
59682 t.registers.word_selector_t[6]._y : 1 [by t.data[3].d[0]:=0]
|
||||
59846 t.registers.word_selector_t[6].y : 0 [by t.registers.word_selector_t[6]._y:=1]
|
||||
60037 t.registers.ff[0]._sqi : 0 [by t.registers.ff[0]._sqib:=1]
|
||||
64938 t.registers.output_buf._reset_BX : 0 [by t.registers.output_buf.reset_buf._y:=1]
|
||||
64960 t.registers.output_buf.inack_ctl._y : 1 [by t.registers.output_buf._reset_BX:=0]
|
||||
65807 t.registers.ack_read_and.b : 0 [by t.registers.output_buf.inack_ctl._y:=1]
|
||||
67133 t.registers.output_buf.reset_bufarray.buf1._y : 1 [by t.registers.output_buf._reset_BX:=0]
|
||||
67266 t.registers.output_buf._reset_BXX[0] : 0 [by t.registers.output_buf.reset_bufarray.buf1._y:=1]
|
||||
67273 t.registers.output_buf.f_buf_func[0]._y : 1 [by t.registers.output_buf._reset_BXX[0]:=0]
|
||||
67296 t.registers.output_buf.f_buf_func[1]._y : 1 [by t.registers.output_buf._reset_BXX[0]:=0]
|
||||
67364 t.out.d.d[0].f : 0 [by t.registers.output_buf.f_buf_func[0]._y:=1]
|
||||
67487 t.registers.output_buf.t_buf_func[3]._y : 1 [by t.registers.output_buf._reset_BXX[0]:=0]
|
||||
67494 t.out.d.d[3].t : 0 [by t.registers.output_buf.t_buf_func[3]._y:=1]
|
||||
67625 t.registers.output_buf.t_buf_func[1]._y : 1 [by t.registers.output_buf._reset_BXX[0]:=0]
|
||||
69485 t.out.d.d[1].f : 0 [by t.registers.output_buf.f_buf_func[1]._y:=1]
|
||||
70412 t.out.d.d[1].t : 0 [by t.registers.output_buf.t_buf_func[1]._y:=1]
|
||||
71373 t.registers.ff[7]._mqib : 1 [by t.registers._reset_mem_BXX[0]:=0]
|
||||
71479 t.registers.ff[7]._mqi : 0 [by t.registers.ff[7]._mqib:=1]
|
||||
73979 t.registers.output_buf.f_buf_func[2]._y : 1 [by t.registers.output_buf._reset_BXX[0]:=0]
|
||||
74057 t.out.d.d[2].f : 0 [by t.registers.output_buf.f_buf_func[2]._y:=1]
|
||||
78414 t.registers.word_selector_t[4].y : 0 [by t.registers.word_selector_t[4]._y:=1]
|
||||
78689 t.registers.bitselector_t[0].or2s[1]._y : 1 [by t.registers.word_selector_t[4].y:=0]
|
||||
81382 t.registers.output_buf.t_buf_func[2]._y : 1 [by t.registers.output_buf._reset_BXX[0]:=0]
|
||||
81837 t.out.d.d[2].t : 0 [by t.registers.output_buf.t_buf_func[2]._y:=1]
|
||||
82928 t.registers.output_buf.t_buf_func[0]._y : 1 [by t.registers.output_buf._reset_BXX[0]:=0]
|
||||
82940 t.out.d.d[0].t : 0 [by t.registers.output_buf.t_buf_func[0]._y:=1]
|
||||
90463 t.registers.ff[5].q_B : 1 [by t.data[2].d[1]:=0]
|
||||
95935 t.registers.ack_read_and._y : 1 [by t.registers.ack_read_and.b:=0]
|
||||
96339 t.registers._in_a_read : 0 [by t.registers.ack_read_and._y:=1]
|
||||
97685 t.registers.bitselector_t[0].tmp[5] : 0 [by t.registers.bitselector_t[0].or2s[1]._y:=1]
|
||||
97697 t.registers.bitselector_t[0].or2s[2]._y : 1 [by t.registers.bitselector_t[0].tmp[5]:=0]
|
||||
103613 t.registers.bitselector_t[0].out : 0 [by t.registers.bitselector_t[0].or2s[2]._y:=1]
|
||||
124727 t.registers.output_buf.f_buf_func[3]._y : 1 [by t.registers.output_buf._reset_BXX[0]:=0]
|
||||
129003 t.out.d.d[3].f : 0 [by t.registers.output_buf.f_buf_func[3]._y:=1]
|
||||
t.registers._clock_word_temp[0] t.registers.ack_dly._a[1] t.registers._clock_temp_inv t.registers.ff[0].clk_B t.registers._clock[0] t.dly_cfg[1] t.registers.ff[0].d t.registers.ff[4].clk_B t.registers.word_selector_f[3].y t.registers.output_buf._in_vX[0] t.registers._out_encoder[0] t.registers.bitselector_f[1].out t.registers.clock_buffer[1].buf1._y t.registers.atree[2].in[1] t.registers.ff[6].clk_B t.registers.word_selector_f[1].y t.registers.address_propagator_f[1].y t.registers._in_v_temp_write t.registers.bitselector_f[0].out t.registers.address_propagator_t[0].y t.registers._out_encoder[2] t.registers.clk_dly.and2[1]._y t.registers.output_buf._en_X_f[0] t.registers._out_encoder[1] t.registers.val_input.ct.in[0] t.registers.ack_dly.dly[2]._y t.registers.atree[0].in[0] t.in.d.d[0].f t.registers.word_selector_f[0].y t.in.v t.registers.word_selector_f[0].a t.registers.word_selector_f[6].a t.registers.clk_dly.dly[1].a t.registers.output_buf._en t.registers._in_a_write t.registers._clock_word_temp[3] t.registers.word_selector_f[4].a t.registers.output_buf._out_a_BX_t[0] t.registers.val_input.ct.in[3] t.registers.word_to_read[0].y t.registers.ff[1].d t.registers.clock_buffer[0].buf1._y t.registers.word_selector_f[2].y t.registers.output_buf.vc.ct.in[3] t.registers.ack_read_and.a t.registers.address_propagator_f[0]._y t.registers.word_selector_f[2].a t.registers.address_propagator_t[1].y t.registers.atree[1].in[0] t.registers.ack_dly.dly[2].___y t.registers.bitselector_f[0].or2s[2]._y t.registers.output_buf.vc.ct.tmp[4] t.registers.output_buf.vc.ct.tmp[5] t.registers.ack_dly.mu2[0]._y t.in.d.d[1].f t.registers.address_propagator_t[0]._y t.out.v t.registers.val_input.OR2_tf[3]._y t.registers.clk_X.buf1._y t.registers._clock_temp t.registers.word_to_read[3].y t.registers._in_a_write_temp t.registers.word_to_read[1].y t.registers.ff[7]._clk_B t.registers.output_buf.vc.ct.in[0] t.in.a t.registers.atree[0].in[1] t.registers._out_encoder[3] t.registers.ff[1]._clk_B t.registers.clk_dly.dly[0]._y t.registers.word_selector_f[4].y t.registers.val_input.OR2_tf[2]._y t.registers.val_input.ct.in[2] t.registers.output_buf._in_v t.registers.clk_dly.dly[1]._y t.registers.output_buf.vc.OR2_tf[0]._y t.registers.word_to_read[1]._y t.registers.output_buf._out_a_BX_f[0] t.registers.bitselector_f[0].tmp[5] t.registers.bitselector_f[1].tmp[4] t.registers._clock_word_temp[1] t.registers.clk_dly.mu2[0]._s t.registers.output_buf.in.v t.registers.ack_dly.dly[0]._y t.registers.word_selector_f[7].y t.registers.ack_dly.dly[0].a t.registers.address_propagator_f[0].y t.registers.clock_buffer[2].buf1._y t.registers.output_buf.vc.ct.in[1] t.registers.clk_dly.dly[1].__y t.registers.word_to_read[2].y t.registers.ff[2].clk_B t.registers._in_a_temp t.registers.ff[6]._clk_B t.registers.output_buf._en_X_t[0] t.registers.clk_dly.mu2[0]._y t.dly_cfg[0] t.registers.word_selector_f[5].y t.registers.bitselector_f[0].tmp[4] t.registers.clock_buffer[3].buf1._y t.registers.val_input.ct.tmp[5] t.registers._in_v_temp t.registers.output_buf._out_a_B t.registers.ack_dly.dly[1]._y t.registers.and_encoder[0]._y t.registers.clk_dly._a[1] t.registers.bitselector_f[1].or2s[0]._y t.registers.output_buf.vc.ct.in[2] t.registers.ack_dly.dly[1].y t.registers.output_buf.out_a_B_buf_f.buf1._y t.registers.clk_switch.b t.registers.val_input.OR2_tf[1]._y t.registers.clk_dly.dly[0].__y t.registers.output_buf.vc.ct.C2Els[2]._y t.registers.word_selector_f[4]._y t.registers.clk_dly.dly[2].__y t.registers.atree[3].and2s[0]._y t.registers.word_to_read_X[0].buf1._y t.registers.ack_dly.dly[2].y t.registers.ff[4].__clk_B t.registers.word_selector_f[2]._y t.registers.val_input.ct.in[4] t.registers._clock_word_temp[2] t.registers.val_input_X.buf4._y t.registers.atree[2].and2s[0]._y t.registers.val_input.ct.tmp[6] t.registers.val_input.ct.in[1] t.registers.output_buf.en_buf_t.buf1._y t.registers.output_buf.vc.ct.C2Els[0]._y t.registers.word_selector_f[6].y t.registers.bitselector_f[1].or2s[1]._y t.registers.val_input.OR2_tf[0]._y t.out.a t.registers.ff[5]._clk_B t.registers.output_buf.vc.OR2_tf[2]._y t.registers.word_to_read[3]._y t.registers.bitselector_f[1].or2s[2]._y t.registers.word_to_read_X[2].buf1._y t.registers.ack_input_X.buf4._y t.registers.ack_dly.mu2[1]._s t.registers.bitselector_f[0].or2s[0]._y t.registers.clk_dly.dly[2].___y t.registers.val_input.ct.C2Els[0]._y t.registers.ack_dly.mu2[1]._y t.registers.ack_dly.dly[0].__y t.registers.word_selector_f[7]._y t.registers.clk_dly.and2[0]._y t.registers.ack_dly.dly[1].__y t.registers.clk_dly.dly[2]._y t.registers.ff[5].__clk_B t.registers.ack_dly.dly[1].___y t.registers.ff[4]._clk_B t.registers.word_selector_f[6]._y t.registers.clk_dly.dly[1].y t.registers.ff[3]._clk_B t.registers.clk_dly.dly[2].y t.registers.word_selector_f[1]._y t.registers.ack_dly.dly[0].___y t.registers.atree[1].and2s[0]._y t.registers.ff[2].__clk_B t.registers.output_buf.in_v_bufN.buf1._y t.registers.clk_switch._y t.registers.ff[7].__clk_B t.registers.clk_dlLine truncated
|
||||
t.registers.ack_dly.dly[3].bufchain[7].y t.registers.ack_dly.dly[2].bufchain[3]._y t.registers.clk_dly.dly[0].bufchain[2]._y t.registers.clk_dly.dly[5].bufchain[14].y t.registers.clk_dly.dly[0].bufchain[11]._y t.registers.clk_dly.dly[3].bufchain[0].y t.registers.clk_dly.dly[1].bufchain[12].y t.dly_cfg[1] t.registers.ack_dly.dly[5].bufchain[10].y t.registers.ff[0].d t.registers.ack_dly.dly[3].bufchain[10].y t.registers.ff[4].clk_B t.registers.val_chck[7].y t.registers.ack_dly.dly[0].bufchain[4].y t.registers.clk_dly.dly[4].bufchain[3].y t.registers.output_buf._in_vX[0] t.registers.ack_dly.dly[1].bufchain[12].y t.registers.clk_dly.dly[0].bufchain[10]._y t.registers.ff[6].clk_B t.registers.clock_buffer[1].buf1._y t.registers.ack_dly._a[2] t.registers.address_propagator_t[0].y t.registers.ack_dly.dly[5].bufchain[11].y t.registers.bitselector_f[0].out t.in.d.d[0].f t.in.v t.registers.ack_dly.dly[1].bufchain[2].y t.registers.or_encoder[2].a t.registers._clock[0] t.registers.ack_dly.dly[0].bufchain[3]._y t.registers.clk_dly.dly[4].bufchain[4]._y t.registers._in_v_temp_write t.registers.word_selector_f[0].a t.registers._in_a_write t.registers.clk_dly.dly[6].bufchain[7].y t.registers.clk_dly.dly[3].y t.registers.val_chck[3].y t.dly_cfg[2] t.registers.ack_dly.dly[4].bufchain[5].y t.registers._in_v_temp_buf[0] t.registers.clk_dly.dly[6].bufchain[14]._y t.registers.clk_dly.dly[5].bufchain[10].y t.registers.ack_dly.dly[3].bufchain[8].y t.registers.word_to_read[0].y t.registers.clk_dly.dly[5].bufchain[13].y t.registers.ack_dly.dly[6].bufchain[3]._y t.registers.ack_dly.dly[0].bufchain[5]._y t.registers.ack_dly.dly[3].bufchain[14].y t.registers.clk_dly.dly[2].bufchain[11]._y t.registers.ack_dly.dly[1].bufchain[0].y t.registers.clk_dly.dly[2].bufchain[3].y t.registers.clk_dly.dly[6].bufchain[5].y t.registers.ack_dly.dly[0].bufchain[12]._y t.registers.word_selector_f[2].y t.registers.output_buf.vc.ct.in[3] t.registers.clk_dly.dly[2].bufchain[13].y t.registers.atree[0].in[0] t.registers.clk_dly.dly[5].bufchain[4]._y t.registers.address_propagator_f[0]._y t.registers.clk_dly.dly[0].bufchain[8].y t.registers.clk_dly.dly[3].bufchain[1].y t.registers.ack_dly.dly[6].bufchain[1]._y t.registers.clk_dly.dly[3].bufchain[11].y t.registers.ack_dly.dly[2].bufchain[1].y t.registers.output_buf.vc.ct.tmp[4] t.registers.clk_dly.dly[2].bufchain[5].y t.registers.output_buf.vc.ct.tmp[5] t.registers.ack_dly.dly[4].bufchain[12]._y t.registers.ack_dly.mu2[0]._y t.registers.ack_dly.dly[6].bufchain[1].y t.registers.clk_dly.dly[4].bufchain[0].y t.registers.clk_dly.dly[3].bufchain[5]._y t.registers.ack_dly.dly[2].bufchain[11]._y t.in.d.d[1].f t.registers.clk_dly.dly[6].bufchain[10].y t.registers.ack_dly.dly[0].bufchain[5].y t.registers.address_propagator_t[0]._y t.registers.ack_dly.dly[1].bufchain[6]._y t.registers.val_input.OR2_tf[3]._y t.registers.clk_dly.dly[2].bufchain[2].y t.registers.clk_dly.dly[6].bufchain[8]._y t.registers.clk_dly.dly[1].bufchain[12]._y t.registers.ack_dly.dly[0].bufchain[6].y t.registers.word_to_read[3].y t.registers.clk_dly._a[2] t.registers._clock_temp t.registers.ff[7]._clk_B t.in.a t.registers.address_propagator_f[1].y t.registers.ack_dly.dly[3].bufchain[13].y t.registers.val_chck[6].y t.registers.ff[1]._clk_B t.registers.word_selector_f[1].y t.registers.ff[1].d t.registers.clk_dly.dly[6].bufchain[1].y t.registers.output_buf._in_v t.registers.clk_dly.dly[6].bufchain[6].y t.registers.ack_dly.dly[0].bufchain[2].y t.registers.atree[0].in[1] t.registers.word_to_read[1]._y t.registers.clk_dly.dly[1].bufchain[11].y t.registers.address_propagator_t[1].y t.registers.clk_dly.dly[3].a t.registers.clk_dly.dly[1].bufchain[2]._y t.registers.clk_dly.dly[1].bufchain[14]._y t.registers.output_buf._out_a_BX_f[0] t.registers.ack_dly.dly[6].bufchain[8].y t.registers.clk_dly.dly[4].bufchain[9].y t.registers._clock_word_temp[3] t.registers.clk_dly.dly[3].bufchain[3]._y t.registers.ack_dly.dly[4].bufchain[2].y t.registers.clk_dly.dly[2].bufchain[10]._y t.registers.ack_dly.dly[1].bufchain[1].y t.registers.ack_dly.dly[5].bufchain[6].y t.registers.ack_dly.dly[4].bufchain[1].y t.registers.bitselector_f[1].tmp[4] t.registers.ack_dly.dly[2].bufchain[4].y t.registers.ack_dly.dly[0].bufchain[11].y t.registers.clk_dly.dly[2].bufchain[0].y t.registers.clk_dly.dly[6].bufchain[2].y t.registers._clock_word_temp[1] t.registers.clk_dly.dly[2].bufchain[14]._y t.registers.word_selector_f[2].a t.registers.ack_dly.dly[2].bufchain[9]._y t.registers.clk_dly.dly[3].bufchain[6].y t.registers.bitselector_f[0].tmp[5] t.registers.word_selector_f[7].y t.registers.clk_dly.dly[5].bufchain[7]._y t.registers.clk_dly.dly[4].bufchain[13].y t.registers.val_chck[6]._y t.registers.ack_dly.dly[2].bufchain[12].y t.registers.ack_dly.dly[0].a t.registers.clk_dly.dly[1].bufchain[1].y t.registers.ack_dly.dly[1].bufchain[15]._y t.registers.clk_dly.dly[6].bufchain[13].y t.registers.ack_dly.dly[4].bufchain[9].y t.registers.clk_dly.dly[6].bufchain[3].y t.registers.ack_dly.dly[1].bufchainLine truncated
|
||||
[0] start test
|
||||
----------------------------------------------------------
|
||||
129003 t.in.d.d[0].f : 0
|
||||
129003 Reset : 0
|
||||
129003 t.out.v : 0
|
||||
129003 t.in.d.d[1].f : 0
|
||||
129003 t.registers.atree[0].in[1] : 0
|
||||
129003 t.registers.atree[1].in[0] : 0
|
||||
129003 t.out.a : 0
|
||||
129003 t.dly_cfg[1] : 1
|
||||
129003 t.registers.ff[0].d : 0
|
||||
129003 t.registers.atree[0].in[0] : 0
|
||||
129003 t.dly_cfg[0] : 1
|
||||
129003 t.registers.ack_read_and.a : 0
|
||||
129003 t.registers.ff[1].d : 0
|
||||
129003 t.registers.clk_switch.b : 0
|
||||
129003 t.registers.atree[2].in[1] : 0
|
||||
129004 t.registers.address_propagator_f[0]._y : 1 [by t.registers.atree[0].in[0]:=0]
|
||||
129005 t.registers.atree[0].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0]
|
||||
129005 t.registers.atree[2].and2s[0]._y : 1 [by t.registers.atree[0].in[0]:=0]
|
||||
129006 t.registers.address_propagator_f[0].y : 0 [by t.registers.address_propagator_f[0]._y:=1]
|
||||
129008 t.registers._out_encoder[2] : 0 [by t.registers.atree[2].and2s[0]._y:=1]
|
||||
129014 t.registers.clk_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1]
|
||||
129019 t.registers.word_to_read[3]._y : 1 [by t.registers.ack_read_and.a:=0]
|
||||
129037 t.registers.and_encoder[2]._y : 1 [by t.registers._out_encoder[2]:=0]
|
||||
129070 t.registers.word_to_read[1]._y : 1 [by t.registers.ack_read_and.a:=0]
|
||||
129078 t.registers.output_buf._out_a_B : 1 [by t.out.a:=0]
|
||||
129122 t.registers.output_buf.out_a_B_buf_t.buf1._y : 0 [by t.registers.output_buf._out_a_B:=1]
|
||||
129141 t.registers.clk_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1]
|
||||
129169 t.registers.address_propagator_t[0]._y : 1 [by t.registers.atree[1].in[0]:=0]
|
||||
129170 t.registers.address_propagator_t[0].y : 0 [by t.registers.address_propagator_t[0]._y:=1]
|
||||
129223 t.registers.word_to_read[1].y : 0 [by t.registers.word_to_read[1]._y:=1]
|
||||
129245 t.registers.word_to_read_X[1].buf1._y : 1 [by t.registers.word_to_read[1].y:=0]
|
||||
129246 t.registers.word_selector_f[2].a : 0 [by t.registers.word_to_read_X[1].buf1._y:=1]
|
||||
129336 t.registers.word_to_read[3].y : 0 [by t.registers.word_to_read[3]._y:=1]
|
||||
129348 t.registers.ack_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1]
|
||||
129373 t.registers.word_to_read[0]._y : 1 [by t.registers.ack_read_and.a:=0]
|
||||
129387 t.registers.output_buf.vc.OR2_tf[2]._y : 1 [by t.registers.address_propagator_t[0].y:=0]
|
||||
129495 t.registers.word_to_read_X[3].buf1._y : 1 [by t.registers.word_to_read[3].y:=0]
|
||||
129531 t.registers.val_input.OR2_tf[1]._y : 1 [by t.registers.ff[1].d:=0]
|
||||
129551 t.registers.ack_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1]
|
||||
129676 t.registers.val_input.ct.in[1] : 0 [by t.registers.val_input.OR2_tf[1]._y:=1]
|
||||
130252 t.registers.address_propagator_f[1]._y : 1 [by t.registers.atree[0].in[1]:=0]
|
||||
130638 t.registers._clock_word_temp[2] : 0 [by t.registers.and_encoder[2]._y:=1]
|
||||
130674 t.registers.output_buf.vc.ct.in[2] : 0 [by t.registers.output_buf.vc.OR2_tf[2]._y:=1]
|
||||
130827 t.registers.word_selector_f[2]._y : 1 [by t.registers.word_selector_f[2].a:=0]
|
||||
130828 t.registers.word_selector_f[2].y : 0 [by t.registers.word_selector_f[2]._y:=1]
|
||||
131438 t.registers.ack_write_and._y : 1 [by t.registers.clk_switch.b:=0]
|
||||
131644 t.registers.word_to_read[2]._y : 1 [by t.registers.ack_read_and.a:=0]
|
||||
131727 t.registers.word_selector_f[6].a : 0 [by t.registers.word_to_read_X[3].buf1._y:=1]
|
||||
131741 t.registers.word_selector_f[7]._y : 1 [by t.registers.word_selector_f[6].a:=0]
|
||||
131748 t.registers.word_selector_f[7].y : 0 [by t.registers.word_selector_f[7]._y:=1]
|
||||
131806 t.registers.word_to_read[2].y : 0 [by t.registers.word_to_read[2]._y:=1]
|
||||
131839 t.registers.output_buf.out_a_B_buf_f.buf1._y : 0 [by t.registers.output_buf._out_a_B:=1]
|
||||
131902 t._reset_B : 1 [by Reset:=0]
|
||||
131903 t.registers.reset_buf_BX._y : 0 [by t._reset_B:=1]
|
||||
131903 t.registers.output_buf.reset_buf._y : 0 [by t._reset_B:=1]
|
||||
131903 t.registers.reset_buf_BXX._y : 0 [by t._reset_B:=1]
|
||||
131904 t.registers._reset_mem_BX : 1 [by t.registers.reset_buf_BXX._y:=0]
|
||||
131966 t.registers.word_to_read_X[2].buf1._y : 1 [by t.registers.word_to_read[2].y:=0]
|
||||
132090 t.registers.output_buf._reset_BX : 1 [by t.registers.output_buf.reset_buf._y:=0]
|
||||
132091 t.registers.output_buf.reset_bufarray.buf1._y : 0 [by t.registers.output_buf._reset_BX:=1]
|
||||
132502 t.registers.atree[3].and2s[0]._y : 1 [by t.registers.atree[1].in[0]:=0]
|
||||
132507 t.registers._out_encoder[3] : 0 [by t.registers.atree[3].and2s[0]._y:=1]
|
||||
WARNING: weak-interference `t.registers.output_buf.t_buf_func[3]._y'
|
||||
>> cause: t.registers.output_buf._reset_BXX[0] (val: 1)
|
||||
>> time: 132944
|
||||
WARNING: weak-interference `t.registers.output_buf.f_buf_func[0]._y'
|
||||
>> cause: t.registers.output_buf._reset_BXX[0] (val: 1)
|
||||
>> time: 132944
|
||||
WARNING: weak-interference `t.registers.output_buf.f_buf_func[1]._y'
|
||||
>> cause: t.registers.output_buf._reset_BXX[0] (val: 1)
|
||||
>> time: 132944
|
||||
WARNING: weak-interference `t.registers.output_buf.f_buf_func[3]._y'
|
||||
>> cause: t.registers.output_buf._reset_BXX[0] (val: 1)
|
||||
>> time: 132944
|
||||
132944 t.registers.output_buf._reset_BXX[0] : 1 [by t.registers.output_buf.reset_bufarray.buf1._y:=0]
|
||||
WARNING: weak-interference `t.out.d.d[3].t'
|
||||
>> cause: t.registers.output_buf.t_buf_func[3]._y (val: X)
|
||||
>> time: 132945
|
||||
132945 t.registers.output_buf.t_buf_func[3]._y : X [by t.registers.output_buf._reset_BXX[0]:=1]
|
||||
132948 t.out.d.d[3].t : X [by t.registers.output_buf.t_buf_func[3]._y:=X]
|
||||
WARNING: weak-interference `t.out.d.d[0].f'
|
||||
>> cause: t.registers.output_buf.f_buf_func[0]._y (val: X)
|
||||
>> time: 132961
|
||||
132961 t.registers.output_buf.f_buf_func[0]._y : X [by t.registers.output_buf._reset_BXX[0]:=1]
|
||||
133084 t.registers.address_propagator_f[1].y : 0 [by t.registers.address_propagator_f[1]._y:=1]
|
||||
133298 t.registers.output_buf._en : 1 [by t.out.v:=0]
|
||||
133299 t.registers.output_buf.en_buf_t.buf1._y : 0 [by t.registers.output_buf._en:=1]
|
||||
133341 t.registers.output_buf._en_X_t[0] : 1 [by t.registers.output_buf.en_buf_t.buf1._y:=0]
|
||||
133398 t.registers.and_encoder[3]._y : 1 [by t.registers._out_encoder[3]:=0]
|
||||
133538 t.registers.atree[1].and2s[0]._y : 1 [by t.registers.atree[0].in[1]:=0]
|
||||
133565 t.registers.address_propagator_t[1]._y : 1 [by t.registers.ack_read_and.a:=0]
|
||||
133660 t.registers.address_propagator_t[1].y : 0 [by t.registers.address_propagator_t[1]._y:=1]
|
||||
133902 t.out.d.d[0].f : X [by t.registers.output_buf.f_buf_func[0]._y:=X]
|
||||
133995 t.registers.output_buf.vc.OR2_tf[3]._y : 1 [by t.registers.address_propagator_t[1].y:=0]
|
||||
134003 t.registers.output_buf.vc.ct.in[3] : 0 [by t.registers.output_buf.vc.OR2_tf[3]._y:=1]
|
||||
134037 t.registers.output_buf.vc.ct.C2Els[1]._y : 1 [by t.registers.output_buf.vc.ct.in[3]:=0]
|
||||
134146 t.registers._reset_BX : 1 [by t.registers.reset_buf_BX._y:=0]
|
||||
134266 t.registers.val_input.OR2_tf[0]._y : 1 [by t.registers.ff[0].d:=0]
|
||||
135184 t.registers.val_input.ct.in[0] : 0 [by t.registers.val_input.OR2_tf[0]._y:=1]
|
||||
135188 t.registers.val_input.ct.C2Els[0]._y : 1 [by t.registers.val_input.ct.in[0]:=0]
|
||||
WARNING: weak-interference `t.out.d.d[1].f'
|
||||
>> cause: t.registers.output_buf.f_buf_func[1]._y (val: X)
|
||||
>> time: 135517
|
||||
135517 t.registers.output_buf.f_buf_func[1]._y : X [by t.registers.output_buf._reset_BXX[0]:=1]
|
||||
136086 t.registers.reset_bufarray.buf3._y : 0 [by t.registers._reset_mem_BX:=1]
|
||||
136215 t.registers._clock_word_temp[3] : 0 [by t.registers.and_encoder[3]._y:=1]
|
||||
136992 t.registers.clock_buffer[2].buf1._y : 1 [by t.registers._clock_word_temp[2]:=0]
|
||||
137040 t.registers.ff[4].clk_B : 0 [by t.registers.clock_buffer[2].buf1._y:=1]
|
||||
137043 t.registers.ff[4]._clk_B : 1 [by t.registers.ff[4].clk_B:=0]
|
||||
137218 t.registers.ff[5]._clk_B : 1 [by t.registers.ff[4].clk_B:=0]
|
||||
137915 t.out.d.d[1].f : X [by t.registers.output_buf.f_buf_func[1]._y:=X]
|
||||
138591 t.registers.word_selector_f[3]._y : 1 [by t.registers.word_selector_f[2].a:=0]
|
||||
139096 t.registers.word_selector_f[6]._y : 1 [by t.registers.word_selector_f[6].a:=0]
|
||||
139301 t.registers._reset_mem_BXX[0] : 1 [by t.registers.reset_bufarray.buf3._y:=0]
|
||||
WARNING: weak-interference `t.out.d.d[3].f'
|
||||
>> cause: t.registers.output_buf.f_buf_func[3]._y (val: X)
|
||||
>> time: 141305
|
||||
141305 t.registers.output_buf.f_buf_func[3]._y : X [by t.registers.output_buf._reset_BXX[0]:=1]
|
||||
142044 t.registers.val_input.OR2_tf[3]._y : 1 [by t.registers.atree[2].in[1]:=0]
|
||||
142132 t.out.d.d[3].f : X [by t.registers.output_buf.f_buf_func[3]._y:=X]
|
||||
142217 t.registers.val_input.ct.in[3] : 0 [by t.registers.val_input.OR2_tf[3]._y:=1]
|
||||
142805 t.registers.output_buf._out_a_BX_f[0] : 1 [by t.registers.output_buf.out_a_B_buf_t.buf1._y:=0]
|
||||
144542 t.registers.word_selector_f[3].y : 0 [by t.registers.word_selector_f[3]._y:=1]
|
||||
147271 t.registers._out_encoder[1] : 0 [by t.registers.atree[1].and2s[0]._y:=1]
|
||||
147455 t.registers.and_encoder[1]._y : 1 [by t.registers._out_encoder[1]:=0]
|
||||
147456 t.registers._clock_word_temp[1] : 0 [by t.registers.and_encoder[1]._y:=1]
|
||||
147529 t.registers.clock_buffer[1].buf1._y : 1 [by t.registers._clock_word_temp[1]:=0]
|
||||
147533 t.registers.ff[2].clk_B : 0 [by t.registers.clock_buffer[1].buf1._y:=1]
|
||||
147629 t.registers.ff[3]._clk_B : 1 [by t.registers.ff[2].clk_B:=0]
|
||||
147765 t.registers.ff[3].__clk_B : 0 [by t.registers.ff[3]._clk_B:=1]
|
||||
147924 t.registers.output_buf.vc.ct.tmp[5] : 0 [by t.registers.output_buf.vc.ct.C2Els[1]._y:=1]
|
||||
149049 t.registers.word_to_read[0].y : 0 [by t.registers.word_to_read[0]._y:=1]
|
||||
149050 t.registers.word_to_read_X[0].buf1._y : 1 [by t.registers.word_to_read[0].y:=0]
|
||||
149117 t.registers.ff[5].__clk_B : 0 [by t.registers.ff[5]._clk_B:=1]
|
||||
152928 t.registers.val_input.OR2_tf[4]._y : 1 [by t.registers.clk_switch.b:=0]
|
||||
153169 t.registers.val_input.ct.in[4] : 0 [by t.registers.val_input.OR2_tf[4]._y:=1]
|
||||
153396 t.registers.output_buf._out_a_BX_t[0] : 1 [by t.registers.output_buf.out_a_B_buf_f.buf1._y:=0]
|
||||
155883 t.registers.clk_switch._y : 1 [by t.registers.clk_switch.b:=0]
|
||||
158020 t.registers.ff[4].__clk_B : 0 [by t.registers.ff[4]._clk_B:=1]
|
||||
159842 t.registers._in_v_temp_write : 0 [by t.registers.clk_switch._y:=1]
|
||||
159854 t.registers.clk_dly.and2[0]._y : 1 [by t.registers._in_v_temp_write:=0]
|
||||
163754 t.registers.clk_dly.dly[0].a : 0 [by t.registers.clk_dly.and2[0]._y:=1]
|
||||
164783 t.registers.clk_dly.dly[0]._y : 1 [by t.registers.clk_dly.dly[0].a:=0]
|
||||
164784 t.registers.clk_dly.dly[0].__y : 0 [by t.registers.clk_dly.dly[0]._y:=1]
|
||||
164840 t.registers.clk_dly.dly[0].___y : 1 [by t.registers.clk_dly.dly[0].__y:=0]
|
||||
166748 t.registers.word_selector_f[4].a : 0 [by t.registers.word_to_read_X[2].buf1._y:=1]
|
||||
166749 t.registers.word_selector_f[4]._y : 1 [by t.registers.word_selector_f[4].a:=0]
|
||||
166785 t.registers.word_selector_f[5]._y : 1 [by t.registers.word_selector_f[4].a:=0]
|
||||
166786 t.registers.word_selector_f[5].y : 0 [by t.registers.word_selector_f[5]._y:=1]
|
||||
168096 t.registers.word_selector_f[0].a : 0 [by t.registers.word_to_read_X[0].buf1._y:=1]
|
||||
168109 t.registers.word_selector_f[1]._y : 1 [by t.registers.word_selector_f[0].a:=0]
|
||||
169788 t.registers.word_selector_f[0]._y : 1 [by t.registers.word_selector_f[0].a:=0]
|
||||
170145 t.registers.word_selector_f[0].y : 0 [by t.registers.word_selector_f[0]._y:=1]
|
||||
170170 t.registers.bitselector_f[0].or2s[0]._y : 1 [by t.registers.word_selector_f[0].y:=0]
|
||||
170191 t.registers.bitselector_f[0].tmp[4] : 0 [by t.registers.bitselector_f[0].or2s[0]._y:=1]
|
||||
170350 t.registers.bitselector_f[1].or2s[1]._y : 1 [by t.registers.word_selector_f[5].y:=0]
|
||||
170351 t.registers.bitselector_f[1].tmp[5] : 0 [by t.registers.bitselector_f[1].or2s[1]._y:=1]
|
||||
170722 t.registers._in_a_write : 0 [by t.registers.ack_write_and._y:=1]
|
||||
172920 t.registers.val_input.OR2_tf[2]._y : 1 [by t.registers.atree[0].in[0]:=0]
|
||||
172921 t.registers.val_input.ct.in[2] : 0 [by t.registers.val_input.OR2_tf[2]._y:=1]
|
||||
172922 t.registers.val_input.ct.C3Els[0]._y : 1 [by t.registers.val_input.ct.in[2]:=0]
|
||||
173083 t.registers.val_input.ct.tmp[6] : 0 [by t.registers.val_input.ct.C3Els[0]._y:=1]
|
||||
178581 t.registers.word_selector_f[6].y : 0 [by t.registers.word_selector_f[6]._y:=1]
|
||||
180370 t.registers.ack_readwrite._y : 1 [by t.registers._in_a_write:=0]
|
||||
181407 t.registers._in_a_temp : 0 [by t.registers.ack_readwrite._y:=1]
|
||||
181412 t.registers.ack_input_X.buf4._y : 1 [by t.registers._in_a_temp:=0]
|
||||
181566 t.registers.val_input.ct.tmp[5] : 0 [by t.registers.val_input.ct.C2Els[0]._y:=1]
|
||||
181974 t.registers.val_input.ct.C2Els[1]._y : 1 [by t.registers.val_input.ct.tmp[5]:=0]
|
||||
181985 t.registers._in_v_temp : 0 [by t.registers.val_input.ct.C2Els[1]._y:=1]
|
||||
181993 t.in.a : 0 [by t.registers.ack_input_X.buf4._y:=1]
|
||||
183032 t.registers.val_input_X.buf4._y : 1 [by t.registers._in_v_temp:=0]
|
||||
183046 t.in.v : 0 [by t.registers.val_input_X.buf4._y:=1]
|
||||
183334 t.registers.clock_buffer[3].buf1._y : 1 [by t.registers._clock_word_temp[3]:=0]
|
||||
183352 t.registers.ff[6].clk_B : 0 [by t.registers.clock_buffer[3].buf1._y:=1]
|
||||
183356 t.registers.ff[6]._clk_B : 1 [by t.registers.ff[6].clk_B:=0]
|
||||
183456 t.registers.ff[7]._clk_B : 1 [by t.registers.ff[6].clk_B:=0]
|
||||
184660 t.registers.ff[7].__clk_B : 0 [by t.registers.ff[7]._clk_B:=1]
|
||||
184821 t.registers.ff[2]._clk_B : 1 [by t.registers.ff[2].clk_B:=0]
|
||||
185093 t.registers.word_selector_f[1].y : 0 [by t.registers.word_selector_f[1]._y:=1]
|
||||
185321 t.registers.bitselector_f[1].or2s[0]._y : 1 [by t.registers.word_selector_f[1].y:=0]
|
||||
186164 t.registers.bitselector_f[1].tmp[4] : 0 [by t.registers.bitselector_f[1].or2s[0]._y:=1]
|
||||
187623 t.registers.bitselector_f[1].or2s[2]._y : 1 [by t.registers.bitselector_f[1].tmp[4]:=0]
|
||||
187693 t.registers.bitselector_f[1].out : 0 [by t.registers.bitselector_f[1].or2s[2]._y:=1]
|
||||
189963 t.registers._out_encoder[0] : 0 [by t.registers.atree[0].and2s[0]._y:=1]
|
||||
189974 t.registers.and_encoder[0]._y : 1 [by t.registers._out_encoder[0]:=0]
|
||||
189977 t.registers._clock_word_temp[0] : 0 [by t.registers.and_encoder[0]._y:=1]
|
||||
190031 t.registers.clock_buffer[0].buf1._y : 1 [by t.registers._clock_word_temp[0]:=0]
|
||||
190124 t.registers.word_selector_f[4].y : 0 [by t.registers.word_selector_f[4]._y:=1]
|
||||
191179 t.registers.ff[0].clk_B : 0 [by t.registers.clock_buffer[0].buf1._y:=1]
|
||||
191260 t.registers.ff[1]._clk_B : 1 [by t.registers.ff[0].clk_B:=0]
|
||||
191285 t.registers.bitselector_f[0].or2s[1]._y : 1 [by t.registers.word_selector_f[4].y:=0]
|
||||
192260 t.registers.output_buf.en_buf_f.buf1._y : 0 [by t.registers.output_buf._en:=1]
|
||||
192352 t.registers.output_buf._en_X_f[0] : 1 [by t.registers.output_buf.en_buf_f.buf1._y:=0]
|
||||
193276 t.registers.ff[2].__clk_B : 0 [by t.registers.ff[2]._clk_B:=1]
|
||||
199831 t.registers.ff[0]._clk_B : 1 [by t.registers.ff[0].clk_B:=0]
|
||||
202337 t.registers.ff[1].__clk_B : 0 [by t.registers.ff[1]._clk_B:=1]
|
||||
208142 t.registers.ff[0].__clk_B : 0 [by t.registers.ff[0]._clk_B:=1]
|
||||
209268 t.registers.bitselector_f[0].tmp[5] : 0 [by t.registers.bitselector_f[0].or2s[1]._y:=1]
|
||||
209846 t.registers.clk_dly.dly[0].y : 0 [by t.registers.clk_dly.dly[0].___y:=1]
|
||||
210459 t.registers.clk_dly.mu2[0]._y : 1 [by t.registers.clk_dly.dly[0].y:=0]
|
||||
211012 t.registers.bitselector_f[0].or2s[2]._y : 1 [by t.registers.bitselector_f[0].tmp[5]:=0]
|
||||
211057 t.registers.bitselector_f[0].out : 0 [by t.registers.bitselector_f[0].or2s[2]._y:=1]
|
||||
212054 t.registers.output_buf.vc.OR2_tf[0]._y : 1 [by t.registers.bitselector_f[0].out:=0]
|
||||
213703 t.registers.output_buf.vc.ct.in[0] : 0 [by t.registers.output_buf.vc.OR2_tf[0]._y:=1]
|
||||
214800 t.registers.ff[6].__clk_B : 0 [by t.registers.ff[6]._clk_B:=1]
|
||||
224481 t.registers.clk_dly._a[1] : 0 [by t.registers.clk_dly.mu2[0]._y:=1]
|
||||
225006 t.registers.clk_dly.and2[1]._y : 1 [by t.registers.clk_dly._a[1]:=0]
|
||||
225906 t.registers.clk_dly.dly[1].a : 0 [by t.registers.clk_dly.and2[1]._y:=1]
|
||||
225958 t.registers.clk_dly.dly[1]._y : 1 [by t.registers.clk_dly.dly[1].a:=0]
|
||||
225965 t.registers.clk_dly.dly[1].__y : 0 [by t.registers.clk_dly.dly[1]._y:=1]
|
||||
238115 t.registers.output_buf.vc.OR2_tf[1]._y : 1 [by t.registers.bitselector_f[1].out:=0]
|
||||
241577 t.registers.clk_dly.dly[1].___y : 1 [by t.registers.clk_dly.dly[1].__y:=0]
|
||||
241579 t.registers.clk_dly.dly[1].y : 0 [by t.registers.clk_dly.dly[1].___y:=1]
|
||||
241933 t.registers.clk_dly.dly[2]._y : 1 [by t.registers.clk_dly.dly[1].y:=0]
|
||||
242066 t.registers.clk_dly.dly[2].__y : 0 [by t.registers.clk_dly.dly[2]._y:=1]
|
||||
242067 t.registers.clk_dly.dly[2].___y : 1 [by t.registers.clk_dly.dly[2].__y:=0]
|
||||
242071 t.registers.clk_dly.dly[2].y : 0 [by t.registers.clk_dly.dly[2].___y:=1]
|
||||
242617 t.registers.clk_dly.mu2[1]._y : 1 [by t.registers.clk_dly.dly[2].y:=0]
|
||||
244582 t.registers.output_buf.vc.ct.in[1] : 0 [by t.registers.output_buf.vc.OR2_tf[1]._y:=1]
|
||||
244583 t.registers.output_buf.vc.ct.C2Els[0]._y : 1 [by t.registers.output_buf.vc.ct.in[1]:=0]
|
||||
256961 t.registers.output_buf.vc.ct.tmp[4] : 0 [by t.registers.output_buf.vc.ct.C2Els[0]._y:=1]
|
||||
257040 t.registers.output_buf.vc.ct.C2Els[2]._y : 1 [by t.registers.output_buf.vc.ct.tmp[4]:=0]
|
||||
259473 t.registers.output_buf._in_v : 0 [by t.registers.output_buf.vc.ct.C2Els[2]._y:=1]
|
||||
259561 t.registers.output_buf.in_v_buf4._y : 1 [by t.registers.output_buf._in_v:=0]
|
||||
267343 t.registers.output_buf.in.v : 0 [by t.registers.output_buf.in_v_buf4._y:=1]
|
||||
288180 t.registers._clock_temp : 0 [by t.registers.clk_dly.mu2[1]._y:=1]
|
||||
288210 t.registers._clock_temp_inv : 1 [by t.registers._clock_temp:=0]
|
||||
288239 t.registers.ack_dly.and2[0]._y : 1 [by t.registers._clock_temp:=0]
|
||||
289677 t.registers.clk_X.buf1._y : 0 [by t.registers._clock_temp_inv:=1]
|
||||
295670 t.registers.output_buf.in_v_bufN.buf1._y : 1 [by t.registers.output_buf.in.v:=0]
|
||||
296355 t.registers.output_buf._in_vX[0] : 0 [by t.registers.output_buf.in_v_bufN.buf1._y:=1]
|
||||
309061 t.registers._clock[0] : 1 [by t.registers.clk_X.buf1._y:=0]
|
||||
347743 t.registers.ack_dly.dly[0].a : 0 [by t.registers.ack_dly.and2[0]._y:=1]
|
||||
364458 t.registers.ack_dly.dly[0]._y : 1 [by t.registers.ack_dly.dly[0].a:=0]
|
||||
364585 t.registers.ack_dly.dly[0].__y : 0 [by t.registers.ack_dly.dly[0]._y:=1]
|
||||
364754 t.registers.ack_dly.dly[0].___y : 1 [by t.registers.ack_dly.dly[0].__y:=0]
|
||||
364797 t.registers.ack_dly.dly[0].y : 0 [by t.registers.ack_dly.dly[0].___y:=1]
|
||||
364809 t.registers.ack_dly.mu2[0]._y : 1 [by t.registers.ack_dly.dly[0].y:=0]
|
||||
366088 t.registers.ack_dly._a[1] : 0 [by t.registers.ack_dly.mu2[0]._y:=1]
|
||||
366321 t.registers.ack_dly.and2[1]._y : 1 [by t.registers.ack_dly._a[1]:=0]
|
||||
366324 t.registers.ack_dly.dly[1].a : 0 [by t.registers.ack_dly.and2[1]._y:=1]
|
||||
366362 t.registers.ack_dly.dly[1]._y : 1 [by t.registers.ack_dly.dly[1].a:=0]
|
||||
366363 t.registers.ack_dly.dly[1].__y : 0 [by t.registers.ack_dly.dly[1]._y:=1]
|
||||
379115 t.registers.ack_dly.dly[1].___y : 1 [by t.registers.ack_dly.dly[1].__y:=0]
|
||||
379207 t.registers.ack_dly.dly[1].y : 0 [by t.registers.ack_dly.dly[1].___y:=1]
|
||||
381934 t.registers.ack_dly.dly[2]._y : 1 [by t.registers.ack_dly.dly[1].y:=0]
|
||||
381936 t.registers.ack_dly.dly[2].__y : 0 [by t.registers.ack_dly.dly[2]._y:=1]
|
||||
381937 t.registers.ack_dly.dly[2].___y : 1 [by t.registers.ack_dly.dly[2].__y:=0]
|
||||
383438 t.registers.ack_dly.dly[2].y : 0 [by t.registers.ack_dly.dly[2].___y:=1]
|
||||
383440 t.registers.ack_dly.mu2[1]._y : 1 [by t.registers.ack_dly.dly[2].y:=0]
|
||||
383458 t.registers._in_a_write_temp : 0 [by t.registers.ack_dly.mu2[1]._y:=1]
|
||||
t.out.d.d[3].t t.out.d.d[0].f t.out.d.d[3].f t.out.d.d[1].f t.registers.output_buf.f_buf_func[0]._y t.registers.output_buf.t_buf_func[3]._y t.registers.output_buf.f_buf_func[3]._y t.registers.output_buf.f_buf_func[1]._y
|
||||
WRONG ASSERT: "t.out.d.d[0].f" has value X and not 0.
|
||||
WRONG ASSERT: "t.out.d.d[1].f" has value X and not 0.
|
||||
WRONG ASSERT: "t.out.d.d[3].f" has value X and not 0.
|
||||
WRONG ASSERT: "t.out.d.d[3].t" has value X and not 0.
|
||||
140994 t.registers.ff[4].clk_B : 1 [by t.registers.clock_buffer[2].buf1._y:=0]
|
||||
179718 t.registers.ff[2].clk_B : 1 [by t.registers.clock_buffer[1].buf1._y:=0]
|
||||
187387 t.registers.ff[0].clk_B : 1 [by t.registers.clock_buffer[0].buf1._y:=0]
|
||||
198536 t.registers.ff[6].clk_B : 1 [by t.registers.clock_buffer[3].buf1._y:=0]
|
||||
[1] reset completed
|
||||
----------------------------------------------------------
|
||||
408819 t.dly_cfg[0] : 1
|
||||
408819 t.dly_cfg[1] : 1
|
||||
408849 t.registers.ack_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1]
|
||||
408878 t.registers.clk_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1]
|
||||
410286 t.registers.clk_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1]
|
||||
437146 t.registers.ack_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1]
|
||||
468382 t.registers.clk_dly.mu2[0]._y : 1 [by t.registers.clk_dly.mu2[0]._s:=0]
|
||||
487766 t.registers.clk_dly._a[1] : 0 [by t.registers.clk_dly.mu2[0]._y:=1]
|
||||
488451 t.registers.clk_dly.and2[1]._y : 1 [by t.registers.clk_dly._a[1]:=0]
|
||||
505166 t.registers.clk_dly.dly[1].a : 0 [by t.registers.clk_dly.and2[1]._y:=1]
|
||||
505293 t.registers.clk_dly.dly[1]._y : 1 [by t.registers.clk_dly.dly[1].a:=0]
|
||||
505462 t.registers.clk_dly.dly[1].__y : 0 [by t.registers.clk_dly.dly[1]._y:=1]
|
||||
505505 t.registers.clk_dly.dly[1].___y : 1 [by t.registers.clk_dly.dly[1].__y:=0]
|
||||
505517 t.registers.clk_dly.dly[1].y : 0 [by t.registers.clk_dly.dly[1].___y:=1]
|
||||
506796 t.registers.clk_dly.dly[2]._y : 1 [by t.registers.clk_dly.dly[1].y:=0]
|
||||
507029 t.registers.clk_dly.dly[2].__y : 0 [by t.registers.clk_dly.dly[2]._y:=1]
|
||||
507032 t.registers.clk_dly.dly[2].___y : 1 [by t.registers.clk_dly.dly[2].__y:=0]
|
||||
507070 t.registers.clk_dly.dly[2].y : 0 [by t.registers.clk_dly.dly[2].___y:=1]
|
||||
507071 t.registers.clk_dly.mu2[1]._y : 1 [by t.registers.clk_dly.dly[2].y:=0]
|
||||
519823 t.registers._clock_temp : 0 [by t.registers.clk_dly.mu2[1]._y:=1]
|
||||
519915 t.registers._clock_temp_inv : 1 [by t.registers._clock_temp:=0]
|
||||
522642 t.registers.clk_X.buf1._y : 0 [by t.registers._clock_temp_inv:=1]
|
||||
522644 t.registers._clock : 1 [by t.registers.clk_X.buf1._y:=0]
|
||||
522645 t.registers.ack_dly.and2[0]._y : 0 [by t.registers._clock:=1]
|
||||
524146 t.registers.ack_dly.dly[0].a : 1 [by t.registers.ack_dly.and2[0]._y:=0]
|
||||
524148 t.registers.ack_dly.dly[0]._y : 0 [by t.registers.ack_dly.dly[0].a:=1]
|
||||
524166 t.registers.ack_dly.dly[0].__y : 1 [by t.registers.ack_dly.dly[0]._y:=0]
|
||||
524285 t.registers.ack_dly.dly[0].___y : 0 [by t.registers.ack_dly.dly[0].__y:=1]
|
||||
530005 t.registers.ack_dly.dly[0].y : 1 [by t.registers.ack_dly.dly[0].___y:=0]
|
||||
530013 t.registers.ack_dly.mu2[0]._y : 0 [by t.registers.ack_dly.dly[0].y:=1]
|
||||
530067 t.registers.ack_dly._a[1] : 1 [by t.registers.ack_dly.mu2[0]._y:=0]
|
||||
580605 t.registers.ack_dly.and2[1]._y : 0 [by t.registers.ack_dly._a[1]:=1]
|
||||
580610 t.registers.ack_dly.dly[1].a : 1 [by t.registers.ack_dly.and2[1]._y:=0]
|
||||
581677 t.registers.ack_dly.dly[1]._y : 0 [by t.registers.ack_dly.dly[1].a:=1]
|
||||
581678 t.registers.ack_dly.dly[1].__y : 1 [by t.registers.ack_dly.dly[1]._y:=0]
|
||||
581816 t.registers.ack_dly.dly[1].___y : 0 [by t.registers.ack_dly.dly[1].__y:=1]
|
||||
581817 t.registers.ack_dly.dly[1].y : 1 [by t.registers.ack_dly.dly[1].___y:=0]
|
||||
581881 t.registers.ack_dly.dly[2]._y : 0 [by t.registers.ack_dly.dly[1].y:=1]
|
||||
582004 t.registers.ack_dly.dly[2].__y : 1 [by t.registers.ack_dly.dly[2]._y:=0]
|
||||
582006 t.registers.ack_dly.dly[2].___y : 0 [by t.registers.ack_dly.dly[2].__y:=1]
|
||||
582043 t.registers.ack_dly.dly[2].y : 1 [by t.registers.ack_dly.dly[2].___y:=0]
|
||||
582186 t.registers.ack_dly.mu2[1]._y : 0 [by t.registers.ack_dly.dly[2].y:=1]
|
||||
582237 t.registers._in_write.a : 1 [by t.registers.ack_dly.mu2[1]._y:=0]
|
||||
582679 t.registers.read_write_demux._out2_a_B : 0 [by t.registers._in_write.a:=1]
|
||||
582680 t.registers.read_write_demux.out2_a_B_buf_f.buf1._y : 1 [by t.registers.read_write_demux._out2_a_B:=0]
|
||||
582689 t.registers.read_write_demux._out2_a_BX_t[0] : 0 [by t.registers.read_write_demux.out2_a_B_buf_f.buf1._y:=1]
|
||||
582690 t.registers.read_write_demux.out2_a_B_buf_t.buf1._y : 1 [by t.registers.read_write_demux._out2_a_B:=0]
|
||||
582715 t.registers.read_write_demux._out2_a_BX_f[0] : 0 [by t.registers.read_write_demux.out2_a_B_buf_t.buf1._y:=1]
|
||||
[2] delay line set
|
||||
----------------------------------------------------------
|
||||
383458 t.registers.ff[0].d : 1
|
||||
383458 t.registers.clk_switch.b : 1
|
||||
383458 t.registers.atree[0].in[0] : 1
|
||||
383458 t.registers.ff[1].d : 1
|
||||
383458 t.registers.atree[0].in[1] : 1
|
||||
383463 t.registers.val_input.OR2_tf[3]._y : 0 [by t.registers.atree[0].in[1]:=1]
|
||||
383466 t.registers.val_input.OR2_tf[2]._y : 0 [by t.registers.atree[0].in[0]:=1]
|
||||
383467 t.registers.val_input.ct.in[2] : 1 [by t.registers.val_input.OR2_tf[2]._y:=0]
|
||||
383512 t.registers.val_input.OR2_tf[1]._y : 0 [by t.registers.ff[1].d:=1]
|
||||
383577 t.registers.val_input.OR2_tf[0]._y : 0 [by t.registers.ff[0].d:=1]
|
||||
383578 t.registers.val_input.ct.in[0] : 1 [by t.registers.val_input.OR2_tf[0]._y:=0]
|
||||
383650 t.registers.val_input.ct.in[1] : 1 [by t.registers.val_input.OR2_tf[1]._y:=0]
|
||||
383714 t.registers.val_input.ct.C2Els[0]._y : 0 [by t.registers.val_input.ct.in[1]:=1]
|
||||
383837 t.registers.val_input.ct.tmp[5] : 1 [by t.registers.val_input.ct.C2Els[0]._y:=0]
|
||||
384530 t.registers.val_input.ct.in[3] : 1 [by t.registers.val_input.OR2_tf[3]._y:=0]
|
||||
389178 t.registers.val_input.OR2_tf[4]._y : 0 [by t.registers.clk_switch.b:=1]
|
||||
389180 t.registers.val_input.ct.in[4] : 1 [by t.registers.val_input.OR2_tf[4]._y:=0]
|
||||
389217 t.registers.val_input.ct.C3Els[0]._y : 0 [by t.registers.val_input.ct.in[4]:=1]
|
||||
389360 t.registers.val_input.ct.tmp[6] : 1 [by t.registers.val_input.ct.C3Els[0]._y:=0]
|
||||
389411 t.registers.val_input.ct.C2Els[1]._y : 0 [by t.registers.val_input.ct.tmp[6]:=1]
|
||||
389853 t.registers._in_v_temp : 1 [by t.registers.val_input.ct.C2Els[1]._y:=0]
|
||||
389854 t.registers.val_input_X.buf4._y : 0 [by t.registers._in_v_temp:=1]
|
||||
389863 t.in.v : 1 [by t.registers.val_input_X.buf4._y:=0]
|
||||
389864 t.registers.clk_switch._y : 0 [by t.registers._in_v_temp:=1]
|
||||
389889 t.registers._in_v_temp_write : 1 [by t.registers.clk_switch._y:=0]
|
||||
400142 t.registers.clk_dly.and2[0]._y : 0 [by t.registers._in_v_temp_write:=1]
|
||||
403663 t.registers.clk_dly.dly[0].a : 1 [by t.registers.clk_dly.and2[0]._y:=0]
|
||||
403808 t.registers.clk_dly.dly[0]._y : 0 [by t.registers.clk_dly.dly[0].a:=1]
|
||||
419976 t.registers.clk_dly.dly[0].__y : 1 [by t.registers.clk_dly.dly[0]._y:=0]
|
||||
420206 t.registers.clk_dly.dly[0].___y : 0 [by t.registers.clk_dly.dly[0].__y:=1]
|
||||
420897 t.registers.clk_dly.dly[0].y : 1 [by t.registers.clk_dly.dly[0].___y:=0]
|
||||
420911 t.registers.clk_dly.mu2[0]._y : 0 [by t.registers.clk_dly.dly[0].y:=1]
|
||||
422454 t.registers.clk_dly._a[1] : 1 [by t.registers.clk_dly.mu2[0]._y:=0]
|
||||
424065 t.registers.clk_dly.and2[1]._y : 0 [by t.registers.clk_dly._a[1]:=1]
|
||||
433996 t.registers.atree[0].and2s[0]._y : 0 [by t.registers.atree[0].in[1]:=1]
|
||||
434007 t.registers._out_encoder[0] : 1 [by t.registers.atree[0].and2s[0]._y:=0]
|
||||
434008 t.registers.and_encoder[0]._y : 0 [by t.registers._out_encoder[0]:=1]
|
||||
434009 t.registers._clock_word_temp[0] : 1 [by t.registers.and_encoder[0]._y:=0]
|
||||
440510 t.registers.clock_buffer[0].buf1._y : 0 [by t.registers._clock_word_temp[0]:=1]
|
||||
441149 t.registers.ff[0].clk_B : 1 [by t.registers.clock_buffer[0].buf1._y:=0]
|
||||
441281 t.registers.ff[1]._clk_B : 0 [by t.registers.ff[0].clk_B:=1]
|
||||
441282 t.registers.ff[1].__clk_B : 1 [by t.registers.ff[1]._clk_B:=0]
|
||||
441299 t.registers.ff[1]._mqib : 0 [by t.registers.ff[1].__clk_B:=1]
|
||||
441451 t.registers.ff[1]._mqi : 1 [by t.registers.ff[1]._mqib:=0]
|
||||
441577 t.registers.clk_dly.dly[1].a : 1 [by t.registers.clk_dly.and2[1]._y:=0]
|
||||
442942 t.registers.ff[0]._clk_B : 0 [by t.registers.ff[0].clk_B:=1]
|
||||
442945 t.registers.ff[0].__clk_B : 1 [by t.registers.ff[0]._clk_B:=0]
|
||||
443369 t.registers.ff[0]._mqib : 0 [by t.registers.ff[0].__clk_B:=1]
|
||||
443375 t.registers.ff[0]._mqi : 1 [by t.registers.ff[0]._mqib:=0]
|
||||
444560 t.registers.clk_dly.dly[1]._y : 0 [by t.registers.clk_dly.dly[1].a:=1]
|
||||
447148 t.registers.clk_dly.dly[1].__y : 1 [by t.registers.clk_dly.dly[1]._y:=0]
|
||||
449609 t.registers.clk_dly.dly[1].___y : 0 [by t.registers.clk_dly.dly[1].__y:=1]
|
||||
450439 t.registers.clk_dly.dly[1].y : 1 [by t.registers.clk_dly.dly[1].___y:=0]
|
||||
473371 t.registers.clk_dly.dly[2]._y : 0 [by t.registers.clk_dly.dly[1].y:=1]
|
||||
473373 t.registers.clk_dly.dly[2].__y : 1 [by t.registers.clk_dly.dly[2]._y:=0]
|
||||
473567 t.registers.clk_dly.dly[2].___y : 0 [by t.registers.clk_dly.dly[2].__y:=1]
|
||||
474170 t.registers.clk_dly.dly[2].y : 1 [by t.registers.clk_dly.dly[2].___y:=0]
|
||||
474308 t.registers.clk_dly.mu2[1]._y : 0 [by t.registers.clk_dly.dly[2].y:=1]
|
||||
474325 t.registers._clock_temp : 1 [by t.registers.clk_dly.mu2[1]._y:=0]
|
||||
474342 t.registers.ack_dly.and2[0]._y : 0 [by t.registers._clock_temp:=1]
|
||||
474343 t.registers.ack_dly.dly[0].a : 1 [by t.registers.ack_dly.and2[0]._y:=0]
|
||||
474344 t.registers.ack_dly.dly[0]._y : 0 [by t.registers.ack_dly.dly[0].a:=1]
|
||||
474751 t.registers._clock_temp_inv : 0 [by t.registers._clock_temp:=1]
|
||||
474752 t.registers.clk_X.buf1._y : 1 [by t.registers._clock_temp_inv:=0]
|
||||
474771 t.registers._clock[0] : 0 [by t.registers.clk_X.buf1._y:=1]
|
||||
474939 t.registers.and_encoder[0]._y : 1 [by t.registers._clock[0]:=0]
|
||||
475370 t.registers.ack_dly.dly[0].__y : 1 [by t.registers.ack_dly.dly[0]._y:=0]
|
||||
475478 t.registers._clock_word_temp[0] : 0 [by t.registers.and_encoder[0]._y:=1]
|
||||
475531 t.registers.ack_dly.dly[0].___y : 0 [by t.registers.ack_dly.dly[0].__y:=1]
|
||||
475651 t.registers.clock_buffer[0].buf1._y : 1 [by t.registers._clock_word_temp[0]:=0]
|
||||
478078 t.registers.ack_dly.dly[0].y : 1 [by t.registers.ack_dly.dly[0].___y:=0]
|
||||
478079 t.registers.ack_dly.mu2[0]._y : 0 [by t.registers.ack_dly.dly[0].y:=1]
|
||||
478080 t.registers.ack_dly._a[1] : 1 [by t.registers.ack_dly.mu2[0]._y:=0]
|
||||
478470 t.registers.ack_dly.and2[1]._y : 0 [by t.registers.ack_dly._a[1]:=1]
|
||||
478677 t.registers.ack_dly.dly[1].a : 1 [by t.registers.ack_dly.and2[1]._y:=0]
|
||||
479510 t.registers.ack_dly.dly[1]._y : 0 [by t.registers.ack_dly.dly[1].a:=1]
|
||||
479538 t.registers.ack_dly.dly[1].__y : 1 [by t.registers.ack_dly.dly[1]._y:=0]
|
||||
479545 t.registers.ack_dly.dly[1].___y : 0 [by t.registers.ack_dly.dly[1].__y:=1]
|
||||
479959 t.registers.ack_dly.dly[1].y : 1 [by t.registers.ack_dly.dly[1].___y:=0]
|
||||
479963 t.registers.ack_dly.dly[2]._y : 0 [by t.registers.ack_dly.dly[1].y:=1]
|
||||
481742 t.registers.ack_dly.dly[2].__y : 1 [by t.registers.ack_dly.dly[2]._y:=0]
|
||||
490712 t.registers.ff[0].clk_B : 0 [by t.registers.clock_buffer[0].buf1._y:=1]
|
||||
490878 t.registers.ff[0]._clk_B : 1 [by t.registers.ff[0].clk_B:=0]
|
||||
491811 t.registers.ff[0]._sqib : 0 [by t.registers.ff[0]._clk_B:=1]
|
||||
491950 t.data[0].d[0] : 1 [by t.registers.ff[0]._sqib:=0]
|
||||
492667 t.registers.ff[0]._sqi : 1 [by t.registers.ff[0]._sqib:=0]
|
||||
499523 t.registers.ff[0].__clk_B : 0 [by t.registers.ff[0]._clk_B:=1]
|
||||
504616 t.registers.ack_dly.dly[2].___y : 0 [by t.registers.ack_dly.dly[2].__y:=1]
|
||||
504811 t.registers.ack_dly.dly[2].y : 1 [by t.registers.ack_dly.dly[2].___y:=0]
|
||||
504813 t.registers.ack_dly.mu2[1]._y : 0 [by t.registers.ack_dly.dly[2].y:=1]
|
||||
518159 t.registers.ff[0].q_B : 0 [by t.data[0].d[0]:=1]
|
||||
530582 t.registers.ff[1]._clk_B : 1 [by t.registers.ff[0].clk_B:=0]
|
||||
530588 t.registers.ff[1].__clk_B : 0 [by t.registers.ff[1]._clk_B:=1]
|
||||
530836 t.registers.ff[1]._sqib : 0 [by t.registers.ff[1]._clk_B:=1]
|
||||
530837 t.data[0].d[1] : 1 [by t.registers.ff[1]._sqib:=0]
|
||||
530843 t.registers.ff[1].q_B : 0 [by t.data[0].d[1]:=1]
|
||||
530844 t.registers.ff[1]._sqi : 1 [by t.registers.ff[1]._sqib:=0]
|
||||
558262 t.registers._in_a_write_temp : 1 [by t.registers.ack_dly.mu2[1]._y:=0]
|
||||
609298 t.registers.ack_write_and._y : 0 [by t.registers._in_a_write_temp:=1]
|
||||
612388 t.registers._in_a_write : 1 [by t.registers.ack_write_and._y:=0]
|
||||
612614 t.registers.ack_readwrite._y : 0 [by t.registers._in_a_write:=1]
|
||||
613433 t.registers._in_a_temp : 1 [by t.registers.ack_readwrite._y:=0]
|
||||
613434 t.registers.ack_input_X.buf4._y : 0 [by t.registers._in_a_temp:=1]
|
||||
613440 t.in.a : 1 [by t.registers.ack_input_X.buf4._y:=0]
|
||||
WRONG ASSERT: "t.out.d.d[0].f" has value X and not 0.
|
||||
WRONG ASSERT: "t.out.d.d[1].f" has value X and not 0.
|
||||
WRONG ASSERT: "t.out.d.d[3].f" has value X and not 0.
|
||||
WRONG ASSERT: "t.out.d.d[3].t" has value X and not 0.
|
||||
613440 t.registers.ff[0].d : 0
|
||||
613440 t.registers.clk_switch.b : 0
|
||||
613440 t.registers.atree[0].in[0] : 0
|
||||
613440 t.registers.ff[1].d : 0
|
||||
613440 t.registers.atree[0].in[1] : 0
|
||||
613442 t.registers.val_input.OR2_tf[0]._y : 1 [by t.registers.ff[0].d:=0]
|
||||
613455 t.registers.clk_switch._y : 1 [by t.registers.clk_switch.b:=0]
|
||||
613533 t.registers.val_input.OR2_tf[2]._y : 1 [by t.registers.atree[0].in[0]:=0]
|
||||
613547 t.registers.atree[0].and2s[0]._y : 1 [by t.registers.atree[0].in[0]:=0]
|
||||
613548 t.registers._out_encoder[0] : 0 [by t.registers.atree[0].and2s[0]._y:=1]
|
||||
614200 t.registers.val_input.ct.in[0] : 0 [by t.registers.val_input.OR2_tf[0]._y:=1]
|
||||
614249 t.registers.val_input.ct.in[2] : 0 [by t.registers.val_input.OR2_tf[2]._y:=1]
|
||||
615092 t.registers.val_input.OR2_tf[1]._y : 1 [by t.registers.ff[1].d:=0]
|
||||
616078 t.registers._in_v_temp_write : 0 [by t.registers.clk_switch._y:=1]
|
||||
616079 t.registers.clk_dly.and2[0]._y : 1 [by t.registers._in_v_temp_write:=0]
|
||||
616832 t.registers.val_input.ct.in[1] : 0 [by t.registers.val_input.OR2_tf[1]._y:=1]
|
||||
617002 t.registers.ack_write_and._y : 1 [by t.registers.clk_switch.b:=0]
|
||||
617003 t.registers._in_a_write : 0 [by t.registers.ack_write_and._y:=1]
|
||||
617009 t.registers.ack_readwrite._y : 1 [by t.registers._in_a_write:=0]
|
||||
617010 t.registers._in_a_temp : 0 [by t.registers.ack_readwrite._y:=1]
|
||||
617379 t.registers.val_input.OR2_tf[3]._y : 1 [by t.registers.atree[0].in[1]:=0]
|
||||
628231 t.registers.clk_dly.dly[0].a : 0 [by t.registers.clk_dly.and2[0]._y:=1]
|
||||
628253 t.registers.clk_dly.dly[0]._y : 1 [by t.registers.clk_dly.dly[0].a:=0]
|
||||
634241 t.registers.val_input.OR2_tf[4]._y : 1 [by t.registers.clk_switch.b:=0]
|
||||
634248 t.registers.val_input.ct.in[4] : 0 [by t.registers.val_input.OR2_tf[4]._y:=1]
|
||||
638978 t.registers.val_input.ct.in[3] : 0 [by t.registers.val_input.OR2_tf[3]._y:=1]
|
||||
639043 t.registers.val_input.ct.C3Els[0]._y : 1 [by t.registers.val_input.ct.in[3]:=0]
|
||||
639056 t.registers.val_input.ct.tmp[6] : 0 [by t.registers.val_input.ct.C3Els[0]._y:=1]
|
||||
645031 t.registers.val_input.ct.C2Els[0]._y : 1 [by t.registers.val_input.ct.in[1]:=0]
|
||||
646155 t.registers.val_input.ct.tmp[5] : 0 [by t.registers.val_input.ct.C2Els[0]._y:=1]
|
||||
646259 t.registers.val_input.ct.C2Els[1]._y : 1 [by t.registers.val_input.ct.tmp[5]:=0]
|
||||
646300 t.registers._in_v_temp : 0 [by t.registers.val_input.ct.C2Els[1]._y:=1]
|
||||
646301 t.registers.val_input_X.buf4._y : 1 [by t.registers._in_v_temp:=0]
|
||||
646302 t.in.v : 0 [by t.registers.val_input_X.buf4._y:=1]
|
||||
650761 t.registers.clk_dly.dly[0].__y : 0 [by t.registers.clk_dly.dly[0]._y:=1]
|
||||
656499 t.registers.ack_input_X.buf4._y : 1 [by t.registers._in_a_temp:=0]
|
||||
669671 t.in.a : 0 [by t.registers.ack_input_X.buf4._y:=1]
|
||||
715139 t.registers.clk_dly.dly[0].___y : 1 [by t.registers.clk_dly.dly[0].__y:=0]
|
||||
715140 t.registers.clk_dly.dly[0].y : 0 [by t.registers.clk_dly.dly[0].___y:=1]
|
||||
734965 t.registers.clk_dly.mu2[0]._y : 1 [by t.registers.clk_dly.dly[0].y:=0]
|
||||
738101 t.registers.clk_dly._a[1] : 0 [by t.registers.clk_dly.mu2[0]._y:=1]
|
||||
738927 t.registers.clk_dly.and2[1]._y : 1 [by t.registers.clk_dly._a[1]:=0]
|
||||
740760 t.registers.clk_dly.dly[1].a : 0 [by t.registers.clk_dly.and2[1]._y:=1]
|
||||
757308 t.registers.clk_dly.dly[1]._y : 1 [by t.registers.clk_dly.dly[1].a:=0]
|
||||
757366 t.registers.clk_dly.dly[1].__y : 0 [by t.registers.clk_dly.dly[1]._y:=1]
|
||||
759809 t.registers.clk_dly.dly[1].___y : 1 [by t.registers.clk_dly.dly[1].__y:=0]
|
||||
776582 t.registers.clk_dly.dly[1].y : 0 [by t.registers.clk_dly.dly[1].___y:=1]
|
||||
813781 t.registers.clk_dly.dly[2]._y : 1 [by t.registers.clk_dly.dly[1].y:=0]
|
||||
813795 t.registers.clk_dly.dly[2].__y : 0 [by t.registers.clk_dly.dly[2]._y:=1]
|
||||
814151 t.registers.clk_dly.dly[2].___y : 1 [by t.registers.clk_dly.dly[2].__y:=0]
|
||||
849989 t.registers.clk_dly.dly[2].y : 0 [by t.registers.clk_dly.dly[2].___y:=1]
|
||||
850094 t.registers.clk_dly.mu2[1]._y : 1 [by t.registers.clk_dly.dly[2].y:=0]
|
||||
850203 t.registers._clock_temp : 0 [by t.registers.clk_dly.mu2[1]._y:=1]
|
||||
850204 t.registers.ack_dly.and2[0]._y : 1 [by t.registers._clock_temp:=0]
|
||||
850212 t.registers._clock_temp_inv : 1 [by t.registers._clock_temp:=0]
|
||||
850213 t.registers.clk_X.buf1._y : 0 [by t.registers._clock_temp_inv:=1]
|
||||
886607 t.registers._clock[0] : 1 [by t.registers.clk_X.buf1._y:=0]
|
||||
888157 t.registers.ack_dly.dly[0].a : 0 [by t.registers.ack_dly.and2[0]._y:=1]
|
||||
888158 t.registers.ack_dly.dly[0]._y : 1 [by t.registers.ack_dly.dly[0].a:=0]
|
||||
891247 t.registers.ack_dly.dly[0].__y : 0 [by t.registers.ack_dly.dly[0]._y:=1]
|
||||
939973 t.registers.ack_dly.dly[0].___y : 1 [by t.registers.ack_dly.dly[0].__y:=0]
|
||||
940723 t.registers.ack_dly.dly[0].y : 0 [by t.registers.ack_dly.dly[0].___y:=1]
|
||||
947478 t.registers.ack_dly.mu2[0]._y : 1 [by t.registers.ack_dly.dly[0].y:=0]
|
||||
947529 t.registers.ack_dly._a[1] : 0 [by t.registers.ack_dly.mu2[0]._y:=1]
|
||||
947539 t.registers.ack_dly.and2[1]._y : 1 [by t.registers.ack_dly._a[1]:=0]
|
||||
947859 t.registers.ack_dly.dly[1].a : 0 [by t.registers.ack_dly.and2[1]._y:=1]
|
||||
955441 t.registers.ack_dly.dly[1]._y : 1 [by t.registers.ack_dly.dly[1].a:=0]
|
||||
955442 t.registers.ack_dly.dly[1].__y : 0 [by t.registers.ack_dly.dly[1]._y:=1]
|
||||
955443 t.registers.ack_dly.dly[1].___y : 1 [by t.registers.ack_dly.dly[1].__y:=0]
|
||||
957173 t.registers.ack_dly.dly[1].y : 0 [by t.registers.ack_dly.dly[1].___y:=1]
|
||||
958860 t.registers.ack_dly.dly[2]._y : 1 [by t.registers.ack_dly.dly[1].y:=0]
|
||||
958875 t.registers.ack_dly.dly[2].__y : 0 [by t.registers.ack_dly.dly[2]._y:=1]
|
||||
983149 t.registers.ack_dly.dly[2].___y : 1 [by t.registers.ack_dly.dly[2].__y:=0]
|
||||
983603 t.registers.ack_dly.dly[2].y : 0 [by t.registers.ack_dly.dly[2].___y:=1]
|
||||
983919 t.registers.ack_dly.mu2[1]._y : 1 [by t.registers.ack_dly.dly[2].y:=0]
|
||||
983920 t.registers._in_a_write_temp : 0 [by t.registers.ack_dly.mu2[1]._y:=1]
|
||||
4421589 t.registers.ff[0].clk_B : 0 [by t.registers.clock_buffer[0].buf1._y:=1]
|
||||
5922746 t.registers.ff[0].clk_B : 1 [by t.registers.clock_buffer[0].buf1._y:=0]
|
||||
WARNING: unstable `t.registers.ff[1]._sqib'+
|
||||
>> cause: t.registers.ff[1].__clk_B (val: 1)
|
||||
WARNING: weak-interference `t.registers.ff[1]._sqi'
|
||||
>> cause: t.registers.ff[1]._sqib (val: X)
|
||||
>> time: 5949568
|
||||
WARNING: weak-interference `t.data[0].d[1]'
|
||||
>> cause: t.registers.ff[1]._sqib (val: X)
|
||||
>> time: 5949568
|
||||
WARNING: weak-interference `t.registers.ff[1].q_B'
|
||||
>> cause: t.data[0].d[1] (val: X)
|
||||
>> time: 5949569
|
||||
WARNING: weak-unstable `t.registers.ff[1]._sqib'-
|
||||
>> cause: t.registers.ff[1]._sqi (val: X)
|
||||
>> time: 5949575
|
||||
WRONG ASSERT: "t.registers.ff[1].q" has value X and not 1.
|
||||
[3] first writing done
|
||||
----------------------------------------------------------
|
||||
983920 t.in.d.d[0].f : 1
|
||||
983920 t.registers.ack_read_and.a : 1
|
||||
983920 t.registers.atree[0].in[0] : 1
|
||||
983920 t.in.d.d[1].f : 1
|
||||
983920 t.registers.atree[0].in[1] : 1
|
||||
983932 t.registers.val_input.OR2_tf[3]._y : 0 [by t.registers.atree[0].in[1]:=1]
|
||||
983940 t.registers.val_input.OR2_tf[2]._y : 0 [by t.registers.atree[0].in[0]:=1]
|
||||
984007 t.registers.val_input.OR2_tf[1]._y : 0 [by t.in.d.d[1].f:=1]
|
||||
984065 t.registers.address_propagator_f[1]._y : 0 [by t.registers.atree[0].in[1]:=1]
|
||||
984226 t.registers.val_input.ct.in[1] : 1 [by t.registers.val_input.OR2_tf[1]._y:=0]
|
||||
984303 t.registers.val_input.OR2_tf[0]._y : 0 [by t.in.d.d[0].f:=1]
|
||||
984833 t.registers.val_input.ct.in[3] : 1 [by t.registers.val_input.OR2_tf[3]._y:=0]
|
||||
985243 t.registers.address_propagator_f[0]._y : 0 [by t.registers.atree[0].in[0]:=1]
|
||||
985261 t.registers.address_propagator_f[0].y : 1 [by t.registers.address_propagator_f[0]._y:=0]
|
||||
985289 t.registers.val_input.ct.in[2] : 1 [by t.registers.val_input.OR2_tf[2]._y:=0]
|
||||
987455 t.registers.output_buf.vc.OR2_tf[2]._y : 0 [by t.registers.address_propagator_f[0].y:=1]
|
||||
990642 t.registers.atree[0].and2s[0]._y : 0 [by t.registers.atree[0].in[1]:=1]
|
||||
990762 t.registers._out_encoder[0] : 1 [by t.registers.atree[0].and2s[0]._y:=0]
|
||||
991383 t.registers.val_input.OR2_tf[4]._y : 0 [by t.registers.ack_read_and.a:=1]
|
||||
991975 t.registers.val_input.ct.in[4] : 1 [by t.registers.val_input.OR2_tf[4]._y:=0]
|
||||
991982 t.registers.val_input.ct.C3Els[0]._y : 0 [by t.registers.val_input.ct.in[4]:=1]
|
||||
991983 t.registers.val_input.ct.tmp[6] : 1 [by t.registers.val_input.ct.C3Els[0]._y:=0]
|
||||
992396 t.registers.address_propagator_f[1].y : 1 [by t.registers.address_propagator_f[1]._y:=0]
|
||||
992520 t.registers.output_buf.vc.OR2_tf[3]._y : 0 [by t.registers.address_propagator_f[1].y:=1]
|
||||
992826 t.registers.word_to_read[0]._y : 0 [by t.registers._out_encoder[0]:=1]
|
||||
993878 t.registers.word_to_read[0].y : 1 [by t.registers.word_to_read[0]._y:=0]
|
||||
994238 t.registers.word_to_read_X[0].buf1._y : 0 [by t.registers.word_to_read[0].y:=1]
|
||||
997077 t.registers.and_encoder[0]._y : 0 [by t.registers._out_encoder[0]:=1]
|
||||
998174 t.registers._clock_word_temp[0] : 1 [by t.registers.and_encoder[0]._y:=0]
|
||||
998450 t.registers.output_buf.vc.ct.in[3] : 1 [by t.registers.output_buf.vc.OR2_tf[3]._y:=0]
|
||||
1004432 t.registers.word_selector_f[0].a : 1 [by t.registers.word_to_read_X[0].buf1._y:=0]
|
||||
1004436 t.registers.word_selector_t[1]._y : 0 [by t.registers.word_selector_f[0].a:=1]
|
||||
1015884 t.registers.val_input.ct.in[0] : 1 [by t.registers.val_input.OR2_tf[0]._y:=0]
|
||||
1016096 t.registers.word_selector_t[0]._y : 0 [by t.registers.word_selector_f[0].a:=1]
|
||||
1018066 t.registers.clock_buffer[0].buf1._y : 0 [by t.registers._clock_word_temp[0]:=1]
|
||||
1018322 t.registers.ff[0].clk_B : 1 [by t.registers.clock_buffer[0].buf1._y:=0]
|
||||
1018359 t.registers.ff[1]._clk_B : 0 [by t.registers.ff[0].clk_B:=1]
|
||||
1018368 t.registers.ff[1]._mqib : 1 [by t.registers.ff[1]._clk_B:=0]
|
||||
1018371 t.registers.ff[1].__clk_B : 1 [by t.registers.ff[1]._clk_B:=0]
|
||||
1018795 t.registers.ff[1]._mqi : 0 [by t.registers.ff[1]._mqib:=1]
|
||||
1019477 t.registers.word_selector_t[0].y : 1 [by t.registers.word_selector_t[0]._y:=0]
|
||||
1019719 t.registers.bitselector_t[0].or2s[0]._y : 0 [by t.registers.word_selector_t[0].y:=1]
|
||||
1020554 t.registers.bitselector_t[0].tmp[4] : 1 [by t.registers.bitselector_t[0].or2s[0]._y:=0]
|
||||
1025427 t.registers.output_buf.vc.ct.in[2] : 1 [by t.registers.output_buf.vc.OR2_tf[2]._y:=0]
|
||||
1026987 t.registers.output_buf.vc.ct.C2Els[1]._y : 0 [by t.registers.output_buf.vc.ct.in[2]:=1]
|
||||
1033252 t.registers.ff[0]._clk_B : 0 [by t.registers.ff[0].clk_B:=1]
|
||||
1033512 t.registers.ff[0].__clk_B : 1 [by t.registers.ff[0]._clk_B:=0]
|
||||
1033545 t.registers.val_input.ct.C2Els[0]._y : 0 [by t.registers.val_input.ct.in[0]:=1]
|
||||
1033546 t.registers.val_input.ct.tmp[5] : 1 [by t.registers.val_input.ct.C2Els[0]._y:=0]
|
||||
1042240 t.registers.ff[0]._mqib : 1 [by t.registers.ff[0]._clk_B:=0]
|
||||
1042355 t.registers.word_selector_t[1].y : 1 [by t.registers.word_selector_t[1]._y:=0]
|
||||
1042374 t.registers.bitselector_t[1].or2s[0]._y : 0 [by t.registers.word_selector_t[1].y:=1]
|
||||
1042383 t.registers.bitselector_t[1].tmp[4] : 1 [by t.registers.bitselector_t[1].or2s[0]._y:=0]
|
||||
1042624 t.registers.ff[0]._mqi : 0 [by t.registers.ff[0]._mqib:=1]
|
||||
1064080 t.registers.output_buf.vc.ct.tmp[5] : 1 [by t.registers.output_buf.vc.ct.C2Els[1]._y:=0]
|
||||
1064337 t.registers.bitselector_t[1].or2s[2]._y : 0 [by t.registers.bitselector_t[1].tmp[4]:=1]
|
||||
1064525 t.registers.bitselector_t[1].out : 1 [by t.registers.bitselector_t[1].or2s[2]._y:=0]
|
||||
1067290 t.registers.bitselector_t[0].or2s[2]._y : 0 [by t.registers.bitselector_t[0].tmp[4]:=1]
|
||||
1069596 t.registers.val_input.ct.C2Els[1]._y : 0 [by t.registers.val_input.ct.tmp[5]:=1]
|
||||
1069744 t.registers._in_v_temp : 1 [by t.registers.val_input.ct.C2Els[1]._y:=0]
|
||||
1070890 t.registers.bitselector_t[0].out : 1 [by t.registers.bitselector_t[0].or2s[2]._y:=0]
|
||||
1070905 t.registers.output_buf.vc.OR2_tf[0]._y : 0 [by t.registers.bitselector_t[0].out:=1]
|
||||
1081514 t.registers.output_buf.vc.ct.in[0] : 1 [by t.registers.output_buf.vc.OR2_tf[0]._y:=0]
|
||||
1088621 t.registers.val_input_X.buf4._y : 0 [by t.registers._in_v_temp:=1]
|
||||
1089508 t.in.v : 1 [by t.registers.val_input_X.buf4._y:=0]
|
||||
1110301 t.registers.output_buf.vc.OR2_tf[1]._y : 0 [by t.registers.bitselector_t[1].out:=1]
|
||||
1118283 t.registers.output_buf.vc.ct.in[1] : 1 [by t.registers.output_buf.vc.OR2_tf[1]._y:=0]
|
||||
1118284 t.registers.output_buf.vc.ct.C2Els[0]._y : 0 [by t.registers.output_buf.vc.ct.in[1]:=1]
|
||||
1125010 t.registers.output_buf.vc.ct.tmp[4] : 1 [by t.registers.output_buf.vc.ct.C2Els[0]._y:=0]
|
||||
1125375 t.registers.output_buf.vc.ct.C2Els[2]._y : 0 [by t.registers.output_buf.vc.ct.tmp[4]:=1]
|
||||
1134333 t.registers.output_buf._in_v : 1 [by t.registers.output_buf.vc.ct.C2Els[2]._y:=0]
|
||||
1135717 t.registers.output_buf.in_v_buf4._y : 0 [by t.registers.output_buf._in_v:=1]
|
||||
1135738 t.registers.output_buf.in.v : 1 [by t.registers.output_buf.in_v_buf4._y:=0]
|
||||
1135779 t.registers.output_buf.in_v_bufN.buf1._y : 0 [by t.registers.output_buf.in.v:=1]
|
||||
1135782 t.registers.output_buf._in_vX[0] : 1 [by t.registers.output_buf.in_v_bufN.buf1._y:=0]
|
||||
1135784 t.registers.output_buf.f_buf_func[3]._y : 0 [by t.registers.output_buf._in_vX[0]:=1]
|
||||
1135787 t.out.d.d[3].f : 1 [by t.registers.output_buf.f_buf_func[3]._y:=0]
|
||||
1136364 t.registers.output_buf.f_buf_func[2]._y : 0 [by t.registers.output_buf._in_vX[0]:=1]
|
||||
1136365 t.out.d.d[2].f : 1 [by t.registers.output_buf.f_buf_func[2]._y:=0]
|
||||
1137659 t.registers.output_buf.t_buf_func[0]._y : 0 [by t.registers.output_buf._in_vX[0]:=1]
|
||||
1141111 t.out.d.d[0].t : 1 [by t.registers.output_buf.t_buf_func[0]._y:=0]
|
||||
1145291 t.registers.output_buf.t_buf_func[1]._y : 0 [by t.registers.output_buf._in_vX[0]:=1]
|
||||
1152424 t.out.d.d[1].t : 1 [by t.registers.output_buf.t_buf_func[1]._y:=0]
|
||||
WRONG ASSERT: "t.out.d.d[0].f" has value X and not 0.
|
||||
WRONG ASSERT: "t.out.d.d[1].f" has value X and not 0.
|
||||
WRONG ASSERT: "t.out.d.d[3].t" has value X and not 0.
|
||||
1152424 t.out.v : 1
|
||||
1153284 t.registers.output_buf.inack_ctl._y : 0 [by t.out.v:=1]
|
||||
1153285 t.registers.ack_read_and.b : 1 [by t.registers.output_buf.inack_ctl._y:=0]
|
||||
1153360 t.registers.ack_read_and._y : 0 [by t.registers.ack_read_and.b:=1]
|
||||
1153434 t.registers._in_a_read : 1 [by t.registers.ack_read_and._y:=0]
|
||||
1155704 t.registers.ack_readwrite._y : 0 [by t.registers._in_a_read:=1]
|
||||
1155802 t.registers._in_a_temp : 1 [by t.registers.ack_readwrite._y:=0]
|
||||
1161573 t.registers.ack_input_X.buf4._y : 0 [by t.registers._in_a_temp:=1]
|
||||
1181236 t.registers.output_buf._en : 0 [by t.registers.ack_read_and.b:=1]
|
||||
1185089 t.registers.output_buf.en_buf_f.buf1._y : 1 [by t.registers.output_buf._en:=0]
|
||||
1187377 t.registers.output_buf.en_buf_t.buf1._y : 1 [by t.registers.output_buf._en:=0]
|
||||
1187381 t.registers.output_buf._en_X_t[0] : 0 [by t.registers.output_buf.en_buf_t.buf1._y:=1]
|
||||
1187449 t.registers.output_buf._en_X_f[0] : 0 [by t.registers.output_buf.en_buf_f.buf1._y:=1]
|
||||
1193301 t.in.a : 1 [by t.registers.ack_input_X.buf4._y:=0]
|
||||
1193301 t.out.a : 1
|
||||
1193306 t.registers.output_buf._out_a_B : 0 [by t.out.a:=1]
|
||||
1193400 t.registers.output_buf.out_a_B_buf_f.buf1._y : 1 [by t.registers.output_buf._out_a_B:=0]
|
||||
1193401 t.registers.output_buf._out_a_BX_t[0] : 0 [by t.registers.output_buf.out_a_B_buf_f.buf1._y:=1]
|
||||
1193403 t.registers.output_buf.t_buf_func[1]._y : 1 [by t.registers.output_buf._out_a_BX_t[0]:=0]
|
||||
1193437 t.registers.output_buf.t_buf_func[0]._y : 1 [by t.registers.output_buf._out_a_BX_t[0]:=0]
|
||||
1193438 t.out.d.d[0].t : 0 [by t.registers.output_buf.t_buf_func[0]._y:=1]
|
||||
1193439 t.out.d.d[1].t : 0 [by t.registers.output_buf.t_buf_func[1]._y:=1]
|
||||
1193597 t.registers.output_buf.out_a_B_buf_t.buf1._y : 1 [by t.registers.output_buf._out_a_B:=0]
|
||||
1193611 t.registers.output_buf._out_a_BX_f[0] : 0 [by t.registers.output_buf.out_a_B_buf_t.buf1._y:=1]
|
||||
1193623 t.registers.output_buf.f_buf_func[0]._y : 1 [by t.registers.output_buf._out_a_BX_f[0]:=0]
|
||||
1205521 t.out.d.d[0].f : 0 [by t.registers.output_buf.f_buf_func[0]._y:=1]
|
||||
1206601 t.registers.output_buf.f_buf_func[3]._y : 1 [by t.registers.output_buf._out_a_BX_f[0]:=0]
|
||||
1215168 t.registers.output_buf.f_buf_func[2]._y : 1 [by t.registers.output_buf._out_a_BX_f[0]:=0]
|
||||
1215169 t.out.d.d[2].f : 0 [by t.registers.output_buf.f_buf_func[2]._y:=1]
|
||||
1215219 t.registers.output_buf.t_buf_func[3]._y : 1 [by t.registers.output_buf._out_a_BX_t[0]:=0]
|
||||
1215431 t.out.d.d[3].t : 0 [by t.registers.output_buf.t_buf_func[3]._y:=1]
|
||||
1217642 t.registers.output_buf.f_buf_func[1]._y : 1 [by t.registers.output_buf._out_a_BX_f[0]:=0]
|
||||
1225054 t.out.d.d[1].f : 0 [by t.registers.output_buf.f_buf_func[1]._y:=1]
|
||||
1249551 t.out.d.d[3].f : 0 [by t.registers.output_buf.f_buf_func[3]._y:=1]
|
||||
1249551 t.in.d.d[0].f : 0
|
||||
1249551 t.registers.ack_read_and.a : 0
|
||||
1249551 t.registers.atree[0].in[0] : 0
|
||||
1249551 t.in.d.d[1].f : 0
|
||||
1249551 t.registers.atree[0].in[1] : 0
|
||||
1249555 t.registers.word_to_read[0]._y : 1 [by t.registers.ack_read_and.a:=0]
|
||||
1249556 t.registers.val_input.OR2_tf[3]._y : 1 [by t.registers.atree[0].in[1]:=0]
|
||||
1249577 t.registers.atree[0].and2s[0]._y : 1 [by t.registers.atree[0].in[0]:=0]
|
||||
1249596 t.registers._out_encoder[0] : 0 [by t.registers.atree[0].and2s[0]._y:=1]
|
||||
1249612 t.registers.val_input.OR2_tf[1]._y : 1 [by t.in.d.d[1].f:=0]
|
||||
1249627 t.registers.word_to_read[0].y : 0 [by t.registers.word_to_read[0]._y:=1]
|
||||
1249629 t.registers.address_propagator_f[0]._y : 1 [by t.registers.ack_read_and.a:=0]
|
||||
1249664 t.registers.address_propagator_f[0].y : 0 [by t.registers.address_propagator_f[0]._y:=1]
|
||||
1249667 t.registers.val_input.ct.in[3] : 0 [by t.registers.val_input.OR2_tf[3]._y:=1]
|
||||
1249676 t.registers.word_to_read_X[0].buf1._y : 1 [by t.registers.word_to_read[0].y:=0]
|
||||
1249690 t.registers.ack_read_and._y : 1 [by t.registers.ack_read_and.a:=0]
|
||||
1249695 t.registers.and_encoder[0]._y : 1 [by t.registers._out_encoder[0]:=0]
|
||||
1249718 t.registers._in_a_read : 0 [by t.registers.ack_read_and._y:=1]
|
||||
1249815 t.registers.val_input.OR2_tf[2]._y : 1 [by t.registers.atree[0].in[0]:=0]
|
||||
1249875 t.registers.val_input.ct.in[2] : 0 [by t.registers.val_input.OR2_tf[2]._y:=1]
|
||||
1249906 t.registers.val_input.OR2_tf[4]._y : 1 [by t.registers.ack_read_and.a:=0]
|
||||
1249979 t.registers.val_input.ct.in[1] : 0 [by t.registers.val_input.OR2_tf[1]._y:=1]
|
||||
1250682 t.registers._clock_word_temp[0] : 0 [by t.registers.and_encoder[0]._y:=1]
|
||||
1252484 t.registers.val_input.OR2_tf[0]._y : 1 [by t.in.d.d[0].f:=0]
|
||||
1252785 t.registers.clock_buffer[0].buf1._y : 1 [by t.registers._clock_word_temp[0]:=0]
|
||||
1254500 t.registers.word_selector_f[0].a : 0 [by t.registers.word_to_read_X[0].buf1._y:=1]
|
||||
1254501 t.registers.word_selector_t[1]._y : 1 [by t.registers.word_selector_f[0].a:=0]
|
||||
1254504 t.registers.word_selector_t[1].y : 0 [by t.registers.word_selector_t[1]._y:=1]
|
||||
1255841 t.registers.output_buf.vc.OR2_tf[2]._y : 1 [by t.registers.address_propagator_f[0].y:=0]
|
||||
1257310 t.registers.output_buf.vc.ct.in[2] : 0 [by t.registers.output_buf.vc.OR2_tf[2]._y:=1]
|
||||
1259476 t.registers.val_input.ct.in[4] : 0 [by t.registers.val_input.OR2_tf[4]._y:=1]
|
||||
1259506 t.registers.val_input.ct.C3Els[0]._y : 1 [by t.registers.val_input.ct.in[4]:=0]
|
||||
1259512 t.registers.val_input.ct.tmp[6] : 0 [by t.registers.val_input.ct.C3Els[0]._y:=1]
|
||||
1263702 t.registers.ff[0].clk_B : 0 [by t.registers.clock_buffer[0].buf1._y:=1]
|
||||
1263703 t.registers.ff[0]._clk_B : 1 [by t.registers.ff[0].clk_B:=0]
|
||||
1263706 t.registers.ff[0].__clk_B : 0 [by t.registers.ff[0]._clk_B:=1]
|
||||
1263792 t.registers.ff[0]._sqib : 1 [by t.registers.ff[0].__clk_B:=0]
|
||||
1263829 t.registers.ff[1]._clk_B : 1 [by t.registers.ff[0].clk_B:=0]
|
||||
1264724 t.registers.ff[0]._sqi : 0 [by t.registers.ff[0]._sqib:=1]
|
||||
1265285 t.data[0].d[0] : 0 [by t.registers.ff[0]._sqib:=1]
|
||||
1270192 t.registers.val_input.ct.in[0] : 0 [by t.registers.val_input.OR2_tf[0]._y:=1]
|
||||
1270221 t.registers.ack_readwrite._y : 1 [by t.registers._in_a_read:=0]
|
||||
1270222 t.registers._in_a_temp : 0 [by t.registers.ack_readwrite._y:=1]
|
||||
1270466 t.registers.val_input.ct.C2Els[0]._y : 1 [by t.registers.val_input.ct.in[0]:=0]
|
||||
1272552 t.registers.ff[1].__clk_B : 0 [by t.registers.ff[1]._clk_B:=1]
|
||||
1272554 t.registers.ff[1]._sqib : 1 [by t.registers.ff[1].__clk_B:=0]
|
||||
1272913 t.registers.ff[1]._sqi : 0 [by t.registers.ff[1]._sqib:=1]
|
||||
1273168 t.registers.bitselector_t[1].or2s[0]._y : 1 [by t.registers.word_selector_t[1].y:=0]
|
||||
1274570 t.data[0].d[1] : 0 [by t.registers.ff[1]._sqib:=1]
|
||||
1274572 t.registers.ff[1].q_B : 1 [by t.data[0].d[1]:=0]
|
||||
1278373 t.registers.ack_input_X.buf4._y : 1 [by t.registers._in_a_temp:=0]
|
||||
1279638 t.registers.ff[0].q_B : 1 [by t.data[0].d[0]:=0]
|
||||
1280241 t.registers.word_selector_t[0]._y : 1 [by t.registers.word_selector_f[0].a:=0]
|
||||
1280244 t.registers.word_selector_t[0].y : 0 [by t.registers.word_selector_t[0]._y:=1]
|
||||
1287756 t.registers.address_propagator_f[1]._y : 1 [by t.registers.ack_read_and.a:=0]
|
||||
1288100 t.registers.address_propagator_f[1].y : 0 [by t.registers.address_propagator_f[1]._y:=1]
|
||||
1289883 t.registers.output_buf.vc.OR2_tf[3]._y : 1 [by t.registers.address_propagator_f[1].y:=0]
|
||||
1289912 t.registers.output_buf.vc.ct.in[3] : 0 [by t.registers.output_buf.vc.OR2_tf[3]._y:=1]
|
||||
1289983 t.registers.output_buf.vc.ct.C2Els[1]._y : 1 [by t.registers.output_buf.vc.ct.in[3]:=0]
|
||||
1290311 t.registers.val_input.ct.tmp[5] : 0 [by t.registers.val_input.ct.C2Els[0]._y:=1]
|
||||
1290345 t.registers.output_buf.vc.ct.tmp[5] : 0 [by t.registers.output_buf.vc.ct.C2Els[1]._y:=1]
|
||||
1290394 t.registers.val_input.ct.C2Els[1]._y : 1 [by t.registers.val_input.ct.tmp[5]:=0]
|
||||
1292804 t.in.a : 0 [by t.registers.ack_input_X.buf4._y:=1]
|
||||
1297679 t.registers.bitselector_t[1].tmp[4] : 0 [by t.registers.bitselector_t[1].or2s[0]._y:=1]
|
||||
1297786 t.registers.bitselector_t[1].or2s[2]._y : 1 [by t.registers.bitselector_t[1].tmp[4]:=0]
|
||||
1297789 t.registers.bitselector_t[1].out : 0 [by t.registers.bitselector_t[1].or2s[2]._y:=1]
|
||||
1297790 t.registers.output_buf.vc.OR2_tf[1]._y : 1 [by t.registers.bitselector_t[1].out:=0]
|
||||
1297791 t.registers.output_buf.vc.ct.in[1] : 0 [by t.registers.output_buf.vc.OR2_tf[1]._y:=1]
|
||||
1317533 t.registers.bitselector_t[0].or2s[0]._y : 1 [by t.registers.word_selector_t[0].y:=0]
|
||||
1321878 t.registers.bitselector_t[0].tmp[4] : 0 [by t.registers.bitselector_t[0].or2s[0]._y:=1]
|
||||
1322736 t.registers.bitselector_t[0].or2s[2]._y : 1 [by t.registers.bitselector_t[0].tmp[4]:=0]
|
||||
1322748 t.registers.bitselector_t[0].out : 0 [by t.registers.bitselector_t[0].or2s[2]._y:=1]
|
||||
1338556 t.registers._in_v_temp : 0 [by t.registers.val_input.ct.C2Els[1]._y:=1]
|
||||
1359177 t.registers.output_buf.vc.OR2_tf[0]._y : 1 [by t.registers.bitselector_t[0].out:=0]
|
||||
1389525 t.registers.val_input_X.buf4._y : 1 [by t.registers._in_v_temp:=0]
|
||||
1392523 t.registers.output_buf.vc.ct.in[0] : 0 [by t.registers.output_buf.vc.OR2_tf[0]._y:=1]
|
||||
1392551 t.registers.output_buf.vc.ct.C2Els[0]._y : 1 [by t.registers.output_buf.vc.ct.in[0]:=0]
|
||||
1392559 t.registers.output_buf.vc.ct.tmp[4] : 0 [by t.registers.output_buf.vc.ct.C2Els[0]._y:=1]
|
||||
1394506 t.in.v : 0 [by t.registers.val_input_X.buf4._y:=1]
|
||||
1413914 t.registers.output_buf.vc.ct.C2Els[2]._y : 1 [by t.registers.output_buf.vc.ct.tmp[4]:=0]
|
||||
1448245 t.registers.output_buf._in_v : 0 [by t.registers.output_buf.vc.ct.C2Els[2]._y:=1]
|
||||
1448510 t.registers.output_buf.in_v_buf4._y : 1 [by t.registers.output_buf._in_v:=0]
|
||||
1448589 t.registers.output_buf.in.v : 0 [by t.registers.output_buf.in_v_buf4._y:=1]
|
||||
1448597 t.registers.output_buf.in_v_bufN.buf1._y : 1 [by t.registers.output_buf.in.v:=0]
|
||||
1448638 t.registers.output_buf._in_vX[0] : 0 [by t.registers.output_buf.in_v_bufN.buf1._y:=1]
|
||||
WRONG ASSERT: "t.registers.ff[0].q" has value 0 and not 1.
|
||||
WRONG ASSERT: "t.registers.ff[1].q" has value 0 and not 1.
|
||||
[4] reading done
|
||||
----------------------------------------------------------
|
||||
Binary file not shown.
File diff suppressed because it is too large.
Load diff
@@ -31,9 +31,9 @@ import globals;
|
||||
|
||||
open tmpl::dataflow_neuro;
|
||||
// 2 bits encoder, 2 bits long words, 2 delays????
|
||||
defproc register_test (avMx1of2<1+2+2> in; avMx1of2<2+2> out;d1of<2> data[1<<2]; bool? dly_cfg[2]){
|
||||
defproc register_test (avMx1of2<1+2+2> in; avMx1of2<2+2> out;d1of<2> data[1<<2]; bool? dly_cfg[3]){
|
||||
|
||||
register_rw<2,2,2> registers(.in=in,.data = data,.out = out);
|
||||
register_rw<2,2,3> registers(.in=in,.data = data,.out = out);
|
||||
//Low active Reset
|
||||
bool _reset_B;
|
||||
power _supply;
|
||||
|
||||
@@ -1,4 +1,9 @@
|
||||
watchall
|
||||
watch t.registers.clock_buffer[0].out[0]
|
||||
watch t.registers.clock_buffer[1].out[0]
|
||||
watch t.registers.clock_buffer[2].out[0]
|
||||
watch t.registers.clock_buffer[3].out[0]
|
||||
|
||||
|
||||
system "echo '[0] start test'"
|
||||
system "echo '----------------------------------------------------------'"
|
||||
|
||||
@@ -10,21 +15,32 @@ set t.data[1].d[0] 0
|
||||
set t.data[1].d[1] 0
|
||||
set t.dly_cfg[0] 1
|
||||
set t.dly_cfg[1] 1
|
||||
set t.dly_cfg[2] 1
|
||||
|
||||
set t.out.a 0
|
||||
set t.out.v 0
|
||||
cycle
|
||||
#set t.registers._in_write.a 0
|
||||
set t.in.a 0
|
||||
set Reset 0
|
||||
set t.dly_cfg[0] 1
|
||||
set t.dly_cfg[1] 1
|
||||
cycle
|
||||
assert-qdi-channel-neutral "t.in" 5
|
||||
assert-qdi-channel-neutral "t.out" 4
|
||||
# There shouldnt be any status X
|
||||
status X
|
||||
#mode run
|
||||
mode run
|
||||
cycle
|
||||
|
||||
# check delay config programming
|
||||
assert t.registers.clk_dly.s[0] 1
|
||||
assert t.registers.clk_dly.s[1] 1
|
||||
|
||||
assert t.registers.ff[0].q 0
|
||||
assert t.registers.ff[1].q 0
|
||||
assert t.registers.ff[2].q 0
|
||||
assert t.registers.ff[3].q 0
|
||||
assert t.registers.ff[4].q 0
|
||||
assert t.registers.ff[5].q 0
|
||||
assert t.registers.ff[6].q 0
|
||||
assert t.registers.ff[7].q 0
|
||||
|
||||
assert-qdi-channel-neutral "t.out" 4
|
||||
assert t.data[0].d[0] 0
|
||||
assert t.data[0].d[1] 0
|
||||
@@ -34,20 +50,17 @@ cycle
|
||||
system "echo '[1] reset completed'"
|
||||
system "echo '----------------------------------------------------------'"
|
||||
|
||||
# Set delay config lines
|
||||
|
||||
cycle
|
||||
system "echo '[2] delay line set'"
|
||||
system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
set-qdi-channel-valid "t.in" 5 3
|
||||
# 3 -> 00011 -> writing mode, address 00, word 11
|
||||
cycle
|
||||
|
||||
assert t.in.a 1
|
||||
assert-qdi-channel-neutral "t.out" 4
|
||||
assert t.registers._in_v_temp 1
|
||||
set-qdi-channel-neutral "t.in" 5
|
||||
cycle
|
||||
assert t.registers._in_v_temp 0
|
||||
|
||||
assert t.registers.ff[0].q 1
|
||||
assert t.registers.ff[1].q 1
|
||||
assert t.registers.ff[2].q 0
|
||||
@@ -56,31 +69,397 @@ assert t.registers.ff[4].q 0
|
||||
assert t.registers.ff[5].q 0
|
||||
assert t.registers.ff[6].q 0
|
||||
assert t.registers.ff[7].q 0
|
||||
assert t.in.v 0
|
||||
|
||||
set t.out.a 0
|
||||
set t.out.v 0
|
||||
assert t.in.a 0
|
||||
cycle
|
||||
assert t.registers._clock_temp_inv 1
|
||||
|
||||
system "echo '[3] first writing done'"
|
||||
system "echo '----------------------------------------------------------'"
|
||||
|
||||
set-qdi-channel-valid "t.in" 5 16
|
||||
# 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here)
|
||||
cycle
|
||||
assert t.registers._clock_temp_inv 1
|
||||
assert-qdi-channel-valid "t.out" 4 3
|
||||
set t.out.v 1
|
||||
cycle
|
||||
set t.out.a 1
|
||||
assert t.registers._clock_temp_inv 1
|
||||
cycle
|
||||
assert t.in.a 1
|
||||
set-qdi-channel-neutral "t.in" 5
|
||||
assert t.registers._clock_temp_inv 1
|
||||
cycle
|
||||
assert t.registers._clock_temp_inv 1
|
||||
assert t.registers.ff[0].q 1
|
||||
assert t.registers.ff[1].q 1
|
||||
assert t.registers.ff[2].q 0
|
||||
assert t.registers.ff[3].q 0
|
||||
assert-qdi-channel-neutral "t.out" 4
|
||||
system "echo '[4] reading done'"
|
||||
system "echo '----------------------------------------------------------'"
|
||||
# set-qdi-channel-valid "t.in" 5 16
|
||||
# # 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here)
|
||||
# cycle
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
|
||||
# assert t.registers.word_to_read_X[0].out[0] 1
|
||||
# assert t.registers.word_to_read_X[0].out[1] 1
|
||||
# assert t.registers.word_to_read_X[0].out[2] 1
|
||||
# assert t.registers.word_to_read_X[0].out[3] 1
|
||||
|
||||
# assert-qdi-channel-valid "t.out" 4 3
|
||||
# set t.out.v 1
|
||||
# cycle
|
||||
# set t.out.a 1
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
# cycle
|
||||
# assert t.in.a 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
# cycle
|
||||
# assert t.registers.ff[0].q 1
|
||||
# assert t.registers.ff[1].q 1
|
||||
# assert t.registers.ff[2].q 0
|
||||
# assert t.registers.ff[3].q 0
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[4] reading done'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 7
|
||||
# # 7 -> 00111 -> writing mode, address 01, word 11
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 1
|
||||
# assert t.registers.ff[1].q 1
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 0
|
||||
# assert t.registers.ff[5].q 0
|
||||
# assert t.registers.ff[6].q 0
|
||||
# assert t.registers.ff[7].q 0
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# cycle
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
|
||||
# system "echo '[5] second writing done'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 11
|
||||
# # 11 -> 01011 -> writing mode, address 10, word 11
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 1
|
||||
# assert t.registers.ff[1].q 1
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 0
|
||||
# assert t.registers.ff[7].q 0
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[6] third writing done'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 15
|
||||
# # 15 -> 01111 -> writing mode, address 11, word 11
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 1
|
||||
# assert t.registers.ff[1].q 1
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 1
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[7] fourth writing done'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 28
|
||||
# # 28 -> 11100 -> reading mode, address 11, word 00 (word doesnt needed here)
|
||||
# cycle
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
|
||||
# assert-qdi-channel-valid "t.out" 4 15
|
||||
# set t.out.v 1
|
||||
# cycle
|
||||
# set t.out.a 1
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
# cycle
|
||||
# assert t.in.a 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
# cycle
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[8] 11 reading done'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 20
|
||||
# # 20 -> 10100 -> reading mode, address 01, word 00 (word doesnt needed here)
|
||||
# cycle
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
|
||||
# assert-qdi-channel-valid "t.out" 4 7
|
||||
# set t.out.v 1
|
||||
# cycle
|
||||
# set t.out.a 1
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
# cycle
|
||||
# assert t.in.a 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
# cycle
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] 01 reading done'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 24
|
||||
# # 24 -> 11000 -> reading mode, address 10, word 00 (word doesnt needed here)
|
||||
# cycle
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
|
||||
# assert-qdi-channel-valid "t.out" 4 11
|
||||
# set t.out.v 1
|
||||
# cycle
|
||||
# set t.out.a 1
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
# cycle
|
||||
# assert t.in.a 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# assert t.registers._clock_temp_inv 1
|
||||
# cycle
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[8] 10 reading done'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 13
|
||||
# # 13 -> 01101 -> writing mode, address 11, word 01
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 1
|
||||
# assert t.registers.ff[1].q 1
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 1
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 0
|
||||
# # 13 -> 00000 -> writing mode, address 00, word 00
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 0
|
||||
# assert t.registers.ff[1].q 0
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 1
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 0
|
||||
# # 0 -> 00000 -> writing mode, address 00, word 00
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 0
|
||||
# assert t.registers.ff[1].q 0
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 0
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 0
|
||||
# # 0 -> 00000 -> writing mode, address 00, word 00
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 0
|
||||
# assert t.registers.ff[1].q 0
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 0
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 0
|
||||
# # 13 -> 00000 -> writing mode, address 00, word 00
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 0
|
||||
# assert t.registers.ff[1].q 0
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 0
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
# set-qdi-channel-valid "t.in" 5 3
|
||||
# # 13 -> 00011 -> writing mode, address 00, word 11
|
||||
# cycle
|
||||
|
||||
# assert t.in.a 1
|
||||
# assert-qdi-channel-neutral "t.out" 4
|
||||
# assert t.registers._in_v_temp 1
|
||||
# set-qdi-channel-neutral "t.in" 5
|
||||
# cycle
|
||||
# assert t.registers._in_v_temp 0
|
||||
|
||||
# assert t.registers.ff[0].q 1
|
||||
# assert t.registers.ff[1].q 1
|
||||
# assert t.registers.ff[2].q 1
|
||||
# assert t.registers.ff[3].q 1
|
||||
# assert t.registers.ff[4].q 1
|
||||
# assert t.registers.ff[5].q 1
|
||||
# assert t.registers.ff[6].q 1
|
||||
# assert t.registers.ff[7].q 0
|
||||
# assert t.in.v 0
|
||||
|
||||
# set t.out.a 0
|
||||
# set t.out.v 0
|
||||
# assert t.in.a 0
|
||||
# cycle
|
||||
|
||||
# system "echo '[9] Rewrite 11 to 01'"
|
||||
# system "echo '----------------------------------------------------------'"
|
||||
|
||||
|
||||
|
||||
Reference in new issue
Block a user