fixed unit tests

test/unit_tests/nrn_hs_2d/test.act

@@ -33,14 +33,33 @@ open tmpl::dataflow_neuro;
 
 defproc nrn_hs_2d_inst(a1of1 in; a1of1 outx, outy)
 {
+	power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
 	bool _reset_B; 
 	prs {
 		Reset => _reset_B-
 	}
-  nrn_hs_2d b(.in = in, .outx = outx, .outy = outy);
-  b.supply.vdd = Vdd;
-  b.supply.vss = GND; 
-  b.reset_B = _reset_B;
+	nrn_hs_2d b(.in = in, .outx = outx, .outy = outy,
+		.supply = supply, .reset_B = _reset_B);
+
+	nrn_line_end_pull_down pd_x;
+	pd_x.in = b.outx.a;
+	pd_x.out = b.outx.r;
+	pd_x.supply = supply;
+	pd_x.reset_B = _reset_B;
+
+	nrn_line_end_pull_down pd_y;
+	pd_y.in = b.outy.a;
+	pd_y.out = b.outy.r;
+	pd_y.supply = supply;
+	pd_y.reset_B = _reset_B;
+	
+
+
+	
+
 }
 
 nrn_hs_2d_inst b;

test/unit_tests/nrn_hs_2d/test.prsim

@@ -1,202 +1,76 @@
 watchall
 
-set b.in[0].r 0
-set b.in[1].r 0
-set b.in[2].r 0
-set b.in[3].r 0
-set b.in[4].r 0
-set b.in[5].r 0
-set b.in[6].r 0
-set b.in[7].r 0
-set b.in[8].r 0
-set b.in[9].r 0
-set b.in[10].r 0
-set b.in[11].r 0
-set b.in[12].r 0
-set b.in[13].r 0
-set b.in[14].r 0
+set b.in.r 0
 
-set b.outx[0].a 0
-set b.outx[1].a 0
-set b.outx[2].a 0
-
-set b.outy[0].a 0
-set b.outy[1].a 0
-set b.outy[2].a 0
-set b.outy[3].a 0
-set b.outy[4].a 0
-
-set b.outx[0].r 1
-set b.outx[1].r 1
-set b.outx[2].r 1
-
-set b.outy[0].r 1
-set b.outy[1].r 1
-set b.outy[2].r 1
-set b.outy[3].r 1
-set b.outy[4].r 0
-
-set b.b.neurons[0]._en 0
-set b.b.neurons[0]._req 1
-
-# set Reset 0
-cycle
+set b.outx.a 0
+set b.outy.a 0
 
 system "echo '[] set Reset 1'"
 set Reset 1
 cycle
 status X
 
-
 system "echo '[] set Reset 0'"
 set Reset 0
 mode run
 cycle
+status X
 
-assert b.outx[0].r 0
-assert b.outx[1].r 0
-assert b.outx[2].r 0
-
-assert b.outy[0].r 0
-assert b.outy[1].r 0
-assert b.outy[2].r 0
-assert b.outy[3].r 0
-assert b.outy[4].r 0
-
-
-system "echo '[] Neurons 0,1,3 spike'"
-set b.in[0].r 1
-set b.in[1].r 1
-set b.in[3].r 1
+# spike
+set b.in.r 1
 cycle
-assert b.outx[0].r 0
-assert b.outx[1].r 0
-assert b.outx[2].r 0
+assert b.outx.r 0
+assert b.outy.r 1
+assert b.in.a 1
 
-assert b.outy[0].r 1
-assert b.outy[1].r 1
-assert b.outy[2].r 0
-assert b.outy[3].r 0
-assert b.outy[4].r 0
-
-assert b.in[0].a 1
-assert b.in[1].a 1
-assert b.in[3].a 1
-
-system "echo '[] removing in reqs'"
-set b.in[0].r 0
-set b.in[1].r 0
-set b.in[3].r 0
+set b.in.r 0
+set b.outy.a 1
 cycle
-assert b.in[0].a 0
-assert b.in[1].a 0
-assert b.in[3].a 0
+assert b.outx.r 1
+assert b.in.a 0
 
-
-system "echo '[] y0 chosen, give ack'"
-set b.outy[0].a 1
+# send in another spike while its still dealing with previous
+set b.in.r 1
 cycle
-assert b.outx[0].r 1
-assert b.outx[1].r 1
-assert b.outx[2].r 0
+assert b.outx.r 1
+assert b.outy.r 0
+assert b.in.a 0
 
-assert b.outy[0].r 0
-assert b.outy[1].r 1
-assert b.outy[2].r 0
-assert b.outy[3].r 0
-assert b.outy[4].r 0
-
-system "echo '[] x0 chosen, give ack'"
-set b.outx[0].a 1
+set b.outx.a 1
 cycle
-assert b.outx[0].r 0
-assert b.outx[1].r 1
-assert b.outx[2].r 0
+assert b.outx.r 0
+assert b.outy.r 0
+assert b.in.a 0
 
-assert b.outy[0].r 0
-assert b.outy[1].r 1
-assert b.outy[2].r 0
-assert b.outy[3].r 0
-assert b.outy[4].r 0
-
-system "echo '[] remove x ack'"
-set b.outx[0].a 0
+set b.outx.a 0
+set b.outy.a 0
 cycle
-assert b.outx[0].r 0
-assert b.outx[1].r 1
-assert b.outx[2].r 0
+assert b.outy.r 1
+assert b.outx.r 0
+assert b.in.a 1
 
-assert b.outy[0].r 0
-assert b.outy[1].r 1
-assert b.outy[2].r 0
-assert b.outy[3].r 0
-assert b.outy[4].r 0
-
-system "echo '[] x1 remaining, give ack'"
-set b.outx[1].a 1
+set b.in.r 0
+set b.outy.a 1
 cycle
-assert b.outx[0].r 0
-assert b.outx[1].r 0
-assert b.outx[2].r 0
+assert b.outx.r 1
+assert b.outy.r 0
+assert b.in.a 0
 
-assert b.outy[0].r 0
-assert b.outy[1].r 1
-assert b.outy[2].r 0
-assert b.outy[3].r 0
-assert b.outy[4].r 0
-
-system "echo '[] remove acks'"
-set b.outx[1].a 0
-set b.outy[0].a 0
+set b.outx.a 1
 cycle
-assert b.outx[0].r 0
-assert b.outx[1].r 0
-assert b.outx[2].r 0
+assert b.outx.r 0
+assert b.outy.r 0
 
-assert b.outy[0].r 0
-assert b.outy[1].r 1
-assert b.outy[2].r 0
-assert b.outy[3].r 0
-assert b.outy[4].r 0
-
-system "echo '[] y1 remaining, give ack'"
-set b.outy[1].a 1
+set b.outx.a 0
+set b.outy.a 0
 cycle
-assert b.outx[0].r 1
-assert b.outx[1].r 0
-assert b.outx[2].r 0
-
-assert b.outy[0].r 0
-assert b.outy[1].r 0
-assert b.outy[2].r 0
-assert b.outy[3].r 0
-assert b.outy[4].r 0
-
-system "echo '[] x0 req, give ack'"
-set b.outx[0].a 1
-cycle
-assert b.outx[0].r 0
-assert b.outx[1].r 0
-assert b.outx[2].r 0
-
-assert b.outy[0].r 0
-assert b.outy[1].r 0
-assert b.outy[2].r 0
-assert b.outy[3].r 0
-assert b.outy[4].r 0
+assert b.outx.r 0
+assert b.outy.r 0
+assert b.in.a 0
+
+
+
 
 
-system "echo '[] remove acks'"
-set b.outx[0].a 0
-set b.outy[1].a 0
-cycle
-assert b.outx[0].r 0
-assert b.outx[1].r 0
-assert b.outx[2].r 0
 
-assert b.outy[0].r 0
-assert b.outy[1].r 0
-assert b.outy[2].r 0
-assert b.outy[3].r 0
-assert b.outy[4].r 0
 

test/unit_tests/registerA_w/test.act

@@ -44,7 +44,7 @@ defproc registerA_w (avMx1of2<8> in; Mx1of2<7> out){
     supply.vdd = Vdd;
     supply.vss = GND;
 
-    registerA<7> b(.in = in, .out = out, .reset_B = _reset_B, .supply = supply);
+    register_acells_improved<7> b(.in = in, .out = out, .reset_B = _reset_B, .supply = supply);
 }
 
 

test/unit_tests/registerA_w_array/test.act

@@ -35,7 +35,7 @@ open std::data;
 
 open tmpl::dataflow_neuro;
 
-defproc registerA_w_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]){
+defproc registerA_w_array_3x5x8 (avMx1of2<3+5> in; Mx1of2<5> data[8]){
     bool _reset_B; 
     prs {
         Reset => _reset_B-
@@ -46,7 +46,7 @@ defproc registerA_w_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]){
 
     // Make a register array with 3 bit address (-> 8 registers), 
     // each register holding 5 bits.
-    registerA_w_array<3,5,8> b(.in = in, .data = data, .reset_B = _reset_B, .supply = supply);
+    register_w_array<3,5,8> b(.in = in, .data = data, .reset_B = _reset_B, .supply = supply);
 }
 
 

test/unit_tests/registerA_w_array/test.prsim

@@ -1,6 +1,6 @@
 watchall
 
-set-qdi-channel-neutral "b.in" 9
+set-qdi-channel-neutral "b.in" 8
 cycle
 
 
@@ -13,42 +13,42 @@ assert b.in.a 0
 assert b.in.v 0
 
 system "echo '[] Sending packet write 0s to reg0'"
-set-qdi-channel-valid "b.in" 9 256
+set-qdi-channel-valid "b.in" 8 256
 cycle
 assert b.in.a 1
 assert b.in.v 1
 assert-var-int "b.data[0]" 5 0
 
 system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
+set-qdi-channel-neutral "b.in" 8
 cycle
 assert b.in.a 0
 assert b.in.v 0
 assert-var-int "b.data[0]" 5 0
 
 system "echo '[] Sending packet write 0s to reg0'"
-set-qdi-channel-valid "b.in" 9 256
+set-qdi-channel-valid "b.in" 8 256
 cycle
 assert b.in.a 1
 assert b.in.v 1
 assert-var-int "b.data[0]" 5 0
 
 system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
+set-qdi-channel-neutral "b.in" 8
 cycle
 assert b.in.a 0
 assert b.in.v 0
 assert-var-int "b.data[0]" 5 0
 
 system "echo '[] Sending packet write 01100 to reg0'"
-set-qdi-channel-valid "b.in" 9 352
+set-qdi-channel-valid "b.in" 8 352
 cycle
 assert b.in.a 1
 assert b.in.v 1
 assert-var-int "b.data[0]" 5 12
 
 system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
+set-qdi-channel-neutral "b.in" 8
 cycle
 assert b.in.a 0
 assert b.in.v 0
@@ -56,88 +56,88 @@ assert-var-int "b.data[0]" 5 12
 
 
 system "echo '[] Sending packet write 0s to reg1'"
-set-qdi-channel-valid "b.in" 9 257
+set-qdi-channel-valid "b.in" 8 257
 cycle
 assert b.in.a 1
 assert b.in.v 1
 assert-var-int "b.data[1]" 5 0
 
 system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
+set-qdi-channel-neutral "b.in" 8
 cycle
 assert b.in.a 0
 assert b.in.v 0
 
 system "echo '[] Sending packet write 0s to reg2'"
-set-qdi-channel-valid "b.in" 9 258
+set-qdi-channel-valid "b.in" 8 258
 cycle
 assert b.in.a 1
 assert b.in.v 1
 assert-var-int "b.data[2]" 5 0
 
 system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
+set-qdi-channel-neutral "b.in" 8
 cycle
 assert b.in.a 0
 assert b.in.v 0
 assert-var-int "b.data[2]" 5 0
 
 system "echo '[] Sending packet write 0s to reg3'"
-set-qdi-channel-valid "b.in" 9 259
+set-qdi-channel-valid "b.in" 8 259
 cycle
 assert b.in.a 1
 assert b.in.v 1
 
 system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
+set-qdi-channel-neutral "b.in" 8
 cycle
 assert b.in.a 0
 assert b.in.v 0
 
 system "echo '[] Sending packet write 0s to reg4'"
-set-qdi-channel-valid "b.in" 9 260
+set-qdi-channel-valid "b.in" 8 260
 cycle
 assert b.in.a 1
 assert b.in.v 1
 
 system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
+set-qdi-channel-neutral "b.in" 8
 cycle
 assert b.in.a 0
 assert b.in.v 0
 
 system "echo '[] Sending packet write 0s to reg5'"
-set-qdi-channel-valid "b.in" 9 261
+set-qdi-channel-valid "b.in" 8 261
 cycle
 assert b.in.a 1
 assert b.in.v 1
 
 system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
+set-qdi-channel-neutral "b.in" 8
 cycle
 assert b.in.a 0
 assert b.in.v 0
 
 system "echo '[] Sending packet write 0s to reg6'"
-set-qdi-channel-valid "b.in" 9 262
+set-qdi-channel-valid "b.in" 8 262
 cycle
 assert b.in.a 1
 assert b.in.v 1
 
 system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
+set-qdi-channel-neutral "b.in" 8
 cycle
 assert b.in.a 0
 assert b.in.v 0
 
 system "echo '[] Sending packet write 0s to reg7'"
-set-qdi-channel-valid "b.in" 9 263
+set-qdi-channel-valid "b.in" 8 263
 cycle
 assert b.in.a 1
 assert b.in.v 1
 
 system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
+set-qdi-channel-neutral "b.in" 8
 cycle
 assert b.in.a 0
 assert b.in.v 0

test/unit_tests/registerA_wr_array/test.act

@@ -46,7 +46,7 @@ defproc registerA_wr_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]; avMx1of
 
     // Make a register array with 3 bit address (-> 8 registers), 
     // each register holding 5 bits.
-    registerA_wr_array<3,5,8> b(.in = in, .data = data, .out = out,
+    register_wr_array<3,5,8> b(.in = in, .data = data, .out = out,
         .reset_B = _reset_B, .supply = supply);
 }
 

test/unit_tests/register_write/test.act

@@ -1,52 +0,0 @@
-/*************************************************************************
- *
- *  This file is part of ACT dataflow neuro library.
- * It's the testing facility for cell_lib_std.act
- *
- *  Copyright (c) 2022 University of Groningen - Ole Richter  
- *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
- *  Copyright (c) 2022 University of Groningen - Michele Mastella
- *  Copyright (c) 2022 University of Groningen - Madison Cotteret
- *
- *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
- *
- *  You may redistribute and modify this documentation and make products
- *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
- *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
- *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
- *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
- *  for applicable conditions.
- *
- *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
- *
- *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
- *  these sources, You must maintain the Source Location visible in its
- *  documentation.
- *
- **************************************************************************
- */
-
-import "../../dataflow_neuro/registers.act";
-import globals;
-
-open tmpl::dataflow_neuro;
-// 2 bits encoder, 2 bits long words, 2 delays????
-defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[1<<2]; bool? dly_cfg[2]){
-
-    register_w<2,2,2> registers(.in=in,.data = data);
-    //Low active Reset 
-    bool _reset_B; 
-    power _supply;
-    prs {
-    	Reset => _reset_B-
-    }
-    registers.supply = _supply;
-    _supply.vss = GND;
-    _supply.vdd = Vdd;
-    registers.reset_B = _reset_B;
-    registers.reset_mem_B = _reset_B;
-    registers.dly_cfg = dly_cfg;
-    
-}
-
-register_test t;

test/unit_tests/register_write/test.prsim

@@ -1,49 +0,0 @@
-watchall
-system "echo '[0] start test'"
-
-set-qdi-channel-neutral "t.in" 5
-
-set t.data[0].d[0] 0
-set t.data[0].d[1] 0
-set t.data[1].d[0] 0
-set t.data[1].d[1] 0
-
-set t.registers._in_write.a 0
-set t.registers._in_read.a 0
-set t.registers._in_write.v 0
-set t.registers._in_read.v 0
-
-set Reset 0
-cycle
-status X
-mode run
-assert-qdi-channel-neutral "t.in" 5
-assert t.data[0].d[0] 0
-assert t.data[0].d[1] 0
-assert t.data[1].d[0] 0
-assert t.data[1].d[1] 0
-cycle
-system "echo '[1] reset completed'"
-# Set delay config lines
-set t.dly_cfg[0] 1
-set t.dly_cfg[1] 1
-cycle
-assert-qdi-channel-neutral "t.in" 5
-system "echo '[2] delay line set'"
-set-qdi-channel-valid "t.in" 5 19
-cycle
-assert-qdi-channel-valid "t.registers._in_write" 4 3
-assert t.registers._clock 0
-assert t.registers._out_encoder[0] 1
-assert t.registers._out_encoder[1] 0
-assert t.registers._out_encoder[2] 0
-assert t.registers._out_encoder[3] 0
-cycle
-set-qdi-channel-neutral "t.in" 5
-cycle
-assert t.registers._clock 1
-assert t.registers.ff[0].q 1
-assert t.registers.ff[1].q 1
-system "echo '[3] clock checked'"
-
-

test/unit_tests/register_wrw/test.act

@@ -1,52 +0,0 @@
-/*************************************************************************
- *
- *  This file is part of ACT dataflow neuro library.
- * It's the testing facility for cell_lib_std.act
- *
- *  Copyright (c) 2022 University of Groningen - Ole Richter  
- *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
- *  Copyright (c) 2022 University of Groningen - Michele Mastella
- *  Copyright (c) 2022 University of Groningen - Madison Cotteret
- *
- *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
- *
- *  You may redistribute and modify this documentation and make products
- *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
- *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
- *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
- *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
- *  for applicable conditions.
- *
- *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
- *
- *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
- *  these sources, You must maintain the Source Location visible in its
- *  documentation.
- *
- **************************************************************************
- */
-
-import "../../dataflow_neuro/registers.act";
-import globals;
-
-open tmpl::dataflow_neuro;
-// 2 bits encoder, 2 bits long words, 2 delays????
-defproc register_test (avMx1of2<1+2+2> in; avMx1of2<2+2> out;d1of<2> data[1<<2]; bool? dly_cfg[3]){
-
-    register_rw<2,2,3> registers(.in=in,.data = data,.out = out);
-    //Low active Reset 
-    bool _reset_B; 
-    power _supply;
-    prs {
-    	Reset => _reset_B-
-    }
-    registers.supply = _supply;
-    _supply.vss = GND;
-    _supply.vdd = Vdd;
-    registers.reset_B = _reset_B;
-    registers.reset_mem_B = _reset_B;
-    registers.dly_cfg = dly_cfg;
-    
-}
-
-register_test t;

test/unit_tests/register_wrw/test.prsim

@@ -1,465 +0,0 @@
-watch t.registers.clock_buffer[0].out[0]
-watch t.registers.clock_buffer[1].out[0]
-watch t.registers.clock_buffer[2].out[0]
-watch t.registers.clock_buffer[3].out[0]
-
-
-system "echo '[0] start test'"
-system "echo '----------------------------------------------------------'"
-
-set-qdi-channel-neutral "t.in" 5
-set-qdi-channel-neutral "t.out" 4
-set t.data[0].d[0] 0
-set t.data[0].d[1] 0
-set t.data[1].d[0] 0
-set t.data[1].d[1] 0
-set t.dly_cfg[0] 1
-set t.dly_cfg[1] 1
-set t.dly_cfg[2] 1
-
-set t.out.a 0
-set t.out.v 0
-cycle
-set t.in.a 0
-set Reset 0
-cycle
-assert-qdi-channel-neutral "t.in" 5
-assert-qdi-channel-neutral "t.out" 4
-mode run
-cycle
-
-# check delay config programming 
-assert t.registers.clk_dly.s[0] 1
-assert t.registers.clk_dly.s[1] 1
-
-assert t.registers.ff[0].q 0
-assert t.registers.ff[1].q 0
-assert t.registers.ff[2].q 0
-assert t.registers.ff[3].q 0
-assert t.registers.ff[4].q 0
-assert t.registers.ff[5].q 0
-assert t.registers.ff[6].q 0
-assert t.registers.ff[7].q 0
-
-assert-qdi-channel-neutral "t.out" 4
-assert t.data[0].d[0] 0
-assert t.data[0].d[1] 0
-assert t.data[1].d[0] 0
-assert t.data[1].d[1] 0
-cycle
-system "echo '[1] reset completed'"
-system "echo '----------------------------------------------------------'"
-
-set-qdi-channel-valid "t.in" 5 3
-# 3 -> 00011 -> writing mode, address 00, word 11
-cycle
-
-assert t.in.a 1
-assert-qdi-channel-neutral "t.out" 4
-assert t.registers._in_v_temp 1
-set-qdi-channel-neutral "t.in" 5
-cycle
-assert t.registers._in_v_temp 0
-
-assert t.registers.ff[0].q 1
-assert t.registers.ff[1].q 1
-assert t.registers.ff[2].q 0
-assert t.registers.ff[3].q 0
-assert t.registers.ff[4].q 0
-assert t.registers.ff[5].q 0
-assert t.registers.ff[6].q 0
-assert t.registers.ff[7].q 0
-assert t.in.v 0
-
-set t.out.a 0
-set t.out.v 0
-assert t.in.a 0
-cycle 
-assert t.registers._clock_temp_inv 1
-
-system "echo '[3] first writing done'"
-system "echo '----------------------------------------------------------'"
-
-# set-qdi-channel-valid "t.in" 5 16
-# # 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here)
-# cycle
-# assert t.registers._clock_temp_inv 1
-
-# assert t.registers.word_to_read_X[0].out[0] 1
-# assert t.registers.word_to_read_X[0].out[1] 1
-# assert t.registers.word_to_read_X[0].out[2] 1
-# assert t.registers.word_to_read_X[0].out[3] 1
-
-# assert-qdi-channel-valid "t.out" 4 3
-# set t.out.v 1
-# cycle
-# set t.out.a 1
-# assert t.registers._clock_temp_inv 1
-# cycle
-# assert t.in.a 1
-# set-qdi-channel-neutral "t.in" 5
-# assert t.registers._clock_temp_inv 1
-# cycle
-# assert t.registers.ff[0].q 1
-# assert t.registers.ff[1].q 1
-# assert t.registers.ff[2].q 0
-# assert t.registers.ff[3].q 0
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle 
-
-# system "echo '[4] reading done'"
-# system "echo '----------------------------------------------------------'"
-
-
-# set-qdi-channel-valid "t.in" 5 7
-# # 7 -> 00111 -> writing mode, address 01, word 11
-# cycle
-
-# assert t.in.a 1
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 1
-
-# set-qdi-channel-neutral "t.in" 5
-# cycle
-# assert t.registers._in_v_temp 0
-
-# assert t.registers.ff[0].q 1
-# assert t.registers.ff[1].q 1
-# assert t.registers.ff[2].q 1
-# assert t.registers.ff[3].q 1
-# assert t.registers.ff[4].q 0
-# assert t.registers.ff[5].q 0
-# assert t.registers.ff[6].q 0
-# assert t.registers.ff[7].q 0
-# assert t.in.v 0
-
-# set t.out.a 0
-# set t.out.v 0
-# cycle 
-# assert t.registers._clock_temp_inv 1
-
-# system "echo '[5] second writing done'"
-# system "echo '----------------------------------------------------------'"
-
-# set-qdi-channel-valid "t.in" 5 11
-# # 11 -> 01011 -> writing mode, address 10, word 11
-# cycle
-
-# assert t.in.a 1
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 1
-# set-qdi-channel-neutral "t.in" 5
-# cycle
-# assert t.registers._in_v_temp 0
-
-# assert t.registers.ff[0].q 1
-# assert t.registers.ff[1].q 1
-# assert t.registers.ff[2].q 1
-# assert t.registers.ff[3].q 1
-# assert t.registers.ff[4].q 1
-# assert t.registers.ff[5].q 1
-# assert t.registers.ff[6].q 0
-# assert t.registers.ff[7].q 0
-# assert t.in.v 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle 
-
-# system "echo '[6] third writing done'"
-# system "echo '----------------------------------------------------------'"
-
-# set-qdi-channel-valid "t.in" 5 15
-# # 15 -> 01111 -> writing mode, address 11, word 11
-# cycle
-
-# assert t.in.a 1
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 1
-# set-qdi-channel-neutral "t.in" 5
-# cycle
-# assert t.registers._in_v_temp 0
-
-# assert t.registers.ff[0].q 1
-# assert t.registers.ff[1].q 1
-# assert t.registers.ff[2].q 1
-# assert t.registers.ff[3].q 1
-# assert t.registers.ff[4].q 1
-# assert t.registers.ff[5].q 1
-# assert t.registers.ff[6].q 1
-# assert t.registers.ff[7].q 1
-# assert t.in.v 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle 
-
-# system "echo '[7] fourth writing done'"
-# system "echo '----------------------------------------------------------'"
-
-# set-qdi-channel-valid "t.in" 5 28
-# # 28 -> 11100 -> reading mode, address 11, word 00 (word doesnt needed here)
-# cycle
-# assert t.registers._clock_temp_inv 1
-
-# assert-qdi-channel-valid "t.out" 4 15
-# set t.out.v 1
-# cycle
-# set t.out.a 1
-# assert t.registers._clock_temp_inv 1
-# cycle
-# assert t.in.a 1
-# set-qdi-channel-neutral "t.in" 5
-# assert t.registers._clock_temp_inv 1
-# cycle
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle 
-
-# system "echo '[8] 11 reading done'"
-# system "echo '----------------------------------------------------------'"
-
-# set-qdi-channel-valid "t.in" 5 20
-# # 20 -> 10100 -> reading mode, address 01, word 00 (word doesnt needed here)
-# cycle
-# assert t.registers._clock_temp_inv 1
-
-# assert-qdi-channel-valid "t.out" 4 7
-# set t.out.v 1
-# cycle
-# set t.out.a 1
-# assert t.registers._clock_temp_inv 1
-# cycle
-# assert t.in.a 1
-# set-qdi-channel-neutral "t.in" 5
-# assert t.registers._clock_temp_inv 1
-# cycle
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle 
-
-# system "echo '[9] 01 reading done'"
-# system "echo '----------------------------------------------------------'"
-
-# set-qdi-channel-valid "t.in" 5 24
-# # 24 -> 11000 -> reading mode, address 10, word 00 (word doesnt needed here)
-# cycle
-# assert t.registers._clock_temp_inv 1
-
-# assert-qdi-channel-valid "t.out" 4 11
-# set t.out.v 1
-# cycle
-# set t.out.a 1
-# assert t.registers._clock_temp_inv 1
-# cycle
-# assert t.in.a 1
-# set-qdi-channel-neutral "t.in" 5
-# assert t.registers._clock_temp_inv 1
-# cycle
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle
-
-# system "echo '[8] 10 reading done'"
-# system "echo '----------------------------------------------------------'"
-
-# set-qdi-channel-valid "t.in" 5 13
-# # 13 -> 01101 -> writing mode, address 11, word 01
-# cycle
-
-# assert t.in.a 1
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 1
-# set-qdi-channel-neutral "t.in" 5
-# cycle
-# assert t.registers._in_v_temp 0
-
-# assert t.registers.ff[0].q 1
-# assert t.registers.ff[1].q 1
-# assert t.registers.ff[2].q 1
-# assert t.registers.ff[3].q 1
-# assert t.registers.ff[4].q 1
-# assert t.registers.ff[5].q 1
-# assert t.registers.ff[6].q 1
-# assert t.registers.ff[7].q 1
-# assert t.in.v 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle 
-
-# system "echo '[9] Rewrite 11 to 01'"
-# system "echo '----------------------------------------------------------'"
-
-
-# set-qdi-channel-valid "t.in" 5 0
-# # 13 -> 00000 -> writing mode, address 00, word 00
-# cycle
-
-# assert t.in.a 1
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 1
-# set-qdi-channel-neutral "t.in" 5
-# cycle
-# assert t.registers._in_v_temp 0
-
-# assert t.registers.ff[0].q 0
-# assert t.registers.ff[1].q 0
-# assert t.registers.ff[2].q 1
-# assert t.registers.ff[3].q 1
-# assert t.registers.ff[4].q 1
-# assert t.registers.ff[5].q 1
-# assert t.registers.ff[6].q 1
-# assert t.registers.ff[7].q 1
-# assert t.in.v 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle 
-
-# system "echo '[9] Rewrite 11 to 01'"
-# system "echo '----------------------------------------------------------'"
-
-
-# set-qdi-channel-valid "t.in" 5 0
-# # 0 -> 00000 -> writing mode, address 00, word 00
-# cycle
-
-# assert t.in.a 1
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 1
-# set-qdi-channel-neutral "t.in" 5
-# cycle
-# assert t.registers._in_v_temp 0
-
-# assert t.registers.ff[0].q 0
-# assert t.registers.ff[1].q 0
-# assert t.registers.ff[2].q 1
-# assert t.registers.ff[3].q 1
-# assert t.registers.ff[4].q 1
-# assert t.registers.ff[5].q 1
-# assert t.registers.ff[6].q 1
-# assert t.registers.ff[7].q 0
-# assert t.in.v 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle 
-
-# system "echo '[9] Rewrite 11 to 01'"
-# system "echo '----------------------------------------------------------'"
-
-
-# set-qdi-channel-valid "t.in" 5 0
-# # 0 -> 00000 -> writing mode, address 00, word 00
-# cycle
-
-# assert t.in.a 1
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 1
-# set-qdi-channel-neutral "t.in" 5
-# cycle
-# assert t.registers._in_v_temp 0
-
-# assert t.registers.ff[0].q 0
-# assert t.registers.ff[1].q 0
-# assert t.registers.ff[2].q 1
-# assert t.registers.ff[3].q 1
-# assert t.registers.ff[4].q 1
-# assert t.registers.ff[5].q 1
-# assert t.registers.ff[6].q 1
-# assert t.registers.ff[7].q 0
-# assert t.in.v 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle 
-
-# system "echo '[9] Rewrite 11 to 01'"
-# system "echo '----------------------------------------------------------'"
-
-
-# set-qdi-channel-valid "t.in" 5 0
-# # 13 -> 00000 -> writing mode, address 00, word 00
-# cycle
-
-# assert t.in.a 1
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 1
-# set-qdi-channel-neutral "t.in" 5
-# cycle
-# assert t.registers._in_v_temp 0
-
-# assert t.registers.ff[0].q 0
-# assert t.registers.ff[1].q 0
-# assert t.registers.ff[2].q 1
-# assert t.registers.ff[3].q 1
-# assert t.registers.ff[4].q 1
-# assert t.registers.ff[5].q 1
-# assert t.registers.ff[6].q 1
-# assert t.registers.ff[7].q 0
-# assert t.in.v 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle 
-
-# system "echo '[9] Rewrite 11 to 01'"
-# system "echo '----------------------------------------------------------'"
-
-
-# set-qdi-channel-valid "t.in" 5 3
-# # 13 -> 00011 -> writing mode, address 00, word 11
-# cycle
-
-# assert t.in.a 1
-# assert-qdi-channel-neutral "t.out" 4
-# assert t.registers._in_v_temp 1
-# set-qdi-channel-neutral "t.in" 5
-# cycle
-# assert t.registers._in_v_temp 0
-
-# assert t.registers.ff[0].q 1
-# assert t.registers.ff[1].q 1
-# assert t.registers.ff[2].q 1
-# assert t.registers.ff[3].q 1
-# assert t.registers.ff[4].q 1
-# assert t.registers.ff[5].q 1
-# assert t.registers.ff[6].q 1
-# assert t.registers.ff[7].q 0
-# assert t.in.v 0
-
-# set t.out.a 0
-# set t.out.v 0
-# assert t.in.a 0
-# cycle 
-
-# system "echo '[9] Rewrite 11 to 01'"
-# system "echo '----------------------------------------------------------'"
-
-
-