added flip flop from XFAB

dataflow_neuro/cell_lib_async.act

@@ -536,6 +536,20 @@ namespace tmpl {
         prs{
         [keeper=0] ~a -> y+
         }
+        }
+
+        def A_2C2P_RB_X1(bool! y;bool? c1,c2,p1,p2,reset_B,vdd,vss){
+            bool _y;
+            prs{
+                (~p1 & ~p2 & ~c1 & ~c2)|~reset_B -> _y+
+                (c1 & c2 & reset_B) -> _y-
+                _y => y-
+            }
+            sizing {leak_adjust <- 1; 
+                p_n_mode <- 1;
+                y {-1}; _y{-1} }
+
+
         }
         }}
 

dataflow_neuro/cell_lib_std.act

@@ -373,49 +373,29 @@ namespace tmpl {
       }
       sizing { _en{-2}; y{-2,2} }
     }
-    export defproc DFFQ_R_X1 (bool? clk, reset, S, d, vdd, vss; bool! q)
+    export defproc DFFQ_R_X1 (bool? clk, reset_B, d; bool! q; bool? vdd,vss)
     {
-      bool _clk, __clk, _q_B, _dl;
+      bool _clk, __clk, _mqi,_mqib,_sqi,_sqib;
-      bool _Ro, _So;
-      bool _So2;
-      bool _qb;
-
       prs {
-        _q_B<10> -> q-
-       ~_q_B<20> -> q+
 
-        clk<10> -> _clk-
+        // Creating delayed versions of the clock
-       ~clk<20> -> _clk+
+        clk => _clk-
+        _clk => __clk-
 
-        _clk<10> -> __clk-
+        (~d & ~_clk)|(~reset_B)|(~__clk&~_mqi) -> _mqib+
-       ~_clk<20> -> __clk+
+        (d & __clk)|(reset_B & _mqi & _clk) -> _mqib-
 
-       reset<20>  -> _Ro-
+        _mqib => _mqi-
-      ~reset<20>  -> _Ro+
 
-       //  S<20> & _dl -> _So-
+        (~_mqi &~__clk)|(~reset_B)|(~_sqi&~_clk) -> _sqib+
-       // ~S<20> | ~_dl -> _So+
+        (_mqi &_clk)|(_sqi&__clk&reset_B) -> _sqib-
 
-       [keeper=0] d<10> & _clk -> _dl-
+        _sqib => _sqi-
-                ~d<20> & ~__clk<10> -> _dl+
+        _sqib => q-
 
-        reset<20> & _qb -> _q_B-
-       ~reset<20> | ~_qb -> _q_B+
 
-       //  _q_B<20> & S -> _So2-
-       // ~_q_B<20> | ~S -> _So2+
-
-       // input stage feedback
-       transgate<10> (__clk,_clk,_Ro,_dl)
-
-       // input to output
-       transgate<10> (__clk,_clk,reset,_qb)
-
-      // output feedback
-       transgate<10> (_clk,__clk,reset,_qb)
       }
-      sizing { q{-1} }
+    } 
-    }
   }
 }