bics/actlib_dataflow_neuro
20
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Compare commits

base: bics:9d864117d464bf905919c5c85f8b4a9252fc9c11
Branches Tags
bics:dev
bics:main
bics:encoder_wip
bics:TexelTapeout
..
compare: bics:4216f8808f7f189326a30ba997902e49b8002979
Branches Tags
bics:main
bics:dev
bics:encoder_wip
bics:TexelTapeout

2 Commits
9d864117d4 ... 4216f8808f

Author SHA1 Message Date
alexmadison
4216f8808f added sigbuf in chips 2022-04-12 16:41:30 +02:00
alexmadison
fdf05371f3 added sigbufs to register 2022-04-12 16:37:59 +02:00
2 changed files with 37 additions and 28 deletions
Show Stats Expand all files Collapse all files

39
dataflow_neuro/chips.act
View File

@ -70,69 +70,72 @@ defproc chip_texel (bd<N_IN> in, out;
power supply; power supply;
bool? reset_B){ bool? reset_B){
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
pint index = 0; // Just useful pint index = 0; // Just useful
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2, bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = reset_B, .supply = supply); .reset_B = _reset_BX, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = reset_B, .supply = supply); fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = reset_B, .supply = supply); fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
// Loopback // Loopback
fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = reset_B, .supply = supply); fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en, dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
.supply = supply); .supply = supply);
// Onwards // Onwards
fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = reset_B, .supply = supply); fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
demux_bit_msb<N_IN-1> _demux(.in = fifo_fork2dmx.out, .reset_B = reset_B, .supply = supply); demux_bit_msb<N_IN-1> _demux(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
// Register // Register
fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = reset_B, .supply = supply); fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data, register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
.supply = supply, .reset_B = reset_B); .supply = supply, .reset_B = _reset_BX);
fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = reset_B, .supply = supply); fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);
// Spike Decoder // Spike Decoder
pint NC_SYN; pint NC_SYN;
NC_SYN = NC_SYN_X + NC_SYN_Y; NC_SYN = NC_SYN_X + NC_SYN_Y;
slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply); slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = reset_B, .supply = supply); fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out, decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
.out = synapses, .out = synapses,
.hs_en = register.data[0].d[0].t, // Defaults to handshake disable .hs_en = register.data[0].d[0].t, // Defaults to handshake disable
.supply = supply, .reset_B = reset_B); .supply = supply, .reset_B = _reset_BX);
(i:N_SYN_DLY_CFG: decoder.dly_cfg[i] = register.data[0].d[1 + i].f;) // Defaults to max delay (i:N_SYN_DLY_CFG: decoder.dly_cfg[i] = register.data[0].d[1 + i].f;) // Defaults to max delay
// Neurons + encoder // Neurons + encoder
pint NC_NRN; pint NC_NRN;
NC_NRN = NC_NRN_X + NC_NRN_Y; NC_NRN = NC_NRN_X + NC_NRN_Y;
nrn_hs_2d_array<N_NRN_X,N_NRN_Y,N_LINE_PD_DLY> nrn_grid(.in = neurons, nrn_hs_2d_array<N_NRN_X,N_NRN_Y,N_LINE_PD_DLY> nrn_grid(.in = neurons,
.supply = supply, .reset_B = reset_B); .supply = supply, .reset_B = _reset_BX);
encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y> encoder( encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y> encoder(
.inx = nrn_grid.outx, .inx = nrn_grid.outx,
.iny = nrn_grid.outy, .iny = nrn_grid.outy,
.reset_B = reset_B, .supply = supply .reset_B = _reset_BX, .supply = supply
); );
fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out, fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
.reset_B = reset_B, .supply = supply); .reset_B = _reset_BX, .supply = supply);
// Merge // Merge
append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply); append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
append<N_IN-2, 2, 0> append_reg(.in = fifo_reg2mrg.out, .supply = supply); append<N_IN-2, 2, 0> append_reg(.in = fifo_reg2mrg.out, .supply = supply);
merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out, merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out,
.supply = supply, .reset_B = reset_B); .supply = supply, .reset_B = _reset_BX);
merge<N_IN> merge_loop8mrg(.in1 = merge_enc8reg.out, .in2 = _loopback_dropper.out, merge<N_IN> merge_loop8mrg(.in1 = merge_enc8reg.out, .in2 = _loopback_dropper.out,
.reset_B = reset_B, .supply = supply); .reset_B = _reset_BX, .supply = supply);
// qdi2bd // qdi2bd
fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_loop8mrg.out, fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_loop8mrg.out,
.reset_B = reset_B, .supply = supply); .reset_B = _reset_BX, .supply = supply);
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg, qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
.reset_B = reset_B, .supply = supply); .reset_B = _reset_BX, .supply = supply);

26
dataflow_neuro/registers.act
View File

@ -151,13 +151,14 @@ A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2,
// Pass to let data into the buffer // Pass to let data into the buffer
NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd); NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> passX(.in = pass.y, .supply = supply);
AND2_X1 gandalf_t[N]; AND2_X1 gandalf_t[N];
AND2_X1 gandalf_f[N]; AND2_X1 gandalf_f[N];
(i:0..N-1: (i:0..N-1:
gandalf_t[i].a = in.d.d[i].t; gandalf_t[i].a = in.d.d[i].t;
gandalf_f[i].a = in.d.d[i].f; gandalf_f[i].a = in.d.d[i].f;
gandalf_t[i].b = pass.y; gandalf_t[i].b = passX.out[i];
gandalf_f[i].b = pass.y; gandalf_f[i].b = passX.out[i+N];
gandalf_t[i].y = buf.in.d.d[i].t; gandalf_t[i].y = buf.in.d.d[i].t;
gandalf_f[i].y = buf.in.d.d[i].f; gandalf_f[i].y = buf.in.d.d[i].f;
@ -261,8 +262,6 @@ export template<pint NcA, NcW, M>
defproc register_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out; defproc register_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
bool? reset_B; power supply) { bool? reset_B; power supply) {
// BIG TODO
// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
// Input valid tree // Input valid tree
vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v, vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
@ -292,9 +291,11 @@ A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
// Write bit selector // Write bit selector
bool _w = in.d.d[NcA+NcW].t; bool _w = in.d.d[NcA+NcW].t;
bool _wX[M];
sigbuf<M> _w_sb(.in = _w, .out = _wX, .supply = supply);
A_2C_B_X1 write_selectors[M]; A_2C_B_X1 write_selectors[M];
(i:M: (i:M:
write_selectors[i].c1 = _w; write_selectors[i].c1 = _wX[i];
write_selectors[i].c2 = decoder.out[i]; write_selectors[i].c2 = decoder.out[i];
write_selectors[i].vdd = supply.vdd; write_selectors[i].vdd = supply.vdd;
write_selectors[i].vss = supply.vss; write_selectors[i].vss = supply.vss;
@ -328,12 +329,17 @@ TIELO_X1 tielow_writebit_f[M];
// Read bit selector // Read bit selector
bool _r = in.d.d[NcA+NcW].f; bool _r = in.d.d[NcA+NcW].f;
bool _rX[M+NcA];
sigbuf<M+NcA> _r_sb(.in = _r, .out = _rX, .supply = supply);
A_2C_B_X1 read_selectors[M]; A_2C_B_X1 read_selectors[M];
sigbuf_boolarray<M, NcW*2> read_selectorsX(.supply = supply);
(i:M: (i:M:
read_selectors[i].c1 = _r; read_selectors[i].c1 = _rX[i];
read_selectors[i].c2 = decoder.out[i]; read_selectors[i].c2 = decoder.out[i];
read_selectors[i].vdd = supply.vdd; read_selectors[i].vdd = supply.vdd;
read_selectors[i].vss = supply.vss; read_selectors[i].vss = supply.vss;
read_selectorsX.in[i] = read_selectors[i].y;
) )
// OrTrees for each output word bit on read // OrTrees for each output word bit on read
@ -357,9 +363,9 @@ pint index;
index = i + j*NcW; index = i + j*NcW;
and_reads_t[index].a = data[j].d[i].t; and_reads_t[index].a = data[j].d[i].t;
and_reads_t[index].b = read_selectors[j].y; and_reads_t[index].b = read_selectorsX.out[j];
and_reads_f[index].a = data[j].d[i].f; and_reads_f[index].a = data[j].d[i].f;
and_reads_f[index].b = read_selectors[j].y; and_reads_f[index].b = read_selectorsX.out[j];
and_reads_t[index].y = out_ortrees_t[i].in[j]; and_reads_t[index].y = out_ortrees_t[i].in[j];
and_reads_f[index].y = out_ortrees_f[i].in[j]; and_reads_f[index].y = out_ortrees_f[i].in[j];
@ -379,8 +385,8 @@ A_2C_B_X1 addr_read_f[NcA];
addr_read_t[i].c1 = in.d.d[i].t; addr_read_t[i].c1 = in.d.d[i].t;
addr_read_f[i].c1 = in.d.d[i].f; addr_read_f[i].c1 = in.d.d[i].f;
addr_read_t[i].c2 = _r; addr_read_t[i].c2 = _rX[M+i];
addr_read_f[i].c2 = _r; addr_read_f[i].c2 = _rX[M+i];
addr_read_t[i].y = out.d.d[i].t; addr_read_t[i].y = out.d.d[i].t;
addr_read_f[i].y = out.d.d[i].f; addr_read_f[i].y = out.d.d[i].f;