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Author SHA1 Message Date
alexmadison 76e0e22356 removed unused cells 2023-12-01 13:21:46 +01:00
alexmadison 51327289a7 removed sadc handshake because why would anyone instantiate sadc hs when we have a lovely neuron handshake 2023-12-01 12:13:06 +01:00
alexmadison b2de1a45d7 removed std and acell instantiate tests in wrong folder, and they are old, acells do not have x1 etc 2023-12-01 12:09:44 +01:00
6 changed files with 3 additions and 401 deletions
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60
dataflow_neuro/cell_lib_async_test.act
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@ -1,60 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_async.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "cell_lib_async.act";
open tmpl::dataflow_neuro;
A_1C1P2N_RB_X1 cell1;
A_1C1P2N_R_X1 cell2;
A_1C1P_1N_X1 cell3;
A_1C1P_B cell4;
A_1C1P cell5;
A_1C2P1N_X1 cell6;
A_1C2P_B_X1 cell7;
A_1C2P cell8;
A_1C3P2P2N_R_X1 cell9;
A_2C2N2N_RB_X1 cell10;
A_2C2N2N_RB_X2 cell11;
A_2C2N2N_RB_X4 cell12;
A_2C2N2N_R_X1 cell13;
A_2C2N_R_B_X2 cell14;
A_2C2N_R_B_X4 cell15;
A_2C2N_R_X1 cell16;
A_2C_B_X1 cell17;
A_2C_RB_X1 cell18;
A_2C_R_X1 cell19;
A_2C_X1 cell20;
A_3C_RB_X1 cell21;
A_3C_RB_X2 cell22;
A_3C_RB_X4 cell23;
A_3C_R_X1 cell24;
A_3C_X1 cell25;
A_4C_RB_X1 cell26;
A_4C_RB_X2 cell27;
A_4C_RB_X4 cell28;
A_4C_R_X1 cell29;
A_4P1N1N_B_X1 cell30;
A_4P1N1N_X1 cell31;

58
dataflow_neuro/cell_lib_std_test.act
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@ -1,58 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Alex Madison
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "cell_lib_std.act";
open std_cell_template::dataflow_neuro;
TIELO_X1 cell1;
TIEHI_X1 cell2;
INV_X1 cell4;
INV_X2 cell5;
INV_X4 cell6;
INV_X8 cell7;
CLKBUF1 cell8;
CLKBUF2 cell9;
CLKBUF3 cell10;
NOR2_X1 cell11;
NOR3_X1 cell12;
OR2_X1 cell13;
OR2_X2 cell14;
NAND2_X1 cell15;
NAND3_X1 cell16;
AND2_X1 cell17;
AND2_X2 cell18;
XOR2_X1 cell19;
XNOR2_X1 cell20;
MUX2_X1 cell25;
OAI21_X1 cell26;
AOI21_X1 cell27;
OAI22_X1 cell28;
AOI22_X1 cell29;
TBUF1_X1 cell30;
TBUF_X2 cell31;

81
dataflow_neuro/coders.act
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@ -147,23 +147,6 @@ defproc decoder_dualrail_refresh (Mx1of2<Nc> in; bool? out[N]; Mx1of2<Nc> final_
)
}
/**
* Dualrail decoder with buffered outputs.
* Be careful of out[] indexing.
*/
export template<pint Nc, N, OUT_STRENGTH>
defproc decoder_dualrail_x(Mx1of2<Nc> in; bool? out[N]; power supply) {
decoder_dualrail<Nc, N> decoder(.in = in, .supply = supply);
sigbuf<OUT_STRENGTH> sb[N];
(i:N:
sb[i].in = decoder.out[i];
sb[i].supply = supply;
sb[i].out[0] = out[i];
// (j:OUT_STRENGTH:
// sb[i].out[j] = out[j + i*OUT_STRENGTH];
// )
)
}
/**
* Dualrail decoder with on/off switch.
@ -210,6 +193,9 @@ defproc decoder_dualrail_en(Mx1of2<Nc> in; bool? en, out[N]; power supply) {
/**
* @TODO check that this is definitely exactly the same as hybrid, maybe keep
*
*
* 2D decoder which uses a configurable delay from the VCtrees to buffer ack.
* Nx is the x size of the decoder array
* NxC is the number of wires in the x channel.
@ -700,67 +686,6 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[
/**
* Buffer function code.
* Is the function block ripped from the buffer_s.
* Used in the encoder2d.
*/
export template<pint N>
defproc buffer_s_func (Mx1of2<N> in; avMx1of2<N> out; bool? in_v, en, reset_B; power supply) {
//function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N], _in_vX;
// bool _in_vXX_t[N],_in_vXX_f[N];
A_2C2N_RB_X4 f_buf_func[N];
A_2C2N_RB_X4 t_buf_func[N];
// reset buffers
bool _reset_BX,_reset_BXX[N*2];
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
// Enable signal buffers
sigbuf<N> en_buf_t(.in=en, .out=_en_X_t, .supply=supply);
sigbuf<N> en_buf_f(.in=en, .out=_en_X_f, .supply=supply);
// out ack signal buffers
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t, .supply=supply);
sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f, .supply=supply);
// in val signal buffers
BUF_X4 in_v_prebuf(.a = in_v, .y = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
// sigbuf<N> in_v_buf_t(.in=_in_vX, .out=_in_vXX_t, .supply=supply);
// sigbuf<N> in_v_buf_f(.in=_in_vX, .out=_in_vXX_f, .supply=supply);
sigbuf<N*2> in_v_buf(.in=_in_vX,.supply=supply);
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=_en_X_f[i];
t_buf_func[i].c1=_en_X_t[i];
f_buf_func[i].c2=_out_a_BX_f[i];
t_buf_func[i].c2=_out_a_BX_t[i];
f_buf_func[i].n1=in.d[i].f;
t_buf_func[i].n1=in.d[i].t;
f_buf_func[i].n2=in_v_buf.out[i];
t_buf_func[i].n2=in_v_buf.out[i+N];
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i+N];
f_buf_func[i].sr_B = _reset_BXX[i+N];
)
}
export
defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
{

66
dataflow_neuro/dynapse.act
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@ -1,66 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/interfaces.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
export
defproc sadc_hs (a1of1 in, out; bool? reset_B; power supply) {
bool _en;
bool _out_a_B;
INV_X1 ack_inv(.a = out.a, .y = _out_a_B, .vdd = supply.vdd, .vss = supply.vss);
A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = out.r, .y = in.a,
.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
A_2C1N_RB_X1 A_req(.c1 = _en, .c2 = _out_a_B, .n1 = in.r, .y = out.r,
.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
A_1C1P_X1 A_en(.c1 = in.a, .p1 = out.r, .y = _en,
.vdd = supply.vdd, .vss = supply.vss);
}
}
}

67
test/unit_tests/sadc_hs/test.act
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@ -1,67 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/dynapse.act";
import "../../dataflow_neuro/primitives.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc _sadc_hs (a1of1 in[4], out; bool? reset_B) {
power supply;
supply.vdd = Vdd;
supply.vss = GND;
// pipe loads of inputs into the sadc handshake
// to simulate a neuron going nuts
fifo_t<3> in_fifos[4];
arbtree<4> in_arbtree(.supply = supply);
(i:4:
in_fifos[i].in = in[i];
in_fifos[i].reset_B = reset_B;
in_fifos[i].out = in_arbtree.in[i];
in_fifos[i].supply = supply;
)
sadc_hs c(.in = in_arbtree.out,
.reset_B = reset_B, .supply = supply);
fifo_t<8> out_fifo(.in = c.out, .out = out,
.supply = supply, .reset_B = reset_B);
}
// fifo_decoder_neurons_encoder_fifo e;
_sadc_hs c;

72
test/unit_tests/sadc_hs/test.prsim
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@ -1,72 +0,0 @@
watchall
set c.reset_B 0
set c.in[0].r 0
set c.in[1].r 0
set c.in[2].r 0
set c.in[3].r 0
set c.out.a 0
cycle
status X
system "echo '[] Set reset 0'"
mode run
set c.reset_B 1
cycle
system "echo '[] Reset finished'"
status X
system "echo '[] Setting all in reqs high'"
set c.in[0].r 1
set c.in[1].r 1
set c.in[2].r 1
set c.in[3].r 1
cycle
assert c.in[0].a 1
assert c.in[1].a 1
assert c.in[2].a 1
assert c.in[3].a 1
set c.in[0].r 0
set c.in[1].r 0
set c.in[2].r 0
set c.in[3].r 0
cycle
assert c.in[0].a 0
assert c.in[1].a 0
assert c.in[2].a 0
assert c.in[3].a 0
assert c.out.r 1
set c.out.a 1
cycle
assert c.out.r 0
set c.out.a 0
cycle
assert c.out.r 1
set c.out.a 1
cycle
assert c.out.r 0
set c.out.a 0
cycle
assert c.out.r 1
set c.out.a 1
cycle
assert c.out.r 0
set c.out.a 0
cycle
assert c.out.r 1
set c.out.a 1
cycle
assert c.out.r 0
set c.out.a 0
cycle