continued registers.c

dataflow_neuro/registers.act

@@ -51,64 +51,62 @@ namespace tmpl {
 //        - the last wl the word to write
 // data -> the data saved in the flip flop, sized wl x nw
 export template<pint log_nw,wl,N_dly_cfg>
-defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool reset_B,reset_mem_B){
+defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
     bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
+    pint _nw = 2<<log_nw;
     //Validation of the input 
-    Mx1of2<1+log_nw+wl> in_temp;
+    Mx1of2<1+log_nw+wl> _in_temp;
-    (i:1+log_nw+wl:in_temp.d[i] = in.d.d[i];)
+    (i:1+log_nw+wl:_in_temp.d[i] = in.d.d[i];)
-    vtree<1+log_nw+wl> val_input(.in = in_temp,.out = _in_v_temp, .supply = supply);
+    vtree<1+log_nw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
     sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
-    in.v = _in_v_temp;
+    // Generation of the fake clock pulse
-    // Generation of the clock pulse
+    delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
-    delayprog<N_dly_cfg> dly(.in = _in_v_temp, .s = _clock_temp, .supply = supply);
+    sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
-    sigbuf_1output<4> val_input_X(.in = _clock_temp,.out = _clock,.supply = supply);
     // Sending back to the ackowledge
-    delayprog<N_dly_cfg> dly(.in = _clock, .s = _in_a_temp, .supply = supply);
+    delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
-    sigbuf_1output<4> val_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
+    sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
     //Reset Buffers
-    bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[_nw*w];
+    bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[_nw*wl];
-    BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
+    BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
-    BUF_X1 reset_buf(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
+    BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
-    sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_BXX_mem,.vdd=supply.vdd,.vss=supply.vss);
+    sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
     // Creating the different flip flop arrays
-    bool _nw = 2<<log_nw;
+    bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw],_clock_buffer_out[_nw*wl];
-    bool _word_idx = 0;
-    bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw];
     andtree<log_nw> atree[_nw];
     AND2_X1 and_encoder[_nw];
-    sigbuf<wl> clock_buffer;
+    sigbuf<wl> clock_buffer[_nw];
     DFFQ_R_X1 ff[_nw*wl];
-    (k:_nw:atree_x[k].supply = supply;)
+    pint _bitval;
+    (k:_nw:atree[k].supply = supply;)
     (_word_idx:_nw:
         // Decoding the bit pattern to understand which word we are looking at
         (pin_idx:log_nw:
-            bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
+            _bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
-            [bitval = 1 -> 
+            [_bitval = 1 -> 
-                atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].t;
+                atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
-            [] bitval = 0 ->
+            [] _bitval = 0 ->
-                atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].f;
+                atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
-            []bitval >= 2 -> {false : "fuck"};
+            []_bitval >= 2 -> {false : "fuck"};
             ]
         )
         // Activating the fake clock for the right word
-        atree_x[_word_idx].out = _out_encoder[_word_idx];    
+        atree[_word_idx].out = _out_encoder[_word_idx];    
         and_encoder[_word_idx].a = _out_encoder[_word_idx];
         and_encoder[_word_idx].b = _clock;
         and_encoder[_word_idx].y = _clock_word_temp[_word_idx];
         and_encoder[_word_idx].vdd = supply.vdd;
         and_encoder[_word_idx].vss = supply.vss;
         clock_buffer[_word_idx].in = _clock_word_temp[_word_idx];
-        clock_buffer[_word_idx].out = _clock_word[_word_idx];
+        clock_buffer[_word_idx].supply = supply;
-        clock_buffer[_word_idx].vdd = supply.vdd;
-        clock_buffer[_word_idx].vss = supply.vss;
         // Describing all the FF and their connection
         (_bit_idx:wl:
-            ff[_bit_idx*(1+_word_idx)].clk = _clock_word[_word_idx];
+            clock_buffer[_word_idx].out[_bit_idx] = _clock_buffer_out[_bit_idx*(1+_word_idx)];
-            ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw];
+            // ff[_bit_idx*(1+_word_idx)].clk = _clock_buffer_out[_bit_idx*(1+_word_idx)];
-            ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
+            // ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw].t;
-            ff[_bit_idx*(1+_word_idx)].reset_B = reset_mem_BXX[_bit_idx*(1+_word_idx)];
+            // ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
-            ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
+            // ff[_bit_idx*(1+_word_idx)].reset_B = _reset_mem_BXX[_bit_idx*(1+_word_idx)];
-            ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
+            // ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
+            // ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
         )
     )
 }

test/unit_tests/register_write/run/prsim.out

@@ -0,0 +1,298 @@
+t.registers.ff[4].q t.registers._clock_word_temp[0] t.registers.ff[15].reset_B t.in.d.d[1].f t.registers._clock_temp t.registers.ack_dly._a[1] t.dly_cfg[1] t.registers.ff[5].reset_B t.registers.ff[8].d t.registers._clock t.registers.clk_dly.and2[0]._y t.in.d.d[0].t t.registers.ff[2].reset_B t.registers.ff[7].clk t.registers.ff[12]._sqib t.registers.ack_dly.dly[1].__y t.registers._clock_buffer_out[0] t.registers.val_input.ct.in[1] t.registers.ff[1].clk t.registers.ff[5]._mqi t.registers.ff[8]._clk t.registers.ff[7]._mqib t.registers.ff[15].q t.in.d.d[4].f t.registers._clock_word_temp[2] t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.registers.ff[4].reset_B t.registers.ff[13]._clk t.registers._out_encoder[3] t.registers.clock_buffer[1].buf1._y t.registers.ff[11]._mqi t.registers.ff[13]._mqib t.registers.atree[2].in[1] t.dly_cfg[0] t.registers.ff[4].__clk t.registers._in_v_temp t.registers.atree[1].in[0] t.registers._out_encoder[2] t.registers.ff[6].clk t.registers.ff[14]._mqi t.registers._out_encoder[1] t.registers.clk_dly.and2[1]._y t.registers.val_input.ct.in[0] t.registers.atree[0].in[0] t.registers.ack_dly.dly[2]._y t.registers._in_a_temp t.registers.ff[3].__clk t.in.d.d[0].f t.registers.clk_dly.dly[1].y t.registers.ff[1].__clk t.in.v t.registers._clock_word_temp[5] t.registers.clk_dly.dly[2].y t.registers.ff[0].q t.in.d.d[4].t t.registers.ff[0].clk t.registers.ff[14]._clk t.registers.clk_dly.dly[1].a t.registers.ff[10]._mqib t.registers._clock_word_temp[3] t.registers._out_encoder[7] t.registers.ff[6].__clk t.registers.ff[0]._sqib t.registers.ff[9]._clk t.registers.ff[15]._mqib t.registers.ack_dly.dly[0].___y t.registers.ff[11].__clk t.registers._out_encoder[4] t.registers.val_input.ct.in[3] t.registers.ff[7]._mqi t.registers._out_encoder[5] t.registers.ff[5].q t.in.d.d[1].t t.registers.ff[1]._sqi t.registers.ff[1]._sqib t.registers.ff[7]._clk t.registers._clock_word_temp[4] t.registers.clock_buffer[0].buf1._y t.registers._out_encoder[0] t.registers.ack_dly.dly[2].___y t.registers._clock_word_temp[7] t.registers.ff[10].reset_B t.registers.ff[3]._clk t.registers.ff[13]._sqi t.registers.ff[2]._mqi t.registers._clock_word_temp[6] t.registers.ack_dly.mu2[0]._y t.registers.atree[1].and2s[0]._y t.registers.atree[0].in[1] t.registers.clk_dly._a[1] t.registers.val_input.ct.in[4] t.registers.ff[11]._sqi t.registers.ff[3].reset_B t.registers.ff[6]._mqi t.registers.ff[10].clk t.registers.val_input.OR2_tf[3]._y t.registers.ff[5].__clk t.registers.clk_X.buf1._y t.registers.ff[11]._clk t.registers.ff[0].d t.registers.ff[14]._sqi t.registers.ff[7]._sqib t.registers.clk_dly.dly[0].___y t.registers.ff[8].q t.registers._clock_word_temp[1] t.registers.and_encoder[2]._y t.registers.clk_dly.dly[1].___y t.registers.ff[5]._sqib t.registers._out_encoder[6] t.registers.ff[6].reset_B t.registers.clock_buffer[4].buf1._y t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[5].d t.registers.ff[9]._mqib t.registers.clk_dly.dly[0]._y t.registers.ff[4]._mqib t.registers.ff[8]._sqi t.registers.val_input.OR2_tf[2]._y t.registers.val_input.ct.in[2] t.registers.ff[14].q t.registers.val_input.ct.tmp[6] t.registers.clk_dly.dly[1]._y t.registers.ff[13].q t.registers.ff[1].d t.registers.ff[2]._clk t.registers.ff[10].__clk t.registers.ff[3]._mqib t.registers.ack_dly.dly[2].y t.registers.atree[6].and2s[0]._y t.registers.atree[0].and2s[0]._y t.registers.ff[2]._sqi t.registers.ff[3].clk t.registers.ff[3].d t.registers.ff[1]._mqi t.registers.ff[12].clk t.registers.clk_dly.mu2[1]._y t.registers.ff[9]._mqi t.registers.ff[8]._mqib t.registers.clk_dly.mu2[0]._s t.registers.ff[10].q t.registers.ack_dly.dly[0]._y t.registers.clk_dly.dly[0].a t.registers.ff[2].q t.registers.ff[4]._sqib t.registers.ack_dly.dly[0].a t.registers.ff[11].reset_B t.registers.clock_buffer[2].buf1._y t.registers.ff[10]._sqi t.registers.ff[15]._clk t.registers.ff[13]._sqib t.registers.ff[9].clk t.registers.ff[14].reset_B t.registers.ff[7].d t.registers.ff[4].d t.registers.ff[7]._sqi t.registers.clk_dly.dly[1].__y t.registers.ff[15].clk t.registers.ff[6]._mqib t.registers.clk_dly.dly[0].y t.registers.ff[2].__clk t.registers.ff[2]._sqib t.registers.clk_dly.mu2[0]._y t.registers.ff[9].reset_B t.registers.ff[10].d t.registers.ff[1].q t.registers.ff[3]._sqi t.registers.ff[5]._mqib t.registers.ff[6].d t.registers.ff[13].clk t.registers.ff[6]._clk t.registers.ff[5]._sqi t.registers.ff[12]._sqi t.registers.ff[9]._sqi t.registers.atree[7].and2s[0]._y t.registers.ff[4]._clk t.registers.clock_buffer[3].buf1._y t.registers.val_input.ct.tmp[5] t.registers.ff[12]._mqi t.registers.atree[4].and2s[0]._y t.registers.ack_dly.dly[1]._y t.registers.ff[9].__clk t.registers.ff[14].d t.registers.and_encoder[0]._y t.registers.ff[13]._mqi t.registers.and_encoder[6]._y t.registers.val_input.ct.C2Els[1]._y t.registers.ff[8].reset_B t.registers.and_encoder[5]._y t.registers.ack_dly.dly[1].y t.registers.ff[0]._clk t.registers.ff[3]._sqib t.registers.ack_dly.and2[1]._y t.registers.ff[13].d t.reLine truncated
+[0] start test
+	     16472 t.in.d.d[0].f : 0
+	     16472 t.data[1].d[1] : 0
+	     16472 t.data[1].d[0] : 0
+	     16472 t.data[0].d[1] : 0
+	     16472 t.data[0].d[0] : 0
+	     16472 t.in.d.d[4].t : 0
+	     16472 t.in.d.d[4].f : 0
+	     16472 t.registers.atree[2].in[1] : 0
+	     16472 t.in.d.d[1].f : 0
+	     16472 t.registers.atree[0].in[1] : 0
+	     16472 t.registers.atree[1].in[0] : 0
+	     16472 t.in.d.d[0].t : 0
+	     16472 t.registers.atree[0].in[0] : 0
+	     16472 t.in.d.d[1].t : 0
+	     16485 t.registers.val_input.OR2_tf[3]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	     16487 t.registers.atree[6].and2s[0]._y : 1  [by t.registers.atree[2].in[1]:=0]
+	     16488 t.registers.val_input.OR2_tf[2]._y : 1  [by t.registers.atree[0].in[0]:=0]
+	     16491 t.registers._out_encoder[6] : 0  [by t.registers.atree[6].and2s[0]._y:=1]
+	     16492 t.registers.atree[4].and2s[0]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	     16506 t.registers.and_encoder[6]._y : 1  [by t.registers._out_encoder[6]:=0]
+	     16511 t.registers.atree[3].and2s[0]._y : 1  [by t.registers.atree[2].in[1]:=0]
+	     16512 t.registers.atree[0].and2s[0]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	     16519 t.registers.val_input.OR2_tf[0]._y : 1  [by t.in.d.d[0].t:=0]
+	     16566 t.registers._out_encoder[3] : 0  [by t.registers.atree[3].and2s[0]._y:=1]
+	     16887 t.registers.atree[1].and2s[0]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	     16963 t.registers.atree[7].and2s[0]._y : 1  [by t.registers.atree[2].in[1]:=0]
+	     18198 t.registers.atree[2].and2s[0]._y : 1  [by t.registers.atree[2].in[1]:=0]
+	     18620 t.registers._out_encoder[2] : 0  [by t.registers.atree[2].and2s[0]._y:=1]
+	     22533 t.registers.atree[5].and2s[0]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	     22534 t.registers._out_encoder[5] : 0  [by t.registers.atree[5].and2s[0]._y:=1]
+	     22535 t.registers.and_encoder[5]._y : 1  [by t.registers._out_encoder[5]:=0]
+	     25617 t.registers.val_input.ct.in[2] : 0  [by t.registers.val_input.OR2_tf[2]._y:=1]
+	     30209 t.registers.val_input.ct.in[3] : 0  [by t.registers.val_input.OR2_tf[3]._y:=1]
+	     30415 t.registers.and_encoder[3]._y : 1  [by t.registers._out_encoder[3]:=0]
+	     30697 t.registers._clock_word_temp[3] : 0  [by t.registers.and_encoder[3]._y:=1]
+	     31306 t.registers._out_encoder[7] : 0  [by t.registers.atree[7].and2s[0]._y:=1]
+	     31309 t.registers.and_encoder[7]._y : 1  [by t.registers._out_encoder[7]:=0]
+	     31465 t.registers.clock_buffer[3].buf1._y : 1  [by t.registers._clock_word_temp[3]:=0]
+	     41699 t.registers._out_encoder[1] : 0  [by t.registers.atree[1].and2s[0]._y:=1]
+	     42250 t.registers.and_encoder[1]._y : 1  [by t.registers._out_encoder[1]:=0]
+	     42740 t.registers._clock_word_temp[5] : 0  [by t.registers.and_encoder[5]._y:=1]
+	     43321 t.registers._clock_word_temp[1] : 0  [by t.registers.and_encoder[1]._y:=1]
+	     43694 t.registers.clock_buffer[5].buf1._y : 1  [by t.registers._clock_word_temp[5]:=0]
+	     44402 t.registers.clock_buffer[1].buf1._y : 1  [by t.registers._clock_word_temp[1]:=0]
+	     46299 t.registers.val_input.ct.in[0] : 0  [by t.registers.val_input.OR2_tf[0]._y:=1]
+	     53437 t.registers._clock_word_temp[6] : 0  [by t.registers.and_encoder[6]._y:=1]
+	     53750 t.registers._clock_word_temp[7] : 0  [by t.registers.and_encoder[7]._y:=1]
+	     54732 t.registers.clock_buffer[7].buf1._y : 1  [by t.registers._clock_word_temp[7]:=0]
+	     59740 t.registers._out_encoder[4] : 0  [by t.registers.atree[4].and2s[0]._y:=1]
+	     59758 t.registers.and_encoder[4]._y : 1  [by t.registers._out_encoder[4]:=0]
+	     60570 t.registers.val_input.OR2_tf[1]._y : 1  [by t.in.d.d[1].t:=0]
+	     63771 t.registers._clock_word_temp[4] : 0  [by t.registers.and_encoder[4]._y:=1]
+	     64573 t.registers.val_input.ct.in[1] : 0  [by t.registers.val_input.OR2_tf[1]._y:=1]
+	     67334 t.registers.and_encoder[2]._y : 1  [by t.registers._out_encoder[2]:=0]
+	     68165 t.registers._out_encoder[0] : 0  [by t.registers.atree[0].and2s[0]._y:=1]
+	     68667 t.registers.and_encoder[0]._y : 1  [by t.registers._out_encoder[0]:=0]
+	     68870 t.registers._clock_word_temp[0] : 0  [by t.registers.and_encoder[0]._y:=1]
+	     70724 t.registers.clock_buffer[0].buf1._y : 1  [by t.registers._clock_word_temp[0]:=0]
+	     72094 t.registers._clock_word_temp[2] : 0  [by t.registers.and_encoder[2]._y:=1]
+	     72233 t.registers.clock_buffer[2].buf1._y : 1  [by t.registers._clock_word_temp[2]:=0]
+	     81838 t.registers.val_input.OR2_tf[4]._y : 1  [by t.in.d.d[4].f:=0]
+	     86157 t.registers.val_input.ct.C2Els[0]._y : 1  [by t.registers.val_input.ct.in[1]:=0]
+	     86226 t.registers.val_input.ct.tmp[5] : 0  [by t.registers.val_input.ct.C2Els[0]._y:=1]
+	    107907 t.registers.clock_buffer[6].buf1._y : 1  [by t.registers._clock_word_temp[6]:=0]
+	    108672 t.registers.clock_buffer[4].buf1._y : 1  [by t.registers._clock_word_temp[4]:=0]
+	    108683 t.registers._clock_buffer_out[0] : 0  [by t.registers.clock_buffer[4].buf1._y:=1]
+	    118184 t.registers.val_input.ct.in[4] : 0  [by t.registers.val_input.OR2_tf[4]._y:=1]
+	    169970 t.registers.val_input.ct.C3Els[0]._y : 1  [by t.registers.val_input.ct.in[4]:=0]
+	    170174 t.registers.val_input.ct.tmp[6] : 0  [by t.registers.val_input.ct.C3Els[0]._y:=1]
+	    170189 t.registers.val_input.ct.C2Els[1]._y : 1  [by t.registers.val_input.ct.tmp[6]:=0]
+	    170190 t.registers._in_v_temp : 0  [by t.registers.val_input.ct.C2Els[1]._y:=1]
+	    170227 t.registers.clk_dly.and2[0]._y : 1  [by t.registers._in_v_temp:=0]
+	    170339 t.registers.clk_dly.dly[0].a : 0  [by t.registers.clk_dly.and2[0]._y:=1]
+	    170929 t.registers.val_input_X.buf1._y : 1  [by t.registers._in_v_temp:=0]
+	    170969 t.in.v : 0  [by t.registers.val_input_X.buf1._y:=1]
+	    217851 t.registers.clk_dly.dly[0]._y : 1  [by t.registers.clk_dly.dly[0].a:=0]
+	    218108 t.registers.clk_dly.dly[0].__y : 0  [by t.registers.clk_dly.dly[0]._y:=1]
+	    218195 t.registers.clk_dly.dly[0].___y : 1  [by t.registers.clk_dly.dly[0].__y:=0]
+	    218489 t.registers.clk_dly.dly[0].y : 0  [by t.registers.clk_dly.dly[0].___y:=1]
+t.registers.ff[4].q t.registers.ff[15].reset_B t.registers._clock_temp t.registers.ack_dly._a[1] t.dly_cfg[1] t.registers.ff[5].reset_B t.registers.ff[8].d t.registers._clock t.registers.ff[2].reset_B t.registers.ff[7].clk t.registers.ff[12]._sqib t.registers.ack_dly.dly[1].__y t.registers.ff[1].clk t.registers.ff[5]._mqi t.registers.ff[8]._clk t.registers.ff[7]._mqib t.registers.ff[15].q t.registers.clk_dly.dly[2]._y t.registers.ack_dly.dly[1].___y t.registers.ff[4].reset_B t.registers.ff[13]._clk t.registers.ff[11]._mqi t.registers.ff[13]._mqib t.dly_cfg[0] t.registers.ff[4].__clk t.registers.ff[6].clk t.registers.ff[14]._mqi t.registers.clk_dly.and2[1]._y t.registers.ack_dly.dly[2]._y t.registers._in_a_temp t.registers.ff[3].__clk t.registers.clk_dly.dly[1].y t.registers.ff[1].__clk t.registers.clk_dly.dly[2].y t.registers.ff[0].q t.registers.ff[0].clk t.registers.ff[14]._clk t.registers.clk_dly.dly[1].a t.registers.ff[10]._mqib t.registers.ff[6].__clk t.registers.ff[0]._sqib t.registers.ff[9]._clk t.registers.ff[15]._mqib t.registers.ack_dly.dly[0].___y t.registers.ff[11].__clk t.registers.ff[7]._mqi t.registers.ff[5].q t.registers.ff[1]._sqi t.registers.ff[1]._sqib t.registers.ff[7]._clk t.registers.ack_dly.dly[2].___y t.registers.ff[10].reset_B t.registers.ff[3]._clk t.registers.ff[13]._sqi t.registers.ff[2]._mqi t.registers.ack_dly.mu2[0]._y t.registers.clk_dly._a[1] t.registers.ff[11]._sqi t.registers.ff[3].reset_B t.registers.ff[6]._mqi t.registers.ff[10].clk t.registers.ff[5].__clk t.registers.clk_X.buf1._y t.registers.ff[11]._clk t.registers.ff[0].d t.registers.ff[14]._sqi t.registers.ff[7]._sqib t.registers.ff[8].q t.registers.clk_dly.dly[1].___y t.registers.ff[5]._sqib t.registers.ff[6].reset_B t.in.a t.registers.clk_dly.mu2[1]._s t.registers.ff[5].d t.registers.ff[9]._mqib t.registers.ff[4]._mqib t.registers.ff[8]._sqi t.registers.ff[14].q t.registers.clk_dly.dly[1]._y t.registers.ff[13].q t.registers.ff[1].d t.registers.ff[2]._clk t.registers.ff[10].__clk t.registers.ff[3]._mqib t.registers.ack_dly.dly[2].y t.registers.ff[2]._sqi t.registers.ff[3].clk t.registers.ff[3].d t.registers.ff[1]._mqi t.registers.ff[12].clk t.registers.clk_dly.mu2[1]._y t.registers.ff[9]._mqi t.registers.ff[8]._mqib t.registers.clk_dly.mu2[0]._s t.registers.ff[10].q t.registers.ack_dly.dly[0]._y t.registers.ff[2].q t.registers.ff[4]._sqib t.registers.ack_dly.dly[0].a t.registers.ff[11].reset_B t.registers.ff[10]._sqi t.registers.ff[15]._clk t.registers.ff[13]._sqib t.registers.ff[9].clk t.registers.ff[14].reset_B t.registers.ff[7].d t.registers.ff[4].d t.registers.ff[7]._sqi t.registers.clk_dly.dly[1].__y t.registers.ff[15].clk t.registers.ff[6]._mqib t.registers.ff[2].__clk t.registers.ff[2]._sqib t.registers.clk_dly.mu2[0]._y t.registers.ff[9].reset_B t.registers.ff[10].d t.registers.ff[1].q t.registers.ff[3]._sqi t.registers.ff[5]._mqib t.registers.ff[6].d t.registers.ff[13].clk t.registers.ff[6]._clk t.registers.ff[5]._sqi t.registers.ff[12]._sqi t.registers.ff[9]._sqi t.registers.ff[4]._clk t.registers.ff[12]._mqi t.registers.ack_dly.dly[1]._y t.registers.ff[9].__clk t.registers.ff[14].d t.registers.ff[13]._mqi t.registers.ff[8].reset_B t.registers.ack_dly.dly[1].y t.registers.ff[0]._clk t.registers.ff[3]._sqib t.registers.ack_dly.and2[1]._y t.registers.ff[13].d t.registers.ff[1]._mqib t.registers.ff[0].__clk t.registers.ff[4].clk t.registers.ff[9].d t.registers.ack_dly.dly[0].y t.registers.clk_dly.dly[2].__y t.registers.ff[12].q t.registers.ff[10]._mqi t.registers.ff[5]._clk t.registers.ff[12].d t.registers.ff[15].d t.registers.ack_dly.dly[1].a t.registers.ff[9]._sqib t.registers.ff[2].clk t.registers.ff[4]._mqi t.registers.ff[10]._clk t.registers.ff[12]._mqib t.registers.ff[2]._mqib t.registers.ff[8].__clk t.registers.ff[11]._mqib t.registers.ff[1]._clk t.registers.ff[11]._sqib t.registers.ff[9].q t.registers.ff[3].q t.registers.ff[6].q t.registers.ff[10]._sqib t.registers.ff[2].d t.registers.ff[8]._mqi t.registers.ff[1].reset_B t.registers.ff[11].q t.registers.ff[12].reset_B t.registers.ack_dly.dly[2].__y t.registers.ff[6]._sqib t.registers.ff[11].clk t.registers.ff[0]._mqi t.registers.ff[12]._clk t.registers.ff[15]._sqi t.registers.ff[4]._sqi t.registers.ff[8]._sqib t.registers.ff[12].__clk t.registers.ff[6]._sqi t.registers.ff[13].__clk t.registers.ff[14]._mqib t.registers.ff[14].__clk t.registers.ack_dly.and2[0]._y t.registers.ack_dly.mu2[1]._s t.registers.ff[7].__clk t.registers.ff[14]._sqib t.registers.clk_dly.dly[2].___y t.registers.ff[14].clk t.registers.ff[11].d t.registers.ack_input_X.buf1._y t.registers.ff[0]._mqib t.registers.ff[15]._sqib t.registers.ff[0].reset_B t.registers.ack_dly.mu2[1]._y t.registers.ff[5].clk t.registers.ff[7].q t.registers.ff[3]._mqi t.registers.ack_dly.dly[0].__y t.registers.ff[13].reset_B t.registers.ff[8].clk t.registers.ff[15].__clk t.registers.ff[0]._sqi t.registers.ff[15]._mqi t.registers.ack_dly.mu2[0]._s t.registers.ff[7].reset_B 
+	    218489 Reset : 0
+	    218490 t._reset_B : 1  [by Reset:=0]
+	    220296 t.registers.reset_buf_BX._y : 0  [by t._reset_B:=1]
+	    220497 t.registers.reset_buf_BXX._y : 0  [by t._reset_B:=1]
+	    221087 t.registers._reset_mem_BX : 1  [by t.registers.reset_buf_BXX._y:=0]
+	    221265 t.registers.reset_bufarray.buf6._y : 0  [by t.registers._reset_mem_BX:=1]
+	    221505 t.registers._reset_BX : 1  [by t.registers.reset_buf_BX._y:=0]
+	    222068 t.registers._reset_mem_BXX[0] : 1  [by t.registers.reset_bufarray.buf6._y:=0]
+[1] reset completed
+	    222068 t.dly_cfg[0] : 1
+	    222068 t.dly_cfg[1] : 1
+	    222090 t.registers.ack_dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
+	    222232 t.registers.ack_dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
+	    222915 t.registers.clk_dly.mu2[1]._s : 0  [by t.dly_cfg[1]:=1]
+	    224263 t.registers.clk_dly.mu2[0]._s : 0  [by t.dly_cfg[0]:=1]
+	    254391 t.registers.clk_dly.mu2[0]._y : 1  [by t.registers.clk_dly.mu2[0]._s:=0]
+	    254524 t.registers.clk_dly._a[1] : 0  [by t.registers.clk_dly.mu2[0]._y:=1]
+	    270186 t.registers.clk_dly.and2[1]._y : 1  [by t.registers.clk_dly._a[1]:=0]
+	    270545 t.registers.clk_dly.dly[1].a : 0  [by t.registers.clk_dly.and2[1]._y:=1]
+	    284661 t.registers.clk_dly.dly[1]._y : 1  [by t.registers.clk_dly.dly[1].a:=0]
+	    284882 t.registers.clk_dly.dly[1].__y : 0  [by t.registers.clk_dly.dly[1]._y:=1]
+	    284889 t.registers.clk_dly.dly[1].___y : 1  [by t.registers.clk_dly.dly[1].__y:=0]
+	    284919 t.registers.clk_dly.dly[1].y : 0  [by t.registers.clk_dly.dly[1].___y:=1]
+	    291632 t.registers.clk_dly.dly[2]._y : 1  [by t.registers.clk_dly.dly[1].y:=0]
+	    349093 t.registers.clk_dly.dly[2].__y : 0  [by t.registers.clk_dly.dly[2]._y:=1]
+	    349184 t.registers.clk_dly.dly[2].___y : 1  [by t.registers.clk_dly.dly[2].__y:=0]
+	    351373 t.registers.clk_dly.dly[2].y : 0  [by t.registers.clk_dly.dly[2].___y:=1]
+	    351380 t.registers.clk_dly.mu2[1]._y : 1  [by t.registers.clk_dly.dly[2].y:=0]
+	    354167 t.registers._clock_temp : 0  [by t.registers.clk_dly.mu2[1]._y:=1]
+	    354273 t.registers.clk_X.buf1._y : 1  [by t.registers._clock_temp:=0]
+	    354351 t.registers._clock : 0  [by t.registers.clk_X.buf1._y:=1]
+	    354626 t.registers.ack_dly.and2[0]._y : 1  [by t.registers._clock:=0]
+	    373622 t.registers.ack_dly.dly[0].a : 0  [by t.registers.ack_dly.and2[0]._y:=1]
+	    374077 t.registers.ack_dly.dly[0]._y : 1  [by t.registers.ack_dly.dly[0].a:=0]
+	    374089 t.registers.ack_dly.dly[0].__y : 0  [by t.registers.ack_dly.dly[0]._y:=1]
+	    374493 t.registers.ack_dly.dly[0].___y : 1  [by t.registers.ack_dly.dly[0].__y:=0]
+	    374505 t.registers.ack_dly.dly[0].y : 0  [by t.registers.ack_dly.dly[0].___y:=1]
+	    380421 t.registers.ack_dly.mu2[0]._y : 1  [by t.registers.ack_dly.dly[0].y:=0]
+	    384697 t.registers.ack_dly._a[1] : 0  [by t.registers.ack_dly.mu2[0]._y:=1]
+	    387596 t.registers.ack_dly.and2[1]._y : 1  [by t.registers.ack_dly._a[1]:=0]
+	    391891 t.registers.ack_dly.dly[1].a : 0  [by t.registers.ack_dly.and2[1]._y:=1]
+	    391893 t.registers.ack_dly.dly[1]._y : 1  [by t.registers.ack_dly.dly[1].a:=0]
+	    396428 t.registers.ack_dly.dly[1].__y : 0  [by t.registers.ack_dly.dly[1]._y:=1]
+	    397677 t.registers.ack_dly.dly[1].___y : 1  [by t.registers.ack_dly.dly[1].__y:=0]
+	    401176 t.registers.ack_dly.dly[1].y : 0  [by t.registers.ack_dly.dly[1].___y:=1]
+	    401342 t.registers.ack_dly.dly[2]._y : 1  [by t.registers.ack_dly.dly[1].y:=0]
+	    401417 t.registers.ack_dly.dly[2].__y : 0  [by t.registers.ack_dly.dly[2]._y:=1]
+	    401762 t.registers.ack_dly.dly[2].___y : 1  [by t.registers.ack_dly.dly[2].__y:=0]
+	    401900 t.registers.ack_dly.dly[2].y : 0  [by t.registers.ack_dly.dly[2].___y:=1]
+	    407163 t.registers.ack_dly.mu2[1]._y : 1  [by t.registers.ack_dly.dly[2].y:=0]
+	    407165 t.registers._in_a_temp : 0  [by t.registers.ack_dly.mu2[1]._y:=1]
+	    451082 t.registers.ack_input_X.buf1._y : 1  [by t.registers._in_a_temp:=0]
+	    451083 t.in.a : 0  [by t.registers.ack_input_X.buf1._y:=1]
+[2] delay line set
+	    451083 t.in.d.d[0].t : 1
+	    451083 t.in.d.d[4].f : 1
+	    451083 t.registers.atree[0].in[0] : 1
+	    451083 t.in.d.d[1].t : 1
+	    451083 t.registers.atree[0].in[1] : 1
+	    451094 t.registers.val_input.OR2_tf[4]._y : 0  [by t.in.d.d[4].f:=1]
+	    451099 t.registers.atree[0].and2s[0]._y : 0  [by t.registers.atree[0].in[1]:=1]
+	    451150 t.registers.val_input.OR2_tf[1]._y : 0  [by t.in.d.d[1].t:=1]
+	    451453 t.registers.val_input.OR2_tf[2]._y : 0  [by t.registers.atree[0].in[0]:=1]
+	    451622 t.registers.val_input.ct.in[4] : 1  [by t.registers.val_input.OR2_tf[4]._y:=0]
+	    451631 t.registers.val_input.OR2_tf[0]._y : 0  [by t.in.d.d[0].t:=1]
+	    453534 t.registers._out_encoder[0] : 1  [by t.registers.atree[0].and2s[0]._y:=0]
+	    453724 t.registers.val_input.OR2_tf[3]._y : 0  [by t.registers.atree[0].in[1]:=1]
+	    453726 t.registers.val_input.ct.in[3] : 1  [by t.registers.val_input.OR2_tf[3]._y:=0]
+	    455645 t.registers.atree[4].and2s[0]._y : 0  [by t.registers.atree[0].in[1]:=1]
+	    464672 t.registers.val_input.ct.in[0] : 1  [by t.registers.val_input.OR2_tf[0]._y:=0]
+	    475378 t.registers.val_input.ct.in[2] : 1  [by t.registers.val_input.OR2_tf[2]._y:=0]
+	    475381 t.registers.val_input.ct.C3Els[0]._y : 0  [by t.registers.val_input.ct.in[2]:=1]
+	    475410 t.registers.val_input.ct.tmp[6] : 1  [by t.registers.val_input.ct.C3Els[0]._y:=0]
+	    478030 t.registers.val_input.ct.in[1] : 1  [by t.registers.val_input.OR2_tf[1]._y:=0]
+	    478347 t.registers.val_input.ct.C2Els[0]._y : 0  [by t.registers.val_input.ct.in[1]:=1]
+	    479948 t.registers.val_input.ct.tmp[5] : 1  [by t.registers.val_input.ct.C2Els[0]._y:=0]
+	    480101 t.registers.val_input.ct.C2Els[1]._y : 0  [by t.registers.val_input.ct.tmp[5]:=1]
+	    480145 t.registers._in_v_temp : 1  [by t.registers.val_input.ct.C2Els[1]._y:=0]
+	    482906 t.registers.clk_dly.and2[0]._y : 0  [by t.registers._in_v_temp:=1]
+	    482907 t.registers.clk_dly.dly[0].a : 1  [by t.registers.clk_dly.and2[0]._y:=0]
+	    483124 t.registers.clk_dly.dly[0]._y : 0  [by t.registers.clk_dly.dly[0].a:=1]
+	    483146 t.registers.clk_dly.dly[0].__y : 1  [by t.registers.clk_dly.dly[0]._y:=0]
+	    483147 t.registers.clk_dly.dly[0].___y : 0  [by t.registers.clk_dly.dly[0].__y:=1]
+	    484728 t.registers.clk_dly.dly[0].y : 1  [by t.registers.clk_dly.dly[0].___y:=0]
+	    493828 t.registers.val_input_X.buf1._y : 0  [by t.registers._in_v_temp:=1]
+	    493987 t.in.v : 1  [by t.registers.val_input_X.buf1._y:=0]
+	    494073 t.registers.clk_dly.mu2[0]._y : 0  [by t.registers.clk_dly.dly[0].y:=1]
+	    513749 t.registers.clk_dly._a[1] : 1  [by t.registers.clk_dly.mu2[0]._y:=0]
+	    515036 t.registers.clk_dly.and2[1]._y : 0  [by t.registers.clk_dly._a[1]:=1]
+	    516603 t.registers._out_encoder[4] : 1  [by t.registers.atree[4].and2s[0]._y:=0]
+	    517268 t.registers.clk_dly.dly[1].a : 1  [by t.registers.clk_dly.and2[1]._y:=0]
+	    517413 t.registers.clk_dly.dly[1]._y : 0  [by t.registers.clk_dly.dly[1].a:=1]
+	    520245 t.registers.clk_dly.dly[1].__y : 1  [by t.registers.clk_dly.dly[1]._y:=0]
+	    526599 t.registers.clk_dly.dly[1].___y : 0  [by t.registers.clk_dly.dly[1].__y:=1]
+	    526600 t.registers.clk_dly.dly[1].y : 1  [by t.registers.clk_dly.dly[1].___y:=0]
+	    565884 t.registers.clk_dly.dly[2]._y : 0  [by t.registers.clk_dly.dly[1].y:=1]
+	    566046 t.registers.clk_dly.dly[2].__y : 1  [by t.registers.clk_dly.dly[2]._y:=0]
+	    573415 t.registers.clk_dly.dly[2].___y : 0  [by t.registers.clk_dly.dly[2].__y:=1]
+	    573429 t.registers.clk_dly.dly[2].y : 1  [by t.registers.clk_dly.dly[2].___y:=0]
+	    573436 t.registers.clk_dly.mu2[1]._y : 0  [by t.registers.clk_dly.dly[2].y:=1]
+	    573596 t.registers._clock_temp : 1  [by t.registers.clk_dly.mu2[1]._y:=0]
+	    595153 t.registers.clk_X.buf1._y : 0  [by t.registers._clock_temp:=1]
+	    595154 t.registers._clock : 1  [by t.registers.clk_X.buf1._y:=0]
+	    595155 t.registers.and_encoder[4]._y : 0  [by t.registers._clock:=1]
+	    595155 t.registers.and_encoder[0]._y : 0  [by t.registers._clock:=1]
+	    595156 t.registers._clock_word_temp[0] : 1  [by t.registers.and_encoder[0]._y:=0]
+	    595342 t.registers._clock_word_temp[4] : 1  [by t.registers.and_encoder[4]._y:=0]
+	    597397 t.registers.ack_dly.and2[0]._y : 0  [by t.registers._clock:=1]
+	    597398 t.registers.ack_dly.dly[0].a : 1  [by t.registers.ack_dly.and2[0]._y:=0]
+	    598251 t.registers.ack_dly.dly[0]._y : 0  [by t.registers.ack_dly.dly[0].a:=1]
+	    598256 t.registers.ack_dly.dly[0].__y : 1  [by t.registers.ack_dly.dly[0]._y:=0]
+	    599147 t.registers.ack_dly.dly[0].___y : 0  [by t.registers.ack_dly.dly[0].__y:=1]
+	    599148 t.registers.ack_dly.dly[0].y : 1  [by t.registers.ack_dly.dly[0].___y:=0]
+	    599165 t.registers.ack_dly.mu2[0]._y : 0  [by t.registers.ack_dly.dly[0].y:=1]
+WARNING: interference `t.registers._clock_buffer_out[0]'
+>> cause: t.registers.clock_buffer[0].buf1._y (val: 0)
+>> time:     599338
+	    599338 t.registers.clock_buffer[0].buf1._y : 0  [by t.registers._clock_word_temp[0]:=1]
+	    601738 t.registers.ack_dly._a[1] : 1  [by t.registers.ack_dly.mu2[0]._y:=0]
+	    601741 t.registers.ack_dly.and2[1]._y : 0  [by t.registers.ack_dly._a[1]:=1]
+	    602682 t.registers.ack_dly.dly[1].a : 1  [by t.registers.ack_dly.and2[1]._y:=0]
+	    607699 t.registers._clock_buffer_out[0] : X  [by t.registers.clock_buffer[0].buf1._y:=0]
+	    630124 t.registers.clock_buffer[4].buf1._y : 0  [by t.registers._clock_word_temp[4]:=1]
+	    661644 t.registers.ack_dly.dly[1]._y : 0  [by t.registers.ack_dly.dly[1].a:=1]
+	    661645 t.registers.ack_dly.dly[1].__y : 1  [by t.registers.ack_dly.dly[1]._y:=0]
+	    661687 t.registers.ack_dly.dly[1].___y : 0  [by t.registers.ack_dly.dly[1].__y:=1]
+	    664504 t.registers.ack_dly.dly[1].y : 1  [by t.registers.ack_dly.dly[1].___y:=0]
+	    678237 t.registers.ack_dly.dly[2]._y : 0  [by t.registers.ack_dly.dly[1].y:=1]
+	    678332 t.registers.ack_dly.dly[2].__y : 1  [by t.registers.ack_dly.dly[2]._y:=0]
+	    678667 t.registers.ack_dly.dly[2].___y : 0  [by t.registers.ack_dly.dly[2].__y:=1]
+	    678675 t.registers.ack_dly.dly[2].y : 1  [by t.registers.ack_dly.dly[2].___y:=0]
+	    678709 t.registers.ack_dly.mu2[1]._y : 0  [by t.registers.ack_dly.dly[2].y:=1]
+	    692596 t.registers._in_a_temp : 1  [by t.registers.ack_dly.mu2[1]._y:=0]
+	    693514 t.registers.ack_input_X.buf1._y : 0  [by t.registers._in_a_temp:=1]
+	    693518 t.in.a : 1  [by t.registers.ack_input_X.buf1._y:=0]
+	    693518 t.in.d.d[0].t : 0
+	    693518 t.in.d.d[4].f : 0
+	    693518 t.registers.atree[0].in[0] : 0
+	    693518 t.in.d.d[1].t : 0
+	    693518 t.registers.atree[0].in[1] : 0
+	    693521 t.registers.val_input.OR2_tf[1]._y : 1  [by t.in.d.d[1].t:=0]
+	    693566 t.registers.atree[4].and2s[0]._y : 1  [by t.registers.atree[0].in[0]:=0]
+	    693696 t.registers.val_input.OR2_tf[3]._y : 1  [by t.registers.atree[0].in[1]:=0]
+	    695916 t.registers.val_input.OR2_tf[4]._y : 1  [by t.in.d.d[4].f:=0]
+	    696733 t.registers.val_input.OR2_tf[2]._y : 1  [by t.registers.atree[0].in[0]:=0]
+	    697560 t.registers.val_input.ct.in[2] : 0  [by t.registers.val_input.OR2_tf[2]._y:=1]
+	    699647 t.registers.val_input.ct.in[3] : 0  [by t.registers.val_input.OR2_tf[3]._y:=1]
+	    705465 t.registers._out_encoder[4] : 0  [by t.registers.atree[4].and2s[0]._y:=1]
+	    705638 t.registers.and_encoder[4]._y : 1  [by t.registers._out_encoder[4]:=0]
+	    705822 t.registers._clock_word_temp[4] : 0  [by t.registers.and_encoder[4]._y:=1]
+	    705823 t.registers.clock_buffer[4].buf1._y : 1  [by t.registers._clock_word_temp[4]:=0]
+	    714498 t.registers.val_input.ct.in[1] : 0  [by t.registers.val_input.OR2_tf[1]._y:=1]
+	    735401 t.registers.val_input.ct.in[4] : 0  [by t.registers.val_input.OR2_tf[4]._y:=1]
+	    735474 t.registers.val_input.ct.C3Els[0]._y : 1  [by t.registers.val_input.ct.in[4]:=0]
+	    735478 t.registers.val_input.ct.tmp[6] : 0  [by t.registers.val_input.ct.C3Els[0]._y:=1]
+	    739896 t.registers.val_input.OR2_tf[0]._y : 1  [by t.in.d.d[0].t:=0]
+	    740637 t.registers.atree[0].and2s[0]._y : 1  [by t.registers.atree[0].in[0]:=0]
+	    740733 t.registers._out_encoder[0] : 0  [by t.registers.atree[0].and2s[0]._y:=1]
+	    740869 t.registers.and_encoder[0]._y : 1  [by t.registers._out_encoder[0]:=0]
+	    740870 t.registers._clock_word_temp[0] : 0  [by t.registers.and_encoder[0]._y:=1]
+	    759916 t.registers.clock_buffer[0].buf1._y : 1  [by t.registers._clock_word_temp[0]:=0]
+	    760157 t.registers._clock_buffer_out[0] : 0  [by t.registers.clock_buffer[0].buf1._y:=1]
+	    777184 t.registers.val_input.ct.in[0] : 0  [by t.registers.val_input.OR2_tf[0]._y:=1]
+	    781143 t.registers.val_input.ct.C2Els[0]._y : 1  [by t.registers.val_input.ct.in[0]:=0]
+	    781155 t.registers.val_input.ct.tmp[5] : 0  [by t.registers.val_input.ct.C2Els[0]._y:=1]
+	    785055 t.registers.val_input.ct.C2Els[1]._y : 1  [by t.registers.val_input.ct.tmp[5]:=0]
+	    786084 t.registers._in_v_temp : 0  [by t.registers.val_input.ct.C2Els[1]._y:=1]
+	    786085 t.registers.clk_dly.and2[0]._y : 1  [by t.registers._in_v_temp:=0]
+	    786140 t.registers.val_input_X.buf1._y : 1  [by t.registers._in_v_temp:=0]
+	    786141 t.in.v : 0  [by t.registers.val_input_X.buf1._y:=1]
+	    831091 t.registers.clk_dly.dly[0].a : 0  [by t.registers.clk_dly.and2[0]._y:=1]
+	    831128 t.registers.clk_dly.dly[0]._y : 1  [by t.registers.clk_dly.dly[0].a:=0]
+	    854503 t.registers.clk_dly.dly[0].__y : 0  [by t.registers.clk_dly.dly[0]._y:=1]
+	    854504 t.registers.clk_dly.dly[0].___y : 1  [by t.registers.clk_dly.dly[0].__y:=0]
+	    858068 t.registers.clk_dly.dly[0].y : 0  [by t.registers.clk_dly.dly[0].___y:=1]
+	    859760 t.registers.clk_dly.mu2[0]._y : 1  [by t.registers.clk_dly.dly[0].y:=0]
+	    859773 t.registers.clk_dly._a[1] : 0  [by t.registers.clk_dly.mu2[0]._y:=1]
+	    876757 t.registers.clk_dly.and2[1]._y : 1  [by t.registers.clk_dly._a[1]:=0]
+	    877114 t.registers.clk_dly.dly[1].a : 0  [by t.registers.clk_dly.and2[1]._y:=1]
+	    877139 t.registers.clk_dly.dly[1]._y : 1  [by t.registers.clk_dly.dly[1].a:=0]
+	    877160 t.registers.clk_dly.dly[1].__y : 0  [by t.registers.clk_dly.dly[1]._y:=1]
+	    877161 t.registers.clk_dly.dly[1].___y : 1  [by t.registers.clk_dly.dly[1].__y:=0]
+	    886809 t.registers.clk_dly.dly[1].y : 0  [by t.registers.clk_dly.dly[1].___y:=1]
+	    886810 t.registers.clk_dly.dly[2]._y : 1  [by t.registers.clk_dly.dly[1].y:=0]
+	    886811 t.registers.clk_dly.dly[2].__y : 0  [by t.registers.clk_dly.dly[2]._y:=1]
+	    886972 t.registers.clk_dly.dly[2].___y : 1  [by t.registers.clk_dly.dly[2].__y:=0]
+	    888009 t.registers.clk_dly.dly[2].y : 0  [by t.registers.clk_dly.dly[2].___y:=1]
+	    888014 t.registers.clk_dly.mu2[1]._y : 1  [by t.registers.clk_dly.dly[2].y:=0]
+	    888595 t.registers._clock_temp : 0  [by t.registers.clk_dly.mu2[1]._y:=1]
+	    889003 t.registers.clk_X.buf1._y : 1  [by t.registers._clock_temp:=0]
+	    889014 t.registers._clock : 0  [by t.registers.clk_X.buf1._y:=1]
+	    890061 t.registers.ack_dly.and2[0]._y : 1  [by t.registers._clock:=0]
+	    890075 t.registers.ack_dly.dly[0].a : 0  [by t.registers.ack_dly.and2[0]._y:=1]
+	    890093 t.registers.ack_dly.dly[0]._y : 1  [by t.registers.ack_dly.dly[0].a:=0]
+	    890097 t.registers.ack_dly.dly[0].__y : 0  [by t.registers.ack_dly.dly[0]._y:=1]
+	    890201 t.registers.ack_dly.dly[0].___y : 1  [by t.registers.ack_dly.dly[0].__y:=0]
+	    921645 t.registers.ack_dly.dly[0].y : 0  [by t.registers.ack_dly.dly[0].___y:=1]
+	    922849 t.registers.ack_dly.mu2[0]._y : 1  [by t.registers.ack_dly.dly[0].y:=0]
+	    931304 t.registers.ack_dly._a[1] : 0  [by t.registers.ack_dly.mu2[0]._y:=1]
+	    931532 t.registers.ack_dly.and2[1]._y : 1  [by t.registers.ack_dly._a[1]:=0]
+	    932375 t.registers.ack_dly.dly[1].a : 0  [by t.registers.ack_dly.and2[1]._y:=1]
+	    933834 t.registers.ack_dly.dly[1]._y : 1  [by t.registers.ack_dly.dly[1].a:=0]
+	    933904 t.registers.ack_dly.dly[1].__y : 0  [by t.registers.ack_dly.dly[1]._y:=1]
+	    984326 t.registers.ack_dly.dly[1].___y : 1  [by t.registers.ack_dly.dly[1].__y:=0]
+	    984337 t.registers.ack_dly.dly[1].y : 0  [by t.registers.ack_dly.dly[1].___y:=1]
+	    984340 t.registers.ack_dly.dly[2]._y : 1  [by t.registers.ack_dly.dly[1].y:=0]
+	    984394 t.registers.ack_dly.dly[2].__y : 0  [by t.registers.ack_dly.dly[2]._y:=1]
+	    985542 t.registers.ack_dly.dly[2].___y : 1  [by t.registers.ack_dly.dly[2].__y:=0]
+	    986703 t.registers.ack_dly.dly[2].y : 0  [by t.registers.ack_dly.dly[2].___y:=1]
+	    995355 t.registers.ack_dly.mu2[1]._y : 1  [by t.registers.ack_dly.dly[2].y:=0]
+	    995436 t.registers._in_a_temp : 0  [by t.registers.ack_dly.mu2[1]._y:=1]
+	   1006513 t.registers.ack_input_X.buf1._y : 1  [by t.registers._in_a_temp:=0]
+	   1024496 t.in.a : 0  [by t.registers.ack_input_X.buf1._y:=1]
+WRONG ASSERT:	"t.registers.ff[0].q" has value X and not 1.
+WRONG ASSERT:	"t.registers.ff[1].q" has value X and not 1.
+[3] clock checked

test/unit_tests/register_write/test.act

@@ -30,13 +30,13 @@ import "../../dataflow_neuro/registers.act";
 import globals;
 
 open tmpl::dataflow_neuro;
-
+// 2 bits encoder, 2 bits long words, 2 delays????
-defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]){
+defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]; bool? dly_cfg[2]){
 
     register_rw<2,2,2> registers(.in=in,.data = data);
     //Low active Reset 
     bool _reset_B; 
-    power supply;
+    power _supply;
     prs {
     	Reset => _reset_B-
     }
@@ -44,7 +44,8 @@ defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]){
     _supply.vss = GND;
     _supply.vdd = Vdd;
     registers.reset_B = _reset_B;
-    registers.reset_B_mem = _reset_B;
+    registers.reset_mem_B = _reset_B;
+    registers.dly_cfg = dly_cfg;
     
 }
 

test/unit_tests/register_write/test.prsim

@@ -1,8 +1,43 @@
 watchall
 system "echo '[0] start test'"
 set Reset 1
-set-qdi-channel-neutral "t.in" 2
+
+
+set-qdi-channel-neutral "t.in" 5
+set t.data[0].d[0] 0
+set t.data[0].d[1] 0
+set t.data[1].d[0] 0
+set t.data[1].d[1] 0
 cycle
 status X
 mode run
+assert-qdi-channel-neutral "t.in" 5
+assert t.data[0].d[0] 0
+assert t.data[0].d[1] 0
+assert t.data[1].d[0] 0
+assert t.data[1].d[1] 0
+set Reset 0
+cycle
 system "echo '[1] reset completed'"
+# Set delay config lines
+set t.dly_cfg[0] 1
+set t.dly_cfg[1] 1
+cycle
+assert-qdi-channel-neutral "t.in" 5
+system "echo '[2] delay line set'"
+set-qdi-channel-valid "t.in" 5 3
+cycle
+assert-qdi-channel-valid "t.in" 5 3
+assert t.registers._clock 1
+assert t.registers._out_encoder[0] 1
+assert t.registers._out_encoder[1] 0
+assert t.registers._out_encoder[2] 0
+assert t.registers._out_encoder[3] 0
+set-qdi-channel-neutral "t.in" 5
+cycle
+assert t.registers._clock 0
+assert t.registers.ff[0].q 1
+assert t.registers.ff[1].q 1
+system "echo '[3] clock checked'"
+
+

test/unit_tests/vtree_5/run/prsim.out

@@ -0,0 +1,50 @@
+t._in.d[1].t t.vtree_test.ct.in[2] t._in.d[2].f t._in.d[3].t t._in.d[3].f t.vtree_test.ct.C3Els[0]._y t.vtree_test.ct.in[0] t._in.d[4].f t._in.d[0].f t._in.d[4].t t._in.d[0].t t.out t._in.d[1].f t._in.d[2].t t.vtree_test.ct.in[3] t.vtree_test.ct.tmp[6] t.vtree_test.OR2_tf[3]._y t.vtree_test.ct.in[1] t.vtree_test.ct.in[4] t.vtree_test.OR2_tf[4]._y t.vtree_test.OR2_tf[0]._y t.vtree_test.ct.C2Els[1]._y t.vtree_test.ct.C2Els[0]._y t.vtree_test.ct.tmp[5] t.vtree_test.OR2_tf[2]._y t.vtree_test.OR2_tf[1]._y 
+[0] starting test true high
+	         0 t._in.d[0].f : 0
+	         0 t._in.d[4].t : 0
+	         0 t._in.d[4].f : 0
+	         0 t._in.d[3].t : 0
+	         0 t._in.d[1].f : 0
+	         0 t._in.d[3].f : 0
+	         0 t._in.d[2].t : 0
+	         0 t._in.d[0].t : 0
+	         0 t._in.d[2].f : 0
+	         0 t._in.d[1].t : 0
+	         1 t.vtree_test.OR2_tf[4]._y : 1  [by t._in.d[4].f:=0]
+	         2 t.vtree_test.OR2_tf[2]._y : 1  [by t._in.d[2].f:=0]
+	       116 t.vtree_test.ct.in[2] : 0  [by t.vtree_test.OR2_tf[2]._y:=1]
+	      1138 t.vtree_test.ct.in[4] : 0  [by t.vtree_test.OR2_tf[4]._y:=1]
+	      4753 t.vtree_test.OR2_tf[1]._y : 1  [by t._in.d[1].t:=0]
+	      7092 t.vtree_test.OR2_tf[3]._y : 1  [by t._in.d[3].f:=0]
+	      8818 t.vtree_test.ct.in[3] : 0  [by t.vtree_test.OR2_tf[3]._y:=1]
+	      8857 t.vtree_test.ct.C3Els[0]._y : 1  [by t.vtree_test.ct.in[3]:=0]
+	      8872 t.vtree_test.ct.tmp[6] : 0  [by t.vtree_test.ct.C3Els[0]._y:=1]
+	     10467 t.vtree_test.OR2_tf[0]._y : 1  [by t._in.d[0].t:=0]
+	     10958 t.vtree_test.ct.in[0] : 0  [by t.vtree_test.OR2_tf[0]._y:=1]
+	     70119 t.vtree_test.ct.in[1] : 0  [by t.vtree_test.OR2_tf[1]._y:=1]
+	     70132 t.vtree_test.ct.C2Els[0]._y : 1  [by t.vtree_test.ct.in[1]:=0]
+	     70172 t.vtree_test.ct.tmp[5] : 0  [by t.vtree_test.ct.C2Els[0]._y:=1]
+	     70587 t.vtree_test.ct.C2Els[1]._y : 1  [by t.vtree_test.ct.tmp[5]:=0]
+	     70607 t.out : 0  [by t.vtree_test.ct.C2Els[1]._y:=1]
+	     70607 t._in.d[0].t : 1
+	     70607 t._in.d[4].f : 1
+	     70607 t._in.d[2].f : 1
+	     70607 t._in.d[1].t : 1
+	     70607 t._in.d[3].f : 1
+	     70623 t.vtree_test.OR2_tf[2]._y : 0  [by t._in.d[2].f:=1]
+	     70627 t.vtree_test.ct.in[2] : 1  [by t.vtree_test.OR2_tf[2]._y:=0]
+	     70654 t.vtree_test.OR2_tf[4]._y : 0  [by t._in.d[4].f:=1]
+	     76668 t.vtree_test.OR2_tf[0]._y : 0  [by t._in.d[0].t:=1]
+	     76683 t.vtree_test.ct.in[0] : 1  [by t.vtree_test.OR2_tf[0]._y:=0]
+	     79783 t.vtree_test.ct.in[4] : 1  [by t.vtree_test.OR2_tf[4]._y:=0]
+	     84331 t.vtree_test.OR2_tf[3]._y : 0  [by t._in.d[3].f:=1]
+	    114705 t.vtree_test.OR2_tf[1]._y : 0  [by t._in.d[1].t:=1]
+	    127579 t.vtree_test.ct.in[3] : 1  [by t.vtree_test.OR2_tf[3]._y:=0]
+	    127634 t.vtree_test.ct.C3Els[0]._y : 0  [by t.vtree_test.ct.in[3]:=1]
+	    151636 t.vtree_test.ct.in[1] : 1  [by t.vtree_test.OR2_tf[1]._y:=0]
+	    179287 t.vtree_test.ct.tmp[6] : 1  [by t.vtree_test.ct.C3Els[0]._y:=0]
+	    181416 t.vtree_test.ct.C2Els[0]._y : 0  [by t.vtree_test.ct.in[1]:=1]
+	    195265 t.vtree_test.ct.tmp[5] : 1  [by t.vtree_test.ct.C2Els[0]._y:=0]
+	    220077 t.vtree_test.ct.C2Els[1]._y : 0  [by t.vtree_test.ct.tmp[5]:=1]
+	    234420 t.out : 1  [by t.vtree_test.ct.C2Els[1]._y:=0]
+[1] cleaning input

test/unit_tests/vtree_5/run/test.prs

@@ -0,0 +1,218 @@
+= "GND" "GND"
+= "Vdd" "Vdd"
+= "Reset" "Reset"
+~"t.vtree_test.ct.C2Els[0].c1"&~"t.vtree_test.ct.C2Els[0].c2"->"t.vtree_test.ct.C2Els[0]._y"+
+"t.vtree_test.ct.C2Els[0].c1"&"t.vtree_test.ct.C2Els[0].c2"->"t.vtree_test.ct.C2Els[0]._y"-
+"t.vtree_test.ct.C2Els[0]._y"->"t.vtree_test.ct.C2Els[0].y"-
+~("t.vtree_test.ct.C2Els[0]._y")->"t.vtree_test.ct.C2Els[0].y"+
+~"t.vtree_test.ct.C2Els[1].c1"&~"t.vtree_test.ct.C2Els[1].c2"->"t.vtree_test.ct.C2Els[1]._y"+
+"t.vtree_test.ct.C2Els[1].c1"&"t.vtree_test.ct.C2Els[1].c2"->"t.vtree_test.ct.C2Els[1]._y"-
+"t.vtree_test.ct.C2Els[1]._y"->"t.vtree_test.ct.C2Els[1].y"-
+~("t.vtree_test.ct.C2Els[1]._y")->"t.vtree_test.ct.C2Els[1].y"+
+~"t.vtree_test.ct.C3Els[0].c1"&~"t.vtree_test.ct.C3Els[0].c2"&~"t.vtree_test.ct.C3Els[0].c3"->"t.vtree_test.ct.C3Els[0]._y"+
+"t.vtree_test.ct.C3Els[0].c1"&"t.vtree_test.ct.C3Els[0].c2"&"t.vtree_test.ct.C3Els[0].c3"->"t.vtree_test.ct.C3Els[0]._y"-
+"t.vtree_test.ct.C3Els[0]._y"->"t.vtree_test.ct.C3Els[0].y"-
+~("t.vtree_test.ct.C3Els[0]._y")->"t.vtree_test.ct.C3Els[0].y"+
+= "t.vtree_test.ct.tmp[5]" "t.vtree_test.ct.C2Els[1].c1"
+= "t.vtree_test.ct.tmp[5]" "t.vtree_test.ct.C2Els[0].y"
+= "t.vtree_test.ct.tmp[6]" "t.vtree_test.ct.C2Els[1].c2"
+= "t.vtree_test.ct.tmp[6]" "t.vtree_test.ct.C3Els[0].y"
+= "t.vtree_test.ct.supply.vdd" "t.vtree_test.ct.C3Els[0].vdd"
+= "t.vtree_test.ct.supply.vdd" "t.vtree_test.ct.C2Els[1].vdd"
+= "t.vtree_test.ct.supply.vdd" "t.vtree_test.ct.C2Els[0].vdd"
+= "t.vtree_test.ct.supply.vss" "t.vtree_test.ct.C3Els[0].vss"
+= "t.vtree_test.ct.supply.vss" "t.vtree_test.ct.C2Els[1].vss"
+= "t.vtree_test.ct.supply.vss" "t.vtree_test.ct.C2Els[0].vss"
+= "t.vtree_test.ct.in[0]" "t.vtree_test.ct.C2Els[0].c1"
+= "t.vtree_test.ct.in[0]" "t.vtree_test.ct.tmp[0]"
+= "t.vtree_test.ct.in[1]" "t.vtree_test.ct.C2Els[0].c2"
+= "t.vtree_test.ct.in[1]" "t.vtree_test.ct.tmp[1]"
+= "t.vtree_test.ct.in[2]" "t.vtree_test.ct.C3Els[0].c1"
+= "t.vtree_test.ct.in[2]" "t.vtree_test.ct.tmp[2]"
+= "t.vtree_test.ct.in[3]" "t.vtree_test.ct.C3Els[0].c2"
+= "t.vtree_test.ct.in[3]" "t.vtree_test.ct.tmp[3]"
+= "t.vtree_test.ct.in[4]" "t.vtree_test.ct.C3Els[0].c3"
+= "t.vtree_test.ct.in[4]" "t.vtree_test.ct.tmp[4]"
+= "t.vtree_test.ct.out" "t.vtree_test.ct.C2Els[1].y"
+= "t.vtree_test.ct.out" "t.vtree_test.ct.tmp[7]"
+= "t.vtree_test.ct.in[0]" "t.vtree_test.OR2_tf[0].y"
+= "t.vtree_test.ct.in[1]" "t.vtree_test.OR2_tf[1].y"
+= "t.vtree_test.ct.in[2]" "t.vtree_test.OR2_tf[2].y"
+= "t.vtree_test.ct.in[3]" "t.vtree_test.OR2_tf[3].y"
+= "t.vtree_test.ct.in[4]" "t.vtree_test.OR2_tf[4].y"
+"t.vtree_test.OR2_tf[0].a"|"t.vtree_test.OR2_tf[0].b"->"t.vtree_test.OR2_tf[0]._y"-
+~("t.vtree_test.OR2_tf[0].a"|"t.vtree_test.OR2_tf[0].b")->"t.vtree_test.OR2_tf[0]._y"+
+"t.vtree_test.OR2_tf[0]._y"->"t.vtree_test.OR2_tf[0].y"-
+~("t.vtree_test.OR2_tf[0]._y")->"t.vtree_test.OR2_tf[0].y"+
+"t.vtree_test.OR2_tf[1].a"|"t.vtree_test.OR2_tf[1].b"->"t.vtree_test.OR2_tf[1]._y"-
+~("t.vtree_test.OR2_tf[1].a"|"t.vtree_test.OR2_tf[1].b")->"t.vtree_test.OR2_tf[1]._y"+
+"t.vtree_test.OR2_tf[1]._y"->"t.vtree_test.OR2_tf[1].y"-
+~("t.vtree_test.OR2_tf[1]._y")->"t.vtree_test.OR2_tf[1].y"+
+"t.vtree_test.OR2_tf[2].a"|"t.vtree_test.OR2_tf[2].b"->"t.vtree_test.OR2_tf[2]._y"-
+~("t.vtree_test.OR2_tf[2].a"|"t.vtree_test.OR2_tf[2].b")->"t.vtree_test.OR2_tf[2]._y"+
+"t.vtree_test.OR2_tf[2]._y"->"t.vtree_test.OR2_tf[2].y"-
+~("t.vtree_test.OR2_tf[2]._y")->"t.vtree_test.OR2_tf[2].y"+
+"t.vtree_test.OR2_tf[3].a"|"t.vtree_test.OR2_tf[3].b"->"t.vtree_test.OR2_tf[3]._y"-
+~("t.vtree_test.OR2_tf[3].a"|"t.vtree_test.OR2_tf[3].b")->"t.vtree_test.OR2_tf[3]._y"+
+"t.vtree_test.OR2_tf[3]._y"->"t.vtree_test.OR2_tf[3].y"-
+~("t.vtree_test.OR2_tf[3]._y")->"t.vtree_test.OR2_tf[3].y"+
+"t.vtree_test.OR2_tf[4].a"|"t.vtree_test.OR2_tf[4].b"->"t.vtree_test.OR2_tf[4]._y"-
+~("t.vtree_test.OR2_tf[4].a"|"t.vtree_test.OR2_tf[4].b")->"t.vtree_test.OR2_tf[4]._y"+
+"t.vtree_test.OR2_tf[4]._y"->"t.vtree_test.OR2_tf[4].y"-
+~("t.vtree_test.OR2_tf[4]._y")->"t.vtree_test.OR2_tf[4].y"+
+= "t.vtree_test.supply.vss" "t.vtree_test.ct.supply.vss"
+= "t.vtree_test.supply.vdd" "t.vtree_test.ct.supply.vdd"
+= "t.vtree_test.supply.vdd" "t.vtree_test.OR2_tf[4].vdd"
+= "t.vtree_test.supply.vdd" "t.vtree_test.OR2_tf[3].vdd"
+= "t.vtree_test.supply.vdd" "t.vtree_test.OR2_tf[2].vdd"
+= "t.vtree_test.supply.vdd" "t.vtree_test.OR2_tf[1].vdd"
+= "t.vtree_test.supply.vdd" "t.vtree_test.OR2_tf[0].vdd"
+= "t.vtree_test.supply.vss" "t.vtree_test.OR2_tf[4].vss"
+= "t.vtree_test.supply.vss" "t.vtree_test.OR2_tf[3].vss"
+= "t.vtree_test.supply.vss" "t.vtree_test.OR2_tf[2].vss"
+= "t.vtree_test.supply.vss" "t.vtree_test.OR2_tf[1].vss"
+= "t.vtree_test.supply.vss" "t.vtree_test.OR2_tf[0].vss"
+= "t.vtree_test.out" "t.vtree_test.ct.out"
+= "t.vtree_test.in.d[0].d[0]" "t.vtree_test.in.d[0].f"
+= "t.vtree_test.in.d[0].d[1]" "t.vtree_test.in.d[0].t"
+= "t.vtree_test.in.d[1].d[0]" "t.vtree_test.in.d[1].f"
+= "t.vtree_test.in.d[1].d[1]" "t.vtree_test.in.d[1].t"
+= "t.vtree_test.in.d[2].d[0]" "t.vtree_test.in.d[2].f"
+= "t.vtree_test.in.d[2].d[1]" "t.vtree_test.in.d[2].t"
+= "t.vtree_test.in.d[3].d[0]" "t.vtree_test.in.d[3].f"
+= "t.vtree_test.in.d[3].d[1]" "t.vtree_test.in.d[3].t"
+= "t.vtree_test.in.d[4].d[0]" "t.vtree_test.in.d[4].f"
+= "t.vtree_test.in.d[4].d[1]" "t.vtree_test.in.d[4].t"
+= "t.vtree_test.in.d[4].d[0]" "t.vtree_test.in.d[4].f"
+= "t.vtree_test.in.d[4].d[1]" "t.vtree_test.in.d[4].t"
+= "t.vtree_test.in.d[3].d[0]" "t.vtree_test.in.d[3].f"
+= "t.vtree_test.in.d[3].d[1]" "t.vtree_test.in.d[3].t"
+= "t.vtree_test.in.d[2].d[0]" "t.vtree_test.in.d[2].f"
+= "t.vtree_test.in.d[2].d[1]" "t.vtree_test.in.d[2].t"
+= "t.vtree_test.in.d[1].d[0]" "t.vtree_test.in.d[1].f"
+= "t.vtree_test.in.d[1].d[1]" "t.vtree_test.in.d[1].t"
+= "t.vtree_test.in.d[0].d[0]" "t.vtree_test.in.d[0].f"
+= "t.vtree_test.in.d[0].d[1]" "t.vtree_test.in.d[0].t"
+= "t.vtree_test.in.d[4].d[0]" "t.vtree_test.OR2_tf[4].b"
+= "t.vtree_test.in.d[4].d[0]" "t.vtree_test.in.d[4].f"
+= "t.vtree_test.in.d[4].d[1]" "t.vtree_test.OR2_tf[4].a"
+= "t.vtree_test.in.d[4].d[1]" "t.vtree_test.in.d[4].t"
+= "t.vtree_test.in.d[3].d[0]" "t.vtree_test.OR2_tf[3].b"
+= "t.vtree_test.in.d[3].d[0]" "t.vtree_test.in.d[3].f"
+= "t.vtree_test.in.d[3].d[1]" "t.vtree_test.OR2_tf[3].a"
+= "t.vtree_test.in.d[3].d[1]" "t.vtree_test.in.d[3].t"
+= "t.vtree_test.in.d[2].d[0]" "t.vtree_test.OR2_tf[2].b"
+= "t.vtree_test.in.d[2].d[0]" "t.vtree_test.in.d[2].f"
+= "t.vtree_test.in.d[2].d[1]" "t.vtree_test.OR2_tf[2].a"
+= "t.vtree_test.in.d[2].d[1]" "t.vtree_test.in.d[2].t"
+= "t.vtree_test.in.d[1].d[0]" "t.vtree_test.OR2_tf[1].b"
+= "t.vtree_test.in.d[1].d[0]" "t.vtree_test.in.d[1].f"
+= "t.vtree_test.in.d[1].d[1]" "t.vtree_test.OR2_tf[1].a"
+= "t.vtree_test.in.d[1].d[1]" "t.vtree_test.in.d[1].t"
+= "t.vtree_test.in.d[0].d[0]" "t.vtree_test.OR2_tf[0].b"
+= "t.vtree_test.in.d[0].d[0]" "t.vtree_test.in.d[0].f"
+= "t.vtree_test.in.d[0].d[1]" "t.vtree_test.OR2_tf[0].a"
+= "t.vtree_test.in.d[0].d[1]" "t.vtree_test.in.d[0].t"
+= "Vdd" "t.vtree_test.supply.vdd"
+= "GND" "t.vtree_test.supply.vss"
+= "t._in.d[0].d[0]" "t._in.d[0].f"
+= "t._in.d[0].d[1]" "t._in.d[0].t"
+= "t._in.d[1].d[0]" "t._in.d[1].f"
+= "t._in.d[1].d[1]" "t._in.d[1].t"
+= "t._in.d[2].d[0]" "t._in.d[2].f"
+= "t._in.d[2].d[1]" "t._in.d[2].t"
+= "t._in.d[3].d[0]" "t._in.d[3].f"
+= "t._in.d[3].d[1]" "t._in.d[3].t"
+= "t._in.d[4].d[0]" "t._in.d[4].f"
+= "t._in.d[4].d[1]" "t._in.d[4].t"
+= "t._in.d[4].d[0]" "t._in.d[4].f"
+= "t._in.d[4].d[1]" "t._in.d[4].t"
+= "t._in.d[3].d[0]" "t._in.d[3].f"
+= "t._in.d[3].d[1]" "t._in.d[3].t"
+= "t._in.d[2].d[0]" "t._in.d[2].f"
+= "t._in.d[2].d[1]" "t._in.d[2].t"
+= "t._in.d[1].d[0]" "t._in.d[1].f"
+= "t._in.d[1].d[1]" "t._in.d[1].t"
+= "t._in.d[0].d[0]" "t._in.d[0].f"
+= "t._in.d[0].d[1]" "t._in.d[0].t"
+= "t._in.d[0].f" "t.vtree_test.in.d[0].f"
+= "t._in.d[0].t" "t.vtree_test.in.d[0].t"
+= "t._in.d[0].d[0]" "t.vtree_test.in.d[0].d[0]"
+= "t._in.d[0].d[1]" "t.vtree_test.in.d[0].d[1]"
+= "t._in.d[1].f" "t.vtree_test.in.d[1].f"
+= "t._in.d[1].t" "t.vtree_test.in.d[1].t"
+= "t._in.d[1].d[0]" "t.vtree_test.in.d[1].d[0]"
+= "t._in.d[1].d[1]" "t.vtree_test.in.d[1].d[1]"
+= "t._in.d[2].f" "t.vtree_test.in.d[2].f"
+= "t._in.d[2].t" "t.vtree_test.in.d[2].t"
+= "t._in.d[2].d[0]" "t.vtree_test.in.d[2].d[0]"
+= "t._in.d[2].d[1]" "t.vtree_test.in.d[2].d[1]"
+= "t._in.d[3].f" "t.vtree_test.in.d[3].f"
+= "t._in.d[3].t" "t.vtree_test.in.d[3].t"
+= "t._in.d[3].d[0]" "t.vtree_test.in.d[3].d[0]"
+= "t._in.d[3].d[1]" "t.vtree_test.in.d[3].d[1]"
+= "t._in.d[4].f" "t.vtree_test.in.d[4].f"
+= "t._in.d[4].t" "t.vtree_test.in.d[4].t"
+= "t._in.d[4].d[0]" "t.vtree_test.in.d[4].d[0]"
+= "t._in.d[4].d[1]" "t.vtree_test.in.d[4].d[1]"
+= "t.out" "t.vtree_test.out"
+= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
+= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
+= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
+= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
+= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
+= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
+= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
+= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
+= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
+= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
+= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
+= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
+= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
+= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
+= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
+= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
+= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
+= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
+= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
+= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
+= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
+= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
+= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
+= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
+= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
+= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
+= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
+= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
+= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
+= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
+= "t.in.d.d[0].f" "t._in.d[0].f"
+= "t.in.d.d[0].t" "t._in.d[0].t"
+= "t.in.d.d[0].d[0]" "t._in.d[0].d[0]"
+= "t.in.d.d[0].d[1]" "t._in.d[0].d[1]"
+= "t.in.d.d[1].f" "t._in.d[1].f"
+= "t.in.d.d[1].t" "t._in.d[1].t"
+= "t.in.d.d[1].d[0]" "t._in.d[1].d[0]"
+= "t.in.d.d[1].d[1]" "t._in.d[1].d[1]"
+= "t.in.d.d[2].f" "t._in.d[2].f"
+= "t.in.d.d[2].t" "t._in.d[2].t"
+= "t.in.d.d[2].d[0]" "t._in.d[2].d[0]"
+= "t.in.d.d[2].d[1]" "t._in.d[2].d[1]"
+= "t.in.d.d[3].f" "t._in.d[3].f"
+= "t.in.d.d[3].t" "t._in.d[3].t"
+= "t.in.d.d[3].d[0]" "t._in.d[3].d[0]"
+= "t.in.d.d[3].d[1]" "t._in.d[3].d[1]"
+= "t.in.d.d[4].f" "t._in.d[4].f"
+= "t.in.d.d[4].t" "t._in.d[4].t"
+= "t.in.d.d[4].d[0]" "t._in.d[4].d[0]"
+= "t.in.d.d[4].d[1]" "t._in.d[4].d[1]"
+= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
+= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
+= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
+= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
+= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
+= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
+= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
+= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
+= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
+= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"

test/unit_tests/vtree_5/test.act

@@ -0,0 +1,49 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/cell_lib_async.act";
+import "../../dataflow_neuro/cell_lib_std.act";
+import "../../dataflow_neuro/treegates.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/coders.act";
+import globals;
+import std::channel;
+open std::channel;
+open tmpl::dataflow_neuro;
+
+defproc vtree_5 (avMx1of2?<5> in; bool! out){
+
+    Mx1of2?<5> _in;
+    (i:5:_in.d[i] = in.d.d[i];)
+    vtree<5> vtree_test(.in=_in, .out=out);
+    vtree_test.supply.vss = GND;
+    vtree_test.supply.vdd = Vdd;
+
+}
+
+vtree_5 t;

test/unit_tests/vtree_5/test.prsim

@@ -0,0 +1,11 @@
+watchall
+system "echo '[0] starting test true high'"
+set-qdi-channel-neutral "t.in" 5
+cycle
+mode run
+assert t.out 0
+set-qdi-channel-valid "t.in" 5 3
+cycle
+mode run
+assert t.out 1
+system "echo '[1] cleaning input'"