continued registers.c

dataflow_neuro/registers.act

@@ -71,7 +71,7 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power s
     BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
     sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
     // Creating the different flip flop arrays
-    bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw];
+    bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw],_clock_buffer_out[_nw*wl];
     andtree<log_nw> atree[_nw];
     AND2_X1 and_encoder[_nw];
     sigbuf<wl> clock_buffer[_nw];
@@ -98,7 +98,16 @@ defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power s
         and_encoder[_word_idx].vss = supply.vss;
         clock_buffer[_word_idx].in = _clock_word_temp[_word_idx];
         clock_buffer[_word_idx].supply = supply;
-
+        // Describing all the FF and their connection
+        (_bit_idx:wl:
+            clock_buffer[_word_idx].out[_bit_idx] = _clock_buffer_out[_bit_idx*(1+_word_idx)];
+            // ff[_bit_idx*(1+_word_idx)].clk = _clock_buffer_out[_bit_idx*(1+_word_idx)];
+            // ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw].t;
+            // ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
+            // ff[_bit_idx*(1+_word_idx)].reset_B = _reset_mem_BXX[_bit_idx*(1+_word_idx)];
+            // ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
+            // ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
+        )
     )
 }
 }}

test/unit_tests/register_write/run/test.prs

@@ -282,7 +282,6 @@
 = "t.registers.clk_X.supply.vdd" "t.registers.clk_X.buf1.vdd"
 = "t.registers.clk_X.supply.vss" "t.registers.clk_X.buf1.vss"
 = "t.registers.clk_X.out" "t.registers.clk_X.buf1.y"
-= "t.registers.clk_X.out" "t.registers.clk_X._out"
 = "t.registers.clk_X.in" "t.registers.clk_X.buf1.a"
 = "t.registers.in.d.d[0].d[0]" "t.registers.in.d.d[0].f"
 = "t.registers.in.d.d[0].d[1]" "t.registers.in.d.d[0].t"
@@ -659,7 +658,6 @@
 = "t.registers.val_input_X.supply.vdd" "t.registers.val_input_X.buf1.vdd"
 = "t.registers.val_input_X.supply.vss" "t.registers.val_input_X.buf1.vss"
 = "t.registers.val_input_X.out" "t.registers.val_input_X.buf1.y"
-= "t.registers.val_input_X.out" "t.registers.val_input_X._out"
 = "t.registers.val_input_X.in" "t.registers.val_input_X.buf1.a"
 "t.registers.ack_input_X.buf1.a"->"t.registers.ack_input_X.buf1._y"-
 ~("t.registers.ack_input_X.buf1.a")->"t.registers.ack_input_X.buf1._y"+
@@ -668,8 +666,31 @@
 = "t.registers.ack_input_X.supply.vdd" "t.registers.ack_input_X.buf1.vdd"
 = "t.registers.ack_input_X.supply.vss" "t.registers.ack_input_X.buf1.vss"
 = "t.registers.ack_input_X.out" "t.registers.ack_input_X.buf1.y"
-= "t.registers.ack_input_X.out" "t.registers.ack_input_X._out"
 = "t.registers.ack_input_X.in" "t.registers.ack_input_X.buf1.a"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[8]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[7].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[7].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[7]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[6].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[6].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[6]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[5].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[5].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[5]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[4].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[4].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[4]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[3].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[3].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[3]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[2].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[2].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[2]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[1].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[1].out[0]"
+= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[0].out[1]"
+= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[0].out[0]"
 ~"t.registers.val_input.ct.C2Els[0].c1"&~"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"+
 "t.registers.val_input.ct.C2Els[0].c1"&"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"-
 "t.registers.val_input.ct.C2Els[0]._y"->"t.registers.val_input.ct.C2Els[0].y"-
@@ -957,9 +978,6 @@
 = "t.registers.atree[7].in[1]" "t.registers.atree[7].tmp[1]"
 = "t.registers.atree[7].out" "t.registers.atree[7].and2s[0].y"
 = "t.registers.atree[7].out" "t.registers.atree[7].tmp[2]"
-= "t.registers._in_v_temp" "t.registers.clk_dly.in"
-= "t.registers._in_v_temp" "t.registers.val_input_X.in"
-= "t.registers._in_v_temp" "t.registers.val_input.out"
 "t.registers.clock_buffer[0].buf1.a"->"t.registers.clock_buffer[0].buf1._y"-
 ~("t.registers.clock_buffer[0].buf1.a")->"t.registers.clock_buffer[0].buf1._y"+
 "t.registers.clock_buffer[0].buf1._y"->"t.registers.clock_buffer[0].buf1.y"-
@@ -1032,14 +1050,9 @@
 = "t.registers.clock_buffer[7].out[0]" "t.registers.clock_buffer[7].out[1]"
 = "t.registers.clock_buffer[7].out[0]" "t.registers.clock_buffer[7].buf1.y"
 = "t.registers.clock_buffer[7].in" "t.registers.clock_buffer[7].buf1.a"
-= "t.registers.clock_buffer[7].out[0]" "t.registers.clock_buffer[7].out[1]"
-= "t.registers.clock_buffer[6].out[0]" "t.registers.clock_buffer[6].out[1]"
-= "t.registers.clock_buffer[5].out[0]" "t.registers.clock_buffer[5].out[1]"
-= "t.registers.clock_buffer[4].out[0]" "t.registers.clock_buffer[4].out[1]"
-= "t.registers.clock_buffer[3].out[0]" "t.registers.clock_buffer[3].out[1]"
-= "t.registers.clock_buffer[2].out[0]" "t.registers.clock_buffer[2].out[1]"
-= "t.registers.clock_buffer[1].out[0]" "t.registers.clock_buffer[1].out[1]"
-= "t.registers.clock_buffer[0].out[0]" "t.registers.clock_buffer[0].out[1]"
+= "t.registers._in_v_temp" "t.registers.clk_dly.in"
+= "t.registers._in_v_temp" "t.registers.val_input_X.in"
+= "t.registers._in_v_temp" "t.registers.val_input.out"
 = "t.registers._clock" "t.registers.and_encoder[7].b"
 = "t.registers._clock" "t.registers.and_encoder[6].b"
 = "t.registers._clock" "t.registers.and_encoder[5].b"

test/unit_tests/register_write/test.prsim

@@ -36,6 +36,8 @@ assert t.registers._out_encoder[3] 0
 set-qdi-channel-neutral "t.in" 5
 cycle
 assert t.registers._clock 0
+assert t.registers.ff[0].q 1
+assert t.registers.ff[1].q 1
 system "echo '[3] clock checked'"