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5 Commits
a12b77edd5
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ad318259a5
| Author | SHA1 | Date | |
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ad318259a5 | ||
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932e967f3d | ||
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cf66c0e665 | ||
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aa67bd6168 | ||
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78a8f72d25 |
@ -51,64 +51,62 @@ namespace tmpl {
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// - the last wl the word to write
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// data -> the data saved in the flip flop, sized wl x nw
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export template<pint log_nw,wl,N_dly_cfg>
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defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool reset_B,reset_mem_B){
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defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
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bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
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pint _nw = 2<<log_nw;
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//Validation of the input
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Mx1of2<1+log_nw+wl> in_temp;
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(i:1+log_nw+wl:in_temp.d[i] = in.d.d[i];)
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vtree<1+log_nw+wl> val_input(.in = in_temp,.out = _in_v_temp, .supply = supply);
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Mx1of2<1+log_nw+wl> _in_temp;
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(i:1+log_nw+wl:_in_temp.d[i] = in.d.d[i];)
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vtree<1+log_nw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
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sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
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in.v = _in_v_temp;
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// Generation of the clock pulse
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delayprog<N_dly_cfg> dly(.in = _in_v_temp, .s = _clock_temp, .supply = supply);
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sigbuf_1output<4> val_input_X(.in = _clock_temp,.out = _clock,.supply = supply);
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// Generation of the fake clock pulse
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delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
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sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
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// Sending back to the ackowledge
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delayprog<N_dly_cfg> dly(.in = _clock, .s = _in_a_temp, .supply = supply);
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sigbuf_1output<4> val_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
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delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
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sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
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//Reset Buffers
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bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[_nw*w];
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BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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BUF_X1 reset_buf(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
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sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_BXX_mem,.vdd=supply.vdd,.vss=supply.vss);
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bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[_nw*wl];
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BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
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sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
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// Creating the different flip flop arrays
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bool _nw = 2<<log_nw;
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bool _word_idx = 0;
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bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw];
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bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw],_clock_buffer_out[_nw*wl];
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andtree<log_nw> atree[_nw];
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AND2_X1 and_encoder[_nw];
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sigbuf<wl> clock_buffer;
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sigbuf<wl> clock_buffer[_nw];
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DFFQ_R_X1 ff[_nw*wl];
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(k:_nw:atree_x[k].supply = supply;)
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pint _bitval;
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(k:_nw:atree[k].supply = supply;)
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(_word_idx:_nw:
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// Decoding the bit pattern to understand which word we are looking at
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(pin_idx:log_nw:
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bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
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[bitval = 1 ->
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atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].t;
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[] bitval = 0 ->
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atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+1].f;
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[]bitval >= 2 -> {false : "fuck"};
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_bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
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[_bitval = 1 ->
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atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
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[] _bitval = 0 ->
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atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
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[]_bitval >= 2 -> {false : "fuck"};
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]
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)
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// Activating the fake clock for the right word
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atree_x[_word_idx].out = _out_encoder[_word_idx];
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atree[_word_idx].out = _out_encoder[_word_idx];
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and_encoder[_word_idx].a = _out_encoder[_word_idx];
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and_encoder[_word_idx].b = _clock;
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and_encoder[_word_idx].y = _clock_word_temp[_word_idx];
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and_encoder[_word_idx].vdd = supply.vdd;
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and_encoder[_word_idx].vss = supply.vss;
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clock_buffer[_word_idx].in = _clock_word_temp[_word_idx];
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clock_buffer[_word_idx].out = _clock_word[_word_idx];
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clock_buffer[_word_idx].vdd = supply.vdd;
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clock_buffer[_word_idx].vss = supply.vss;
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clock_buffer[_word_idx].supply = supply;
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// Describing all the FF and their connection
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(_bit_idx:wl:
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ff[_bit_idx*(1+_word_idx)].clk = _clock_word[_word_idx];
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ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw];
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ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
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ff[_bit_idx*(1+_word_idx)].reset_B = reset_mem_BXX[_bit_idx*(1+_word_idx)];
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ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
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ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
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clock_buffer[_word_idx].out[_bit_idx] = _clock_buffer_out[_bit_idx*(1+_word_idx)];
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// ff[_bit_idx*(1+_word_idx)].clk = _clock_buffer_out[_bit_idx*(1+_word_idx)];
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// ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw].t;
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// ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
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// ff[_bit_idx*(1+_word_idx)].reset_B = _reset_mem_BXX[_bit_idx*(1+_word_idx)];
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// ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
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// ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
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)
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)
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}
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298
test/unit_tests/register_write/run/prsim.out
Normal file
298
test/unit_tests/register_write/run/prsim.out
Normal file
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@ -30,13 +30,13 @@ import "../../dataflow_neuro/registers.act";
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import globals;
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open tmpl::dataflow_neuro;
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defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]){
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// 2 bits encoder, 2 bits long words, 2 delays????
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defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]; bool? dly_cfg[2]){
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register_rw<2,2,2> registers(.in=in,.data = data);
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//Low active Reset
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bool _reset_B;
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power supply;
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power _supply;
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prs {
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Reset => _reset_B-
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}
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@ -44,7 +44,8 @@ defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]){
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_supply.vss = GND;
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_supply.vdd = Vdd;
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registers.reset_B = _reset_B;
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registers.reset_B_mem = _reset_B;
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registers.reset_mem_B = _reset_B;
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registers.dly_cfg = dly_cfg;
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}
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@ -1,8 +1,43 @@
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watchall
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system "echo '[0] start test'"
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set Reset 1
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set-qdi-channel-neutral "t.in" 2
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set-qdi-channel-neutral "t.in" 5
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set t.data[0].d[0] 0
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set t.data[0].d[1] 0
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set t.data[1].d[0] 0
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set t.data[1].d[1] 0
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cycle
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status X
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mode run
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assert-qdi-channel-neutral "t.in" 5
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assert t.data[0].d[0] 0
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assert t.data[0].d[1] 0
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assert t.data[1].d[0] 0
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assert t.data[1].d[1] 0
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set Reset 0
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cycle
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system "echo '[1] reset completed'"
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# Set delay config lines
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set t.dly_cfg[0] 1
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set t.dly_cfg[1] 1
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cycle
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assert-qdi-channel-neutral "t.in" 5
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system "echo '[2] delay line set'"
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set-qdi-channel-valid "t.in" 5 3
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cycle
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assert-qdi-channel-valid "t.in" 5 3
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assert t.registers._clock 1
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assert t.registers._out_encoder[0] 1
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assert t.registers._out_encoder[1] 0
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assert t.registers._out_encoder[2] 0
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assert t.registers._out_encoder[3] 0
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set-qdi-channel-neutral "t.in" 5
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cycle
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assert t.registers._clock 0
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assert t.registers.ff[0].q 1
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assert t.registers.ff[1].q 1
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system "echo '[3] clock checked'"
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50
test/unit_tests/vtree_5/run/prsim.out
Normal file
50
test/unit_tests/vtree_5/run/prsim.out
Normal file
@ -0,0 +1,50 @@
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t._in.d[1].t t.vtree_test.ct.in[2] t._in.d[2].f t._in.d[3].t t._in.d[3].f t.vtree_test.ct.C3Els[0]._y t.vtree_test.ct.in[0] t._in.d[4].f t._in.d[0].f t._in.d[4].t t._in.d[0].t t.out t._in.d[1].f t._in.d[2].t t.vtree_test.ct.in[3] t.vtree_test.ct.tmp[6] t.vtree_test.OR2_tf[3]._y t.vtree_test.ct.in[1] t.vtree_test.ct.in[4] t.vtree_test.OR2_tf[4]._y t.vtree_test.OR2_tf[0]._y t.vtree_test.ct.C2Els[1]._y t.vtree_test.ct.C2Els[0]._y t.vtree_test.ct.tmp[5] t.vtree_test.OR2_tf[2]._y t.vtree_test.OR2_tf[1]._y
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[0] starting test true high
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0 t._in.d[0].f : 0
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0 t._in.d[4].t : 0
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0 t._in.d[4].f : 0
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0 t._in.d[3].t : 0
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0 t._in.d[1].f : 0
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0 t._in.d[3].f : 0
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0 t._in.d[2].t : 0
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0 t._in.d[0].t : 0
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0 t._in.d[2].f : 0
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0 t._in.d[1].t : 0
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1 t.vtree_test.OR2_tf[4]._y : 1 [by t._in.d[4].f:=0]
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2 t.vtree_test.OR2_tf[2]._y : 1 [by t._in.d[2].f:=0]
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116 t.vtree_test.ct.in[2] : 0 [by t.vtree_test.OR2_tf[2]._y:=1]
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1138 t.vtree_test.ct.in[4] : 0 [by t.vtree_test.OR2_tf[4]._y:=1]
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4753 t.vtree_test.OR2_tf[1]._y : 1 [by t._in.d[1].t:=0]
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7092 t.vtree_test.OR2_tf[3]._y : 1 [by t._in.d[3].f:=0]
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8818 t.vtree_test.ct.in[3] : 0 [by t.vtree_test.OR2_tf[3]._y:=1]
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8857 t.vtree_test.ct.C3Els[0]._y : 1 [by t.vtree_test.ct.in[3]:=0]
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8872 t.vtree_test.ct.tmp[6] : 0 [by t.vtree_test.ct.C3Els[0]._y:=1]
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10467 t.vtree_test.OR2_tf[0]._y : 1 [by t._in.d[0].t:=0]
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10958 t.vtree_test.ct.in[0] : 0 [by t.vtree_test.OR2_tf[0]._y:=1]
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70119 t.vtree_test.ct.in[1] : 0 [by t.vtree_test.OR2_tf[1]._y:=1]
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70132 t.vtree_test.ct.C2Els[0]._y : 1 [by t.vtree_test.ct.in[1]:=0]
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70172 t.vtree_test.ct.tmp[5] : 0 [by t.vtree_test.ct.C2Els[0]._y:=1]
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70587 t.vtree_test.ct.C2Els[1]._y : 1 [by t.vtree_test.ct.tmp[5]:=0]
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70607 t.out : 0 [by t.vtree_test.ct.C2Els[1]._y:=1]
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70607 t._in.d[0].t : 1
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70607 t._in.d[4].f : 1
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70607 t._in.d[2].f : 1
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70607 t._in.d[1].t : 1
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70607 t._in.d[3].f : 1
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70623 t.vtree_test.OR2_tf[2]._y : 0 [by t._in.d[2].f:=1]
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70627 t.vtree_test.ct.in[2] : 1 [by t.vtree_test.OR2_tf[2]._y:=0]
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70654 t.vtree_test.OR2_tf[4]._y : 0 [by t._in.d[4].f:=1]
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76668 t.vtree_test.OR2_tf[0]._y : 0 [by t._in.d[0].t:=1]
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76683 t.vtree_test.ct.in[0] : 1 [by t.vtree_test.OR2_tf[0]._y:=0]
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79783 t.vtree_test.ct.in[4] : 1 [by t.vtree_test.OR2_tf[4]._y:=0]
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84331 t.vtree_test.OR2_tf[3]._y : 0 [by t._in.d[3].f:=1]
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114705 t.vtree_test.OR2_tf[1]._y : 0 [by t._in.d[1].t:=1]
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127579 t.vtree_test.ct.in[3] : 1 [by t.vtree_test.OR2_tf[3]._y:=0]
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127634 t.vtree_test.ct.C3Els[0]._y : 0 [by t.vtree_test.ct.in[3]:=1]
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151636 t.vtree_test.ct.in[1] : 1 [by t.vtree_test.OR2_tf[1]._y:=0]
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179287 t.vtree_test.ct.tmp[6] : 1 [by t.vtree_test.ct.C3Els[0]._y:=0]
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181416 t.vtree_test.ct.C2Els[0]._y : 0 [by t.vtree_test.ct.in[1]:=1]
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195265 t.vtree_test.ct.tmp[5] : 1 [by t.vtree_test.ct.C2Els[0]._y:=0]
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220077 t.vtree_test.ct.C2Els[1]._y : 0 [by t.vtree_test.ct.tmp[5]:=1]
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234420 t.out : 1 [by t.vtree_test.ct.C2Els[1]._y:=0]
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[1] cleaning input
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218
test/unit_tests/vtree_5/run/test.prs
Normal file
218
test/unit_tests/vtree_5/run/test.prs
Normal file
@ -0,0 +1,218 @@
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= "GND" "GND"
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= "Vdd" "Vdd"
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= "Reset" "Reset"
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~"t.vtree_test.ct.C2Els[0].c1"&~"t.vtree_test.ct.C2Els[0].c2"->"t.vtree_test.ct.C2Els[0]._y"+
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"t.vtree_test.ct.C2Els[0].c1"&"t.vtree_test.ct.C2Els[0].c2"->"t.vtree_test.ct.C2Els[0]._y"-
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"t.vtree_test.ct.C2Els[0]._y"->"t.vtree_test.ct.C2Els[0].y"-
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~("t.vtree_test.ct.C2Els[0]._y")->"t.vtree_test.ct.C2Els[0].y"+
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~"t.vtree_test.ct.C2Els[1].c1"&~"t.vtree_test.ct.C2Els[1].c2"->"t.vtree_test.ct.C2Els[1]._y"+
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"t.vtree_test.ct.C2Els[1].c1"&"t.vtree_test.ct.C2Els[1].c2"->"t.vtree_test.ct.C2Els[1]._y"-
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"t.vtree_test.ct.C2Els[1]._y"->"t.vtree_test.ct.C2Els[1].y"-
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~("t.vtree_test.ct.C2Els[1]._y")->"t.vtree_test.ct.C2Els[1].y"+
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~"t.vtree_test.ct.C3Els[0].c1"&~"t.vtree_test.ct.C3Els[0].c2"&~"t.vtree_test.ct.C3Els[0].c3"->"t.vtree_test.ct.C3Els[0]._y"+
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"t.vtree_test.ct.C3Els[0].c1"&"t.vtree_test.ct.C3Els[0].c2"&"t.vtree_test.ct.C3Els[0].c3"->"t.vtree_test.ct.C3Els[0]._y"-
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"t.vtree_test.ct.C3Els[0]._y"->"t.vtree_test.ct.C3Els[0].y"-
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~("t.vtree_test.ct.C3Els[0]._y")->"t.vtree_test.ct.C3Els[0].y"+
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= "t.vtree_test.ct.tmp[5]" "t.vtree_test.ct.C2Els[1].c1"
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= "t.vtree_test.ct.tmp[5]" "t.vtree_test.ct.C2Els[0].y"
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= "t.vtree_test.ct.tmp[6]" "t.vtree_test.ct.C2Els[1].c2"
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= "t.vtree_test.ct.tmp[6]" "t.vtree_test.ct.C3Els[0].y"
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= "t.vtree_test.ct.supply.vdd" "t.vtree_test.ct.C3Els[0].vdd"
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= "t.vtree_test.ct.supply.vdd" "t.vtree_test.ct.C2Els[1].vdd"
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= "t.vtree_test.ct.supply.vdd" "t.vtree_test.ct.C2Els[0].vdd"
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= "t.vtree_test.ct.supply.vss" "t.vtree_test.ct.C3Els[0].vss"
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= "t.vtree_test.ct.supply.vss" "t.vtree_test.ct.C2Els[1].vss"
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= "t.vtree_test.ct.supply.vss" "t.vtree_test.ct.C2Els[0].vss"
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= "t.vtree_test.ct.in[0]" "t.vtree_test.ct.C2Els[0].c1"
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= "t.vtree_test.ct.in[0]" "t.vtree_test.ct.tmp[0]"
|
||||
= "t.vtree_test.ct.in[1]" "t.vtree_test.ct.C2Els[0].c2"
|
||||
= "t.vtree_test.ct.in[1]" "t.vtree_test.ct.tmp[1]"
|
||||
= "t.vtree_test.ct.in[2]" "t.vtree_test.ct.C3Els[0].c1"
|
||||
= "t.vtree_test.ct.in[2]" "t.vtree_test.ct.tmp[2]"
|
||||
= "t.vtree_test.ct.in[3]" "t.vtree_test.ct.C3Els[0].c2"
|
||||
= "t.vtree_test.ct.in[3]" "t.vtree_test.ct.tmp[3]"
|
||||
= "t.vtree_test.ct.in[4]" "t.vtree_test.ct.C3Els[0].c3"
|
||||
= "t.vtree_test.ct.in[4]" "t.vtree_test.ct.tmp[4]"
|
||||
= "t.vtree_test.ct.out" "t.vtree_test.ct.C2Els[1].y"
|
||||
= "t.vtree_test.ct.out" "t.vtree_test.ct.tmp[7]"
|
||||
= "t.vtree_test.ct.in[0]" "t.vtree_test.OR2_tf[0].y"
|
||||
= "t.vtree_test.ct.in[1]" "t.vtree_test.OR2_tf[1].y"
|
||||
= "t.vtree_test.ct.in[2]" "t.vtree_test.OR2_tf[2].y"
|
||||
= "t.vtree_test.ct.in[3]" "t.vtree_test.OR2_tf[3].y"
|
||||
= "t.vtree_test.ct.in[4]" "t.vtree_test.OR2_tf[4].y"
|
||||
"t.vtree_test.OR2_tf[0].a"|"t.vtree_test.OR2_tf[0].b"->"t.vtree_test.OR2_tf[0]._y"-
|
||||
~("t.vtree_test.OR2_tf[0].a"|"t.vtree_test.OR2_tf[0].b")->"t.vtree_test.OR2_tf[0]._y"+
|
||||
"t.vtree_test.OR2_tf[0]._y"->"t.vtree_test.OR2_tf[0].y"-
|
||||
~("t.vtree_test.OR2_tf[0]._y")->"t.vtree_test.OR2_tf[0].y"+
|
||||
"t.vtree_test.OR2_tf[1].a"|"t.vtree_test.OR2_tf[1].b"->"t.vtree_test.OR2_tf[1]._y"-
|
||||
~("t.vtree_test.OR2_tf[1].a"|"t.vtree_test.OR2_tf[1].b")->"t.vtree_test.OR2_tf[1]._y"+
|
||||
"t.vtree_test.OR2_tf[1]._y"->"t.vtree_test.OR2_tf[1].y"-
|
||||
~("t.vtree_test.OR2_tf[1]._y")->"t.vtree_test.OR2_tf[1].y"+
|
||||
"t.vtree_test.OR2_tf[2].a"|"t.vtree_test.OR2_tf[2].b"->"t.vtree_test.OR2_tf[2]._y"-
|
||||
~("t.vtree_test.OR2_tf[2].a"|"t.vtree_test.OR2_tf[2].b")->"t.vtree_test.OR2_tf[2]._y"+
|
||||
"t.vtree_test.OR2_tf[2]._y"->"t.vtree_test.OR2_tf[2].y"-
|
||||
~("t.vtree_test.OR2_tf[2]._y")->"t.vtree_test.OR2_tf[2].y"+
|
||||
"t.vtree_test.OR2_tf[3].a"|"t.vtree_test.OR2_tf[3].b"->"t.vtree_test.OR2_tf[3]._y"-
|
||||
~("t.vtree_test.OR2_tf[3].a"|"t.vtree_test.OR2_tf[3].b")->"t.vtree_test.OR2_tf[3]._y"+
|
||||
"t.vtree_test.OR2_tf[3]._y"->"t.vtree_test.OR2_tf[3].y"-
|
||||
~("t.vtree_test.OR2_tf[3]._y")->"t.vtree_test.OR2_tf[3].y"+
|
||||
"t.vtree_test.OR2_tf[4].a"|"t.vtree_test.OR2_tf[4].b"->"t.vtree_test.OR2_tf[4]._y"-
|
||||
~("t.vtree_test.OR2_tf[4].a"|"t.vtree_test.OR2_tf[4].b")->"t.vtree_test.OR2_tf[4]._y"+
|
||||
"t.vtree_test.OR2_tf[4]._y"->"t.vtree_test.OR2_tf[4].y"-
|
||||
~("t.vtree_test.OR2_tf[4]._y")->"t.vtree_test.OR2_tf[4].y"+
|
||||
= "t.vtree_test.supply.vss" "t.vtree_test.ct.supply.vss"
|
||||
= "t.vtree_test.supply.vdd" "t.vtree_test.ct.supply.vdd"
|
||||
= "t.vtree_test.supply.vdd" "t.vtree_test.OR2_tf[4].vdd"
|
||||
= "t.vtree_test.supply.vdd" "t.vtree_test.OR2_tf[3].vdd"
|
||||
= "t.vtree_test.supply.vdd" "t.vtree_test.OR2_tf[2].vdd"
|
||||
= "t.vtree_test.supply.vdd" "t.vtree_test.OR2_tf[1].vdd"
|
||||
= "t.vtree_test.supply.vdd" "t.vtree_test.OR2_tf[0].vdd"
|
||||
= "t.vtree_test.supply.vss" "t.vtree_test.OR2_tf[4].vss"
|
||||
= "t.vtree_test.supply.vss" "t.vtree_test.OR2_tf[3].vss"
|
||||
= "t.vtree_test.supply.vss" "t.vtree_test.OR2_tf[2].vss"
|
||||
= "t.vtree_test.supply.vss" "t.vtree_test.OR2_tf[1].vss"
|
||||
= "t.vtree_test.supply.vss" "t.vtree_test.OR2_tf[0].vss"
|
||||
= "t.vtree_test.out" "t.vtree_test.ct.out"
|
||||
= "t.vtree_test.in.d[0].d[0]" "t.vtree_test.in.d[0].f"
|
||||
= "t.vtree_test.in.d[0].d[1]" "t.vtree_test.in.d[0].t"
|
||||
= "t.vtree_test.in.d[1].d[0]" "t.vtree_test.in.d[1].f"
|
||||
= "t.vtree_test.in.d[1].d[1]" "t.vtree_test.in.d[1].t"
|
||||
= "t.vtree_test.in.d[2].d[0]" "t.vtree_test.in.d[2].f"
|
||||
= "t.vtree_test.in.d[2].d[1]" "t.vtree_test.in.d[2].t"
|
||||
= "t.vtree_test.in.d[3].d[0]" "t.vtree_test.in.d[3].f"
|
||||
= "t.vtree_test.in.d[3].d[1]" "t.vtree_test.in.d[3].t"
|
||||
= "t.vtree_test.in.d[4].d[0]" "t.vtree_test.in.d[4].f"
|
||||
= "t.vtree_test.in.d[4].d[1]" "t.vtree_test.in.d[4].t"
|
||||
= "t.vtree_test.in.d[4].d[0]" "t.vtree_test.in.d[4].f"
|
||||
= "t.vtree_test.in.d[4].d[1]" "t.vtree_test.in.d[4].t"
|
||||
= "t.vtree_test.in.d[3].d[0]" "t.vtree_test.in.d[3].f"
|
||||
= "t.vtree_test.in.d[3].d[1]" "t.vtree_test.in.d[3].t"
|
||||
= "t.vtree_test.in.d[2].d[0]" "t.vtree_test.in.d[2].f"
|
||||
= "t.vtree_test.in.d[2].d[1]" "t.vtree_test.in.d[2].t"
|
||||
= "t.vtree_test.in.d[1].d[0]" "t.vtree_test.in.d[1].f"
|
||||
= "t.vtree_test.in.d[1].d[1]" "t.vtree_test.in.d[1].t"
|
||||
= "t.vtree_test.in.d[0].d[0]" "t.vtree_test.in.d[0].f"
|
||||
= "t.vtree_test.in.d[0].d[1]" "t.vtree_test.in.d[0].t"
|
||||
= "t.vtree_test.in.d[4].d[0]" "t.vtree_test.OR2_tf[4].b"
|
||||
= "t.vtree_test.in.d[4].d[0]" "t.vtree_test.in.d[4].f"
|
||||
= "t.vtree_test.in.d[4].d[1]" "t.vtree_test.OR2_tf[4].a"
|
||||
= "t.vtree_test.in.d[4].d[1]" "t.vtree_test.in.d[4].t"
|
||||
= "t.vtree_test.in.d[3].d[0]" "t.vtree_test.OR2_tf[3].b"
|
||||
= "t.vtree_test.in.d[3].d[0]" "t.vtree_test.in.d[3].f"
|
||||
= "t.vtree_test.in.d[3].d[1]" "t.vtree_test.OR2_tf[3].a"
|
||||
= "t.vtree_test.in.d[3].d[1]" "t.vtree_test.in.d[3].t"
|
||||
= "t.vtree_test.in.d[2].d[0]" "t.vtree_test.OR2_tf[2].b"
|
||||
= "t.vtree_test.in.d[2].d[0]" "t.vtree_test.in.d[2].f"
|
||||
= "t.vtree_test.in.d[2].d[1]" "t.vtree_test.OR2_tf[2].a"
|
||||
= "t.vtree_test.in.d[2].d[1]" "t.vtree_test.in.d[2].t"
|
||||
= "t.vtree_test.in.d[1].d[0]" "t.vtree_test.OR2_tf[1].b"
|
||||
= "t.vtree_test.in.d[1].d[0]" "t.vtree_test.in.d[1].f"
|
||||
= "t.vtree_test.in.d[1].d[1]" "t.vtree_test.OR2_tf[1].a"
|
||||
= "t.vtree_test.in.d[1].d[1]" "t.vtree_test.in.d[1].t"
|
||||
= "t.vtree_test.in.d[0].d[0]" "t.vtree_test.OR2_tf[0].b"
|
||||
= "t.vtree_test.in.d[0].d[0]" "t.vtree_test.in.d[0].f"
|
||||
= "t.vtree_test.in.d[0].d[1]" "t.vtree_test.OR2_tf[0].a"
|
||||
= "t.vtree_test.in.d[0].d[1]" "t.vtree_test.in.d[0].t"
|
||||
= "Vdd" "t.vtree_test.supply.vdd"
|
||||
= "GND" "t.vtree_test.supply.vss"
|
||||
= "t._in.d[0].d[0]" "t._in.d[0].f"
|
||||
= "t._in.d[0].d[1]" "t._in.d[0].t"
|
||||
= "t._in.d[1].d[0]" "t._in.d[1].f"
|
||||
= "t._in.d[1].d[1]" "t._in.d[1].t"
|
||||
= "t._in.d[2].d[0]" "t._in.d[2].f"
|
||||
= "t._in.d[2].d[1]" "t._in.d[2].t"
|
||||
= "t._in.d[3].d[0]" "t._in.d[3].f"
|
||||
= "t._in.d[3].d[1]" "t._in.d[3].t"
|
||||
= "t._in.d[4].d[0]" "t._in.d[4].f"
|
||||
= "t._in.d[4].d[1]" "t._in.d[4].t"
|
||||
= "t._in.d[4].d[0]" "t._in.d[4].f"
|
||||
= "t._in.d[4].d[1]" "t._in.d[4].t"
|
||||
= "t._in.d[3].d[0]" "t._in.d[3].f"
|
||||
= "t._in.d[3].d[1]" "t._in.d[3].t"
|
||||
= "t._in.d[2].d[0]" "t._in.d[2].f"
|
||||
= "t._in.d[2].d[1]" "t._in.d[2].t"
|
||||
= "t._in.d[1].d[0]" "t._in.d[1].f"
|
||||
= "t._in.d[1].d[1]" "t._in.d[1].t"
|
||||
= "t._in.d[0].d[0]" "t._in.d[0].f"
|
||||
= "t._in.d[0].d[1]" "t._in.d[0].t"
|
||||
= "t._in.d[0].f" "t.vtree_test.in.d[0].f"
|
||||
= "t._in.d[0].t" "t.vtree_test.in.d[0].t"
|
||||
= "t._in.d[0].d[0]" "t.vtree_test.in.d[0].d[0]"
|
||||
= "t._in.d[0].d[1]" "t.vtree_test.in.d[0].d[1]"
|
||||
= "t._in.d[1].f" "t.vtree_test.in.d[1].f"
|
||||
= "t._in.d[1].t" "t.vtree_test.in.d[1].t"
|
||||
= "t._in.d[1].d[0]" "t.vtree_test.in.d[1].d[0]"
|
||||
= "t._in.d[1].d[1]" "t.vtree_test.in.d[1].d[1]"
|
||||
= "t._in.d[2].f" "t.vtree_test.in.d[2].f"
|
||||
= "t._in.d[2].t" "t.vtree_test.in.d[2].t"
|
||||
= "t._in.d[2].d[0]" "t.vtree_test.in.d[2].d[0]"
|
||||
= "t._in.d[2].d[1]" "t.vtree_test.in.d[2].d[1]"
|
||||
= "t._in.d[3].f" "t.vtree_test.in.d[3].f"
|
||||
= "t._in.d[3].t" "t.vtree_test.in.d[3].t"
|
||||
= "t._in.d[3].d[0]" "t.vtree_test.in.d[3].d[0]"
|
||||
= "t._in.d[3].d[1]" "t.vtree_test.in.d[3].d[1]"
|
||||
= "t._in.d[4].f" "t.vtree_test.in.d[4].f"
|
||||
= "t._in.d[4].t" "t.vtree_test.in.d[4].t"
|
||||
= "t._in.d[4].d[0]" "t.vtree_test.in.d[4].d[0]"
|
||||
= "t._in.d[4].d[1]" "t.vtree_test.in.d[4].d[1]"
|
||||
= "t.out" "t.vtree_test.out"
|
||||
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
|
||||
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
|
||||
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
|
||||
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
|
||||
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
|
||||
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
|
||||
= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
|
||||
= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
|
||||
= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
|
||||
= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
|
||||
= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
|
||||
= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
|
||||
= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
|
||||
= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
|
||||
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
|
||||
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
|
||||
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
|
||||
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
|
||||
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
|
||||
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
|
||||
= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
|
||||
= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
|
||||
= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
|
||||
= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
|
||||
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
|
||||
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
|
||||
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
|
||||
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
|
||||
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
|
||||
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
|
||||
= "t.in.d.d[0].f" "t._in.d[0].f"
|
||||
= "t.in.d.d[0].t" "t._in.d[0].t"
|
||||
= "t.in.d.d[0].d[0]" "t._in.d[0].d[0]"
|
||||
= "t.in.d.d[0].d[1]" "t._in.d[0].d[1]"
|
||||
= "t.in.d.d[1].f" "t._in.d[1].f"
|
||||
= "t.in.d.d[1].t" "t._in.d[1].t"
|
||||
= "t.in.d.d[1].d[0]" "t._in.d[1].d[0]"
|
||||
= "t.in.d.d[1].d[1]" "t._in.d[1].d[1]"
|
||||
= "t.in.d.d[2].f" "t._in.d[2].f"
|
||||
= "t.in.d.d[2].t" "t._in.d[2].t"
|
||||
= "t.in.d.d[2].d[0]" "t._in.d[2].d[0]"
|
||||
= "t.in.d.d[2].d[1]" "t._in.d[2].d[1]"
|
||||
= "t.in.d.d[3].f" "t._in.d[3].f"
|
||||
= "t.in.d.d[3].t" "t._in.d[3].t"
|
||||
= "t.in.d.d[3].d[0]" "t._in.d[3].d[0]"
|
||||
= "t.in.d.d[3].d[1]" "t._in.d[3].d[1]"
|
||||
= "t.in.d.d[4].f" "t._in.d[4].f"
|
||||
= "t.in.d.d[4].t" "t._in.d[4].t"
|
||||
= "t.in.d.d[4].d[0]" "t._in.d[4].d[0]"
|
||||
= "t.in.d.d[4].d[1]" "t._in.d[4].d[1]"
|
||||
= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
|
||||
= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
|
||||
= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
|
||||
= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
|
||||
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
|
||||
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
|
||||
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
|
||||
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
|
||||
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
|
||||
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
|
||||
49
test/unit_tests/vtree_5/test.act
Normal file
49
test/unit_tests/vtree_5/test.act
Normal file
@ -0,0 +1,49 @@
|
||||
/*************************************************************************
|
||||
*
|
||||
* This file is part of ACT dataflow neuro library.
|
||||
* It's the testing facility for cell_lib_std.act
|
||||
*
|
||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
||||
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
||||
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
||||
*
|
||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||
*
|
||||
* You may redistribute and modify this documentation and make products
|
||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||
* for applicable conditions.
|
||||
*
|
||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||
*
|
||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||
* these sources, You must maintain the Source Location visible in its
|
||||
* documentation.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
import "../../dataflow_neuro/cell_lib_async.act";
|
||||
import "../../dataflow_neuro/cell_lib_std.act";
|
||||
import "../../dataflow_neuro/treegates.act";
|
||||
import "../../dataflow_neuro/primitives.act";
|
||||
import "../../dataflow_neuro/coders.act";
|
||||
import globals;
|
||||
import std::channel;
|
||||
open std::channel;
|
||||
open tmpl::dataflow_neuro;
|
||||
|
||||
defproc vtree_5 (avMx1of2?<5> in; bool! out){
|
||||
|
||||
Mx1of2?<5> _in;
|
||||
(i:5:_in.d[i] = in.d.d[i];)
|
||||
vtree<5> vtree_test(.in=_in, .out=out);
|
||||
vtree_test.supply.vss = GND;
|
||||
vtree_test.supply.vdd = Vdd;
|
||||
|
||||
}
|
||||
|
||||
vtree_5 t;
|
||||
11
test/unit_tests/vtree_5/test.prsim
Normal file
11
test/unit_tests/vtree_5/test.prsim
Normal file
@ -0,0 +1,11 @@
|
||||
watchall
|
||||
system "echo '[0] starting test true high'"
|
||||
set-qdi-channel-neutral "t.in" 5
|
||||
cycle
|
||||
mode run
|
||||
assert t.out 0
|
||||
set-qdi-channel-valid "t.in" 5 3
|
||||
cycle
|
||||
mode run
|
||||
assert t.out 1
|
||||
system "echo '[1] cleaning input'"
|
||||
Loading…
Reference in New Issue
Block a user