Merge branch 'innovus_ready' into dev

Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev
added reg reset sig
2022-04-21 14:49:30 +02:00 · 2022-04-21 14:49:20 +02:00 · 2022-04-21 14:33:41 +02:00 · 2022-04-21 14:32:04 +02:00 · 2022-04-21 14:31:35 +02:00 · 2022-04-21 14:07:15 +02:00
12 changed files with 2971110 additions and 190350 deletions
--- a/dataflow_neuro/chips.act
+++ b/dataflow_neuro/chips.act
@@ -52,24 +52,35 @@ N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse o
 N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
 N_BUFFERS,
 N_LINE_PD_DLY, // Number of dummy delays to add line pull down
-// N_BD_DLY_CFG, N_BD_DLY_CFG2,
 REG_NCA, REG_NCW, REG_M>

 defproc texel_core (avMx1of2<N_IN> in, out;
    Mx1of2<REG_NCW> reg_data[REG_M];
-    a1of1 synapses[N_SYN_X * N_SYN_Y];
-    a1of1 neurons[N_NRN_X * N_NRN_Y];
-    
+
+    // Dummy synapses and neurons in the handshake blocks
+    // should be removed pre-innovus, else they are floating.
+    // a1of1 synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 neurons[N_NRN_X * N_NRN_Y];
+
+    // Synapse decoder stuff
+    // The analogue core and connects to these to replace the above synapses.
+    bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
+    bool? dec_ackB[N_SYN_X];
+    a1of1 syn_pu[N_SYN_X];
+
+    // Neuron encoder stuff
+    a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
+    a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
+
+    // Monitors and flags to/from core, and selected mon out.
    bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
    bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
    bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
    bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
    bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];

-    // bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
-    // bool? loopback_en;
    power supply;
-    bool? reset_B){
+    bool? reset_B, reset_reg_B){

    bool _reset_BX;
    BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
@@ -83,7 +94,7 @@ defproc texel_core (avMx1of2<N_IN> in, out;
    // Register
    fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
    register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
-        .supply = supply, .reset_B = _reset_BX);
+        .supply = supply, .reset_B = reset_reg_B);
    fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);


@@ -93,9 +104,11 @@ defproc texel_core (avMx1of2<N_IN> in, out;
    slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
    fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
    decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
-        .out = synapses,
        .hs_en = register.data[0].d[0].t, // Defaults to handshake disable
        .ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
+        .out_req_x = dec_req_x, .out_req_y = dec_req_y,
+        .to_pu = syn_pu,
+        .in_ackB_decoder = dec_ackB,
        .supply = supply, .reset_B = _reset_BX);
    INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG]; 
    (i:N_SYN_DLY_CFG:
@@ -103,21 +116,33 @@ defproc texel_core (avMx1of2<N_IN> in, out;
        dly_cfg_inverters[i].vdd = supply.vdd;
        dly_cfg_inverters[i].vss = supply.vss;
        decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
-    ) // This sexy hack means that the inverters are max delay throughout the register flush operations.
+    )
+
+    // Synapse handshake circuits, to be removed for innovus
+    // decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
+    //     .synapses = synapses,
+    //     .in_req_x = dec_req_x, .in_req_y = dec_req_y,
+    //     .to_pu = syn_pu,
+    //     .out_ackB_decoder = dec_ackB,
+    //     .supply = supply);

    // Neurons + encoder
    pint NC_NRN;
    NC_NRN = NC_NRN_X + NC_NRN_Y;
-    nrn_hs_2d_array<N_NRN_X,N_NRN_Y,N_LINE_PD_DLY> nrn_grid(.in = neurons,
-        .supply = supply, .reset_B = _reset_BX);
-    encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y> encoder(
-        .inx = nrn_grid.outx,
-        .iny = nrn_grid.outy,
-        .reset_B = _reset_BX, .supply = supply
-        );
+    encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
+        .inx = enc_inx, .iny = enc_iny,
+        .reset_B = _reset_BX, .supply = supply,
+        .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
    fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
        .reset_B = _reset_BX, .supply = supply);

+    // Neuron handshake circuits, to be removed for innovus
+    // nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
+    //     .outx = enc_inx, .outy = enc_iny,
+    //     .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
+    //     .supply = supply, .reset_B = _reset_BX);
+
+

    // Merge
    append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
@@ -131,7 +156,6 @@ defproc texel_core (avMx1of2<N_IN> in, out;
        .reset_B = _reset_BX, .supply = supply);


-
    // Neuron/synapse monitor targeters
    pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
    pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
@@ -262,8 +286,8 @@ REG_NCA, REG_NCW, REG_M>

 defproc texel_singlecore (bd<N_IN> in, out;
 	Mx1of2<REG_NCW> reg_data[REG_M];
-	a1of1 synapses[N_SYN_X * N_SYN_Y];
-	a1of1 neurons[N_NRN_X * N_NRN_Y];
+	// a1of1 synapses[N_SYN_X * N_SYN_Y];
+	// a1of1 neurons[N_NRN_X * N_NRN_Y];
    
    bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
    bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
@@ -300,8 +324,8 @@ defproc texel_singlecore (bd<N_IN> in, out;
    texel_core<N_IN,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
        core(.in = fifo_fork2core.out,
            .reg_data = reg_data,
-            .synapses = synapses,
-            .neurons = neurons,
+            // .synapses = synapses,
+            // .neurons = neurons,
            .nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
            .syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
            .syn_mon_AMZI = syn_mon_AMZI, .nrn_mon_AMZI = nrn_mon_AMZI,
@@ -346,9 +370,17 @@ REG_NCA, REG_NCW, REG_M>
 defproc texel_dualcore (bd<N_IN> in, out;

    Mx1of2<REG_NCW> c1_reg_data[REG_M];
-    a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
-    a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
+
+    // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
    
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+
    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
@@ -356,9 +388,17 @@ defproc texel_dualcore (bd<N_IN> in, out;
    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];

    Mx1of2<REG_NCW> c2_reg_data[REG_M];
-    a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
-    a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
+
+    // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
    
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+
    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
@@ -368,7 +408,7 @@ defproc texel_dualcore (bd<N_IN> in, out;
    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
    bool? loopback_en;
    power supply;
-    bool? reset_B){
+    bool? reset_B, reset_reg_B){

    // Reset buffers
    bool _reset_BX;
@@ -398,15 +438,23 @@ defproc texel_dualcore (bd<N_IN> in, out;
        core1(.in = fifo_dmx2core1.out,

            .reg_data = c1_reg_data,
-            .synapses = c1_synapses,
-            .neurons = c1_neurons,
+            // .synapses = c1_synapses,
+            // .neurons = c1_neurons,
+
+            .dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
+            .dec_ackB = c1_dec_ackB,
+            .syn_pu = c1_syn_pu,
+
+            .enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
+            .nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
+
            .nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
            .syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
            .syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
            .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
            .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,

-            .reset_B = _reset_BX,
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
            .supply = supply
            );

@@ -415,15 +463,23 @@ defproc texel_dualcore (bd<N_IN> in, out;
        core2(.in = fifo_dmx2core2.out,

            .reg_data = c2_reg_data,
-            .synapses = c2_synapses,
-            .neurons = c2_neurons,
+            // .synapses = c2_synapses,
+            // .neurons = c2_neurons,
+
+            .dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
+            .dec_ackB = c2_dec_ackB,
+            .syn_pu = c2_syn_pu,
+
+            .enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
+            .nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
+
            .nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
            .syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
            .syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
            .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
            .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,

-            .reset_B = _reset_BX,
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
            .supply = supply
            );

--- a/dataflow_neuro/coders.act
+++ b/dataflow_neuro/coders.act
@@ -382,6 +382,44 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po

 }

+
+/**
+ * Synapse handshaking stuff which exists in the core, and so will not be spawned in
+ * when innovusing all the periphery.
+ */
+export template<pint Nx, Ny>
+defproc decoder_2d_synapse_hs (bool? in_req_x[Nx], in_req_y[Ny]; a1of1 synapses[Nx*Ny];
+	bool out_ackB_decoder[Nx];
+	a1of1 to_pu[Nx];
+	power supply) {
+
+
+	// and grid for reqs into synapses
+	and_grid<Nx, Ny> _and_grid(.inx = in_req_x, .iny = in_req_y, .supply = supply);
+	(i:Nx*Ny: synapses[i].r = _and_grid.out[i];)
+	
+
+	// Pull DOWNs on the ackB lines by synapses (easier to invert).
+	A_2N_U_X4 ack_pulldowns[Nx*Ny];
+	pint index;
+	(i:Nx:
+		(j:Ny:
+			index = i + Nx*j;
+			ack_pulldowns[index].n1 = synapses[index].a;
+			ack_pulldowns[index].n2 = in_req_x[i]; // GET REFRHRESED IN CORE
+			ack_pulldowns[index].y = out_ackB_decoder[i];
+			ack_pulldowns[index].vss = supply.vss;
+			ack_pulldowns[index].vdd = supply.vdd;
+		)
+	)
+
+	// Connect the ackB lines together
+	(i:Nx: out_ackB_decoder[i] = to_pu[i].a;)
+
+	// Pipe req x lines down to the ackB pullups
+	(i:Nx: to_pu[i].r = in_req_x[i];)
+}
+
 /**
 * 2D decoder which uses either synapse handshaking, or just a delay.
 * Controlled by the "hs_en" (handshake_enable) config bit.
@@ -395,8 +433,12 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
 * Is needed in case there are instabilities while we fiddle with delays.
 */
 export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
-defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg[N_dly_cfg], hs_en, ack_disable,
-	reset_B; power supply) {
+defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[Ny]; bool? dly_cfg[N_dly_cfg], hs_en, ack_disable;
+	bool in_ackB_decoder[Nx]; // AckB lines back to the decoder for handshaking
+	a1of1 to_pu[Nx];
+	// bool out_ackB_pullups[Nx]; // AckB lines from the line end pull ups
+	// bool in_req_x_pullups[Nx]; // req x lines going to the line pull ups
+	bool? reset_B; power supply) {

 	bool _reset_BX[Nx];
 	sigbuf<Nx> reset_sb(.in = reset_B, .out = _reset_BX, .supply = supply);
@@ -416,13 +458,9 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	// sig buf for reqx lines, since they go to synapse pull down gates.
 	// Signals to the and-grid are buffered therein.
 	sigbuf_boolarray<Nx,15> d_dr_xX(.in = d_dr_x.out, .supply = supply);
-
-	// sigbuf<15> d_dr_xX[Nx]; // GET REFRESHED IN CORE
-	// (i:Nx:
-	// 	d_dr_xX[i].in = d_dr_x.out[i];
-	// 	d_dr_xX[i].supply = supply;
-	// )
+	d_dr_xX.out = out_req_x;
 	sigbuf_boolarray<Ny,47> d_dr_yX(.in = d_dr_y.out, .supply = supply);
+	d_dr_yX.out = out_req_y;


 	// Validity 
@@ -432,28 +470,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 		.vdd = supply.vdd, .vss = supply.vss);


-	// and grid for reqs into synapses
-
-	and_grid<Nx, Ny> _and_grid(.inx = d_dr_xX.out, .iny = d_dr_yX.out, .supply = supply);
-	(i:Nx*Ny: out[i].r = _and_grid.out[i];)
-
-	// Acknowledge pull down time
-
-	// Pull DOWNs on the ackB lines by synapses (easier to invert).
-	bool _out_acksB[Nx]; // The vertical output ack lines from each syn.
-	A_2N_U_X4 ack_pulldowns[Nx*Ny];
-	pint index;
-	(i:Nx:
-		(j:Ny:
-			index = i + Nx*j;
-			ack_pulldowns[index].n1 = out[index].a;
-			ack_pulldowns[index].n2 = d_dr_xX.out[i]; // GET REFRHRESED IN CORE
-			ack_pulldowns[index].y = _out_acksB[i];
-			ack_pulldowns[index].vss = supply.vss;
-			ack_pulldowns[index].vdd = supply.vdd;
-		)
-	)
-
+	
 	// Line end pull UPs (triggered once reqs removed)
 	// Use two pullups rather than and-pullup 
 	// bc smaller
@@ -462,14 +479,14 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	A_2P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
 	A_1P_U_X4 pu_reset[Nx];
 	(i:Nx:
-		pu[i].p1 = d_dr_xX.out[i];
+		pu[i].p1 = to_pu[i].r;
 		pu[i].p2 = hs_enB;
-		pu[i].y = _out_acksB[i];
+		pu[i].y = to_pu[i].a;
 		pu[i].vdd = supply.vdd;
 		pu[i].vss = supply.vss;

 		pu_reset[i].p1 = _reset_BX[i];
-		pu_reset[i].y = _out_acksB[i];
+		pu_reset[i].y = to_pu[i].a;
 		pu_reset[i].vdd = supply.vdd;
 		pu_reset[i].vss = supply.vss;
 	)
@@ -479,16 +496,17 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	(i:Nx:
 		keeps[i].vdd = supply.vdd;
 		keeps[i].vss = supply.vss;
-		keeps[i].y = _out_acksB[i];
+		keeps[i].y = to_pu[i].a;
 	)

+
 	// ORtree from all output acks, back to the buffer ack.
 	// This is instead of the ack that came from the delayed validity trees,
 	// in decoder_2d_dly.
 	ortree<Nx>  _ortree(.supply = supply);
 	INV_X1 out_ack_invs[Nx];
 	(i:Nx:
-		out_ack_invs[i].a = _out_acksB[i];
+		out_ack_invs[i].a = in_ackB_decoder[i];
 		out_ack_invs[i].vdd = supply.vdd;
 		out_ack_invs[i].vss = supply.vss;

@@ -734,7 +752,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg


 		export template<pint NxC, NyC, Nx, Ny, ACK_STRENGTH>
-		defproc encoder2d(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out; power supply; bool reset_B)		{
+		defproc encoder2d(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out; power supply; bool reset_B)	{
 			// Reset buffers
 			pint H = 2*(NxC + NyC); //Reset strength? to be investigated
 			
@@ -864,8 +882,20 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 		}


-		export template<pint NxC, NyC, Nx, Ny>
+    export
+    defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
+    {
+      INV_X1 inv(.a = reset_B, .vdd=supply.vdd,.vss =supply.vss);
+
+      A_1N_U_X4 pull_down(.n1=in, .y=out);
+      A_1N_U_X4 pull_downR(.n1=inv.y, .y=out);
+    }
+
+
+
+		export template<pint NxC, NyC, Nx, Ny, N_dly>
 		defproc encoder2d_simple(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out;
+			a1of1 to_pd_x[Nx], to_pd_y[Ny]; // Ports for the line end pull downs to tap into
 			power supply; bool reset_B)		{

 			bool _a_x, _a_y;
@@ -915,6 +945,55 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 				Yenc.out.d[i] = buf.in.d.d[i+NxC];
 			)

+
+			// Line pull down stuff
+			// Create delay fifos to emulate the fact that the line pull downs
+			// are at the end of the line, and thus slow.
+			// Note that if N_dly = 0, delay fifo is just a pipe.
+			delay_chain<N_dly> dly_x[Nx];
+			delay_chain<N_dly> dly_y[Ny];	
+			
+			// Create x line req pull downs
+			nrn_line_end_pull_down pd_x[Nx];
+			sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
+			(i:0..Nx-1:
+				dly_x[i].supply = supply;
+				dly_x[i].in = to_pd_x[i].a;
+				pd_x[i].in = dly_x[i].out;
+				
+				pd_x[i].out = to_pd_x[i].r;
+				pd_x[i].reset_B = rsb_pd_x.out[i];
+				pd_x[i].supply = supply;
+			)
+
+			// Create y line req pull downs
+			nrn_line_end_pull_down pd_y[Ny];
+			sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
+			(j:0..Ny-1:
+				dly_y[j].supply = supply;
+				dly_y[j].in = to_pd_y[j].a;
+				pd_y[j].in = dly_y[j].out;
+			
+				pd_y[j].out = to_pd_y[j].r;
+				pd_y[j].reset_B = rsb_pd_y.out[j];
+				pd_y[j].supply = supply;
+			)
+
+			// Add keeps
+			KEEP keep_x[Nx];
+			(i:Nx:
+				keep_x[i].vdd = supply.vdd;
+				keep_x[i].vss = supply.vss;
+				keep_x[i].y = inx[i].r;
+			)
+
+			KEEP keep_y[Ny];
+			(j:Ny:
+				keep_y[j].vdd = supply.vdd;
+				keep_y[j].vss = supply.vss;
+				keep_y[j].y = iny[j].r;
+			)
+
 		}

 		export template<pint Nc, N>
@@ -1007,30 +1086,6 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 		}


-	// export
- //    defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
- //    {
- //      bool _out, __out, nand_out;
- //      BUF_X1 buf1(.a=in, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
- //      BUF_X1 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
- //      INV_X1 inv(.a = __out, .vdd=supply.vdd,.vss =supply.vss);
-
- //      NAND2_X1 aenor(.a=inv.y, .b=reset_B, .y = nand_out, .vdd=supply.vdd,.vss=supply.vss);
-
- //      A_1N_U_X4 pull_down(.a=nand_out, .y=out);
- //    }
-
-    export
-    defproc nrn_line_end_pull_down (bool? in; bool? reset_B; power supply; bool! out)
-    {
-      INV_X1 inv(.a = reset_B, .vdd=supply.vdd,.vss =supply.vss);
-
-      A_1N_U_X4 pull_down(.n1=in, .y=out);
-      A_1N_U_X4 pull_downR(.n1=inv.y, .y=out);
-    }
-
-
-
 		/**
 	   * A 2d grid of neuron handshakers.
 	   * Should then slot into the encoder.
@@ -1039,8 +1094,9 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 	   * for the purpose of running ACT sims.
 	   * It should probably be set to 0 though.
 	   */
-		export template<pint Nx, Ny, N_dly>
+		export template<pint Nx, Ny>
 		defproc nrn_hs_2d_array(a1of1 in[Nx*Ny]; a1of1 outx[Nx], outy[Ny];
+			a1of1 to_pd_x[Nx], to_pd_y[Ny];
 			power supply; bool reset_B) {

 			// Make hella signal buffers
@@ -1067,10 +1123,8 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 				out_req_buf_y[i].a = _outy[i].r;
 				out_req_buf_y[i].y = outy[i].r;
 			)
+
 			// Add buffers on output ack lines
-			// Note that this should be generalised.
-			// And probably won't even be done by ACT/innovus anwyay
-			// TODO: do it properly with sigbufs?
 			BUF_X12 out_ack_buf_x[Nx];
 			(i:Nx:
 				out_ack_buf_x[i].vss = supply.vss;
@@ -1102,52 +1156,11 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
 				)
 			)

-			// Create delay fifos to emulate the fact that the line pull downs
-			// are at the end of the line, and thus slow.
-			// Note that if N_dly = 0, delay fifo is just a pipe.
-			delay_chain<N_dly> dly_x[Nx];
-			delay_chain<N_dly> dly_y[Ny];	
-			
-			// Create x line req pull downs
-			nrn_line_end_pull_down pd_x[Nx];
-			sigbuf<Nx> rsb_pd_x(.in = reset_B, .supply = supply);
-			(i:0..Nx-1:
-				dly_x[i].supply = supply;
-				dly_x[i].in = _outx[i].a;
-				pd_x[i].in = dly_x[i].out;
-				
-				pd_x[i].out = _outx[i].r;
-				pd_x[i].reset_B = rsb_pd_x.out[i];
-				pd_x[i].supply = supply;
-			)
+			// Pipe the ack/req lines through to the pulldowns
+			to_pd_x = _outx;
+			to_pd_y = _outy;

-			// Create y line req pull downs
-			nrn_line_end_pull_down pd_y[Ny];
-			sigbuf<Ny> rsb_pd_y(.in = reset_B, .supply = supply);
-			(j:0..Ny-1:
-				dly_y[j].supply = supply;
-				dly_y[j].in = _outy[j].a;
-				pd_y[j].in = dly_y[j].out;
-			
-				pd_y[j].out = _outy[j].r;
-				pd_y[j].reset_B = rsb_pd_y.out[j];
-				pd_y[j].supply = supply;
-			)

-			// Add keeps
-			KEEP keep_x[Nx];
-			(i:Nx:
-				keep_x[i].vdd = supply.vdd;
-				keep_x[i].vss = supply.vss;
-				keep_x[i].y = _outx[i].r;
-			)
-
-			KEEP keep_y[Ny];
-			(j:Ny:
-				keep_y[j].vdd = supply.vdd;
-				keep_y[j].vss = supply.vss;
-				keep_y[j].y = _outy[j].r;
-			)
 		}


--- a/test/unit_tests/texel_dualcore/run/prsim.in
+++ b/test/unit_tests/texel_dualcore/run/prsim.in
--- a/test/unit_tests/texel_dualcore/run/prsim.out
+++ b/test/unit_tests/texel_dualcore/run/prsim.out
--- a/test/unit_tests/texel_dualcore/run/test.prs
+++ b/test/unit_tests/texel_dualcore/run/test.prs
--- a/test/unit_tests/texel_dualcore/test.act
+++ b/test/unit_tests/texel_dualcore/test.act
@@ -80,12 +80,16 @@ pint REG_NCW = 23;
 defproc chip_texel_dualcore (bd<N_IN> in, out;

    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+
    a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
    a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
-    // bool c1_syn_r[N_SYN_X * N_SYN_Y];
-    // bool c1_syn_a[N_SYN_X * N_SYN_Y];
-    // bool c1_nrn_r[N_NRN_X * N_NRN_Y];
-    // bool c1_nrn_a[N_NRN_X * N_NRN_Y];
+
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
    
    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
@@ -94,12 +98,16 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];

    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
    a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
    a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
-    // bool c2_syn_r[N_SYN_X * N_SYN_Y];
-    // bool c2_syn_a[N_SYN_X * N_SYN_Y];
-    // bool c2_nrn_r[N_NRN_X * N_NRN_Y];
-    // bool c2_nrn_a[N_NRN_X * N_NRN_Y];
+
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
    
    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
@@ -118,25 +126,6 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
    supply.vdd = Vdd;
    supply.vss = GND;

-
-    // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
-    // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
-    // (i:N_SYN_X * N_SYN_Y:
-    //     c1_synapses[i].r = c1_syn_r[i];
-    //     c2_synapses[i].r = c2_syn_r[i];
-    //     c1_synapses[i].a = c1_syn_a[i];
-    //     c2_synapses[i].a = c2_syn_a[i];
-    // )
-    // (i:N_NRN_X * N_NRN_Y:
-    //     c1_neurons[i].r = c1_nrn_r[i];
-    //     c2_neurons[i].r = c2_nrn_r[i];
-    //     c1_neurons[i].a = c1_nrn_a[i];
-    //     c2_neurons[i].a = c2_nrn_a[i];
-    // )
-
-
    texel_dualcore<N_IN,
    N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
    NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
@@ -148,10 +137,35 @@ defproc chip_texel_dualcore (bd<N_IN> in, out;
    N_LINE_PD_DLY,
    N_BD_DLY_CFG, N_BD_DLY_CFG2,
    REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out,
-        .c1_reg_data = c1_reg_data, .c1_synapses = c1_synapses, .c1_neurons = c1_neurons, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_synapses = c2_synapses, .c2_neurons = c2_neurons, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
-        .loopback_en = loopback_en, .supply = supply, .reset_B = _reset_B);
+        .c1_reg_data = c1_reg_data, .c1_dec_req_x = c1_dec_req_x, .c1_dec_req_y = c1_dec_req_y, .c1_dec_ackB = c1_dec_ackB, .c1_syn_pu = c1_syn_pu, .c1_enc_inx = c1_enc_inx, .c1_enc_iny = c1_enc_iny, .c1_nrn_pd_x = c1_nrn_pd_x, .c1_nrn_pd_y = c1_nrn_pd_y, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_dec_req_x = c2_dec_req_x, .c2_dec_req_y = c2_dec_req_y, .c2_dec_ackB = c2_dec_ackB, .c2_syn_pu = c2_syn_pu, .c2_enc_inx = c2_enc_inx, .c2_enc_iny = c2_enc_iny, .c2_nrn_pd_x = c2_nrn_pd_x, .c2_nrn_pd_y = c2_nrn_pd_y, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
+        .loopback_en = loopback_en,
+        .reset_B = _reset_B, .reset_reg_B = _reset_B,
+        .supply = supply);


+    decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> c1_syn_grid(
+        .synapses = c1_synapses,
+        .in_req_x = c1_dec_req_x, .in_req_y = c1_dec_req_y,
+        .to_pu = c1_syn_pu,
+        .out_ackB_decoder = c1_dec_ackB,
+        .supply = supply);
+
+    nrn_hs_2d_array<N_NRN_X,N_NRN_Y> c1_nrn_grid(.in = c1_neurons,
+        .outx = c1_enc_inx, .outy = c1_enc_iny,
+        .to_pd_x = c1_nrn_pd_x, .to_pd_y = c1_nrn_pd_y,
+        .supply = supply, .reset_B = _reset_B);
+
+    decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> c2_syn_grid(
+        .synapses = c2_synapses,
+        .in_req_x = c2_dec_req_x, .in_req_y = c2_dec_req_y,
+        .to_pu = c2_syn_pu,
+        .out_ackB_decoder = c2_dec_ackB,
+        .supply = supply);
+
+    nrn_hs_2d_array<N_NRN_X,N_NRN_Y> c2_nrn_grid(.in = c2_neurons,
+        .outx = c2_enc_inx, .outy = c2_enc_iny,
+        .to_pd_x = c2_nrn_pd_x, .to_pd_y = c2_nrn_pd_y,
+        .supply = supply, .reset_B = _reset_B);
 }


--- a/test/unit_tests/texel_dualcore/test.prsim
+++ b/test/unit_tests/texel_dualcore/test.prsim
@@ -10644,9 +10644,10 @@ cycle
 mode run
 status X
 system "echo '[] Set reset 0'"
-status X
+# status X
 set Reset 0
 cycle
+status X

 assert-bd-channel-neutral "c.out" 32

--- a/test/unit_tests/texel_dualcore_innovus/run/prsim.in
+++ b/test/unit_tests/texel_dualcore_innovus/run/prsim.in
@@ -0,0 +1,29 @@
+initialize
+load-scm "helper.scm"
+random
+set GND 0
+set Vdd 1
+set Reset 1
+
+mode reset
+cycle
+status U
+# watchall
+
+
+set c.bd_dly_cfg[0] 1
+set c.bd_dly_cfg[1] 1
+set c.bd_dly_cfg[2] 1
+set c.bd_dly_cfg[3] 1
+
+set c.bd_dly_cfg2[0] 1
+set c.bd_dly_cfg2[1] 1
+
+
+set-bd-channel-neutral "c.in" 32
+set c.out.a 0
+set c.loopback_en 1
+# set c.loopback_en 0
+# set R
+
+cycle
--- a/test/unit_tests/texel_dualcore_innovus/run/prsim.out
+++ b/test/unit_tests/texel_dualcore_innovus/run/prsim.out
--- a/test/unit_tests/texel_dualcore_innovus/run/test.prs
+++ b/test/unit_tests/texel_dualcore_innovus/run/test.prs
--- a/test/unit_tests/texel_dualcore_innovus/test.act
+++ b/test/unit_tests/texel_dualcore_innovus/test.act
@@ -0,0 +1,149 @@
+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/chips.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+
+open tmpl::dataflow_neuro;
+
+
+
+pint N_IN = 32;
+
+pint N_NRN_X = 15;
+pint N_NRN_Y = 6;
+pint NC_NRN_X = 4;
+pint NC_NRN_Y = 3;
+
+pint N_SYN_X = 15;
+pint N_SYN_Y = 348;
+pint NC_SYN_X = 6;
+pint NC_SYN_Y = 9;
+
+pint N_SYN_DLY_CFG = 4;
+pint N_BD_DLY_CFG = 4;
+pint N_BD_DLY_CFG2 = 2;
+
+pint N_NRN_MON_X = N_NRN_X*2; // [mon,kill]*N
+pint N_NRN_MON_Y = N_NRN_Y; // [mon]*N
+
+pint N_SYN_MON_X = N_SYN_X*4; // [mon, dev_mon, set, reset]*N
+pint N_SYN_MON_Y = N_SYN_Y; //  [mon]*N
+
+pint N_MON_AMZO_PER_SYN = 5;
+pint N_MON_AMZO_PER_NRN = 7;
+
+pint N_FLAGS_PER_SYN = 4; // Syn: Must be at least 3 (since those ones have special safety)
+pint N_FLAGS_PER_NRN = 9; // and leq than the number of bits in a reg, since have presumed only needs one.
+
+pint N_BUFFERS = 3;
+
+pint N_LINE_PD_DLY = 3;
+
+pint REG_NCA = 6;
+pint REG_M = 1<<REG_NCA;
+pint REG_NCW = 23;
+
+
+defproc chip_texel_dualcore_innovus (bd<N_IN> in, out;
+
+    Mx1of2<REG_NCW> c1_reg_data[REG_M];
+
+    // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
+
+    bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
+    bool? c1_dec_ackB[N_SYN_X];
+    a1of1 c1_syn_pu[N_SYN_X];
+
+    a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
+    a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
+    
+    bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
+    bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
+    bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+
+    // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
+    // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
+
+    bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
+    bool? c2_dec_ackB[N_SYN_X];
+    a1of1 c2_syn_pu[N_SYN_X];
+
+    a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
+    a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
+    
+    bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
+    bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
+    bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
+    bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
+    bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
+
+    bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
+    bool? loopback_en;
+    bool? reset_B, reset_reg_B
+    ){
+
+    // bool _reset_B; 
+    // prs {
+    //     Reset => _reset_B-
+    // }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    texel_dualcore<N_IN,
+    N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
+    NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+    N_SYN_DLY_CFG,
+    N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+    N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,
+    N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,
+    N_BUFFERS,
+    N_LINE_PD_DLY,
+    N_BD_DLY_CFG, N_BD_DLY_CFG2,
+    REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out,
+        .c1_reg_data = c1_reg_data, .c1_dec_req_x = c1_dec_req_x, .c1_dec_req_y = c1_dec_req_y, .c1_dec_ackB = c1_dec_ackB, .c1_syn_pu = c1_syn_pu, .c1_enc_inx = c1_enc_inx, .c1_enc_iny = c1_enc_iny, .c1_nrn_pd_x = c1_nrn_pd_x, .c1_nrn_pd_y = c1_nrn_pd_y, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_dec_req_x = c2_dec_req_x, .c2_dec_req_y = c2_dec_req_y, .c2_dec_ackB = c2_dec_ackB, .c2_syn_pu = c2_syn_pu, .c2_enc_inx = c2_enc_inx, .c2_enc_iny = c2_enc_iny, .c2_nrn_pd_x = c2_nrn_pd_x, .c2_nrn_pd_y = c2_nrn_pd_y, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
+        .loopback_en = loopback_en, .supply = supply, .reset_B = reset_B, .reset_reg_B = reset_reg_B);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+chip_texel_dualcore_innovus c; 
--- a/test/unit_tests/texel_dualcore_innovus/test.prsim
+++ b/test/unit_tests/texel_dualcore_innovus/test.prsim
@@ -0,0 +1,19 @@
+# watchall
+
+
+set c.bd_dly_cfg[0] 1
+set c.bd_dly_cfg[1] 1
+set c.bd_dly_cfg[2] 1
+set c.bd_dly_cfg[3] 1
+
+set c.bd_dly_cfg2[0] 1
+set c.bd_dly_cfg2[1] 1
+
+
+set-bd-channel-neutral "c.in" 32
+set c.out.a 0
+set c.loopback_en 1
+# set c.loopback_en 0
+# set R
+
+cycle
Author	SHA1	Message	Date
alexmadison	3f7cbf2b87	Merge branch 'innovus_ready' into dev	2022-04-21 14:49:30 +02:00
alexmadison	28c821a757	Merge branch 'dev' of ssh://git.web.rug.nl:222/bics/actlib_dataflow_neuro into dev	2022-04-21 14:49:20 +02:00
alexmadison	ec03f8abe4	added reg reset sig	2022-04-21 14:33:41 +02:00
alexmadison	c91a7cad50	added separate reset sig for regs	2022-04-21 14:32:04 +02:00
alexmadison	75a42fff1b	texel prs for innovus generated	2022-04-21 14:31:35 +02:00
alexmadison	3443d46b9b	completely cut out the neuron and synapse hs from core	2022-04-21 14:07:15 +02:00
alexmadison	41f240726c	internal access added	2022-04-21 10:41:37 +02:00
alexmadison	c3b336267b	added nrn syn ports to dualcore	2022-04-21 10:35:43 +02:00
alexmadison	1a41c03aeb	more renaming	2022-04-21 10:23:58 +02:00
alexmadison	10ecb7f55f	exposed pd lines	2022-04-21 10:11:26 +02:00
alexmadison	83ae6a4cc3	adjusted pull up channel names	2022-04-20 19:31:06 +02:00
alexmadison	bb63182694	disentangled neurons and pull downs	2022-04-20 19:21:55 +02:00
alexmadison	351b3ea151	disentangled synapse handshake circuits, passing tests	2022-04-20 18:24:43 +02:00