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e4fbc508af
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1c4206b7d4
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1c4206b7d4 | ||
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dbad8816a9 | ||
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9e7b1cd120 | ||
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ca3a56572d | ||
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627caf1aed | ||
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7e2ae21098 | ||
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8cc3c14f83 |
@ -279,6 +279,12 @@ defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
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/**
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* @TODO if this is going to be released, we should expose the to_pd terminals
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* and probably buffer them the same
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* like we did in the encoder or the hybrid
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* Also we should probably keep the outs to be Nx x lines and Ny y lines,
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* not Nx*Ny and-ed lines.
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*
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* 2D decoder which uses synapse handshaking using line pulldowns.
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* Nx is the x size of the decoder array
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* NxC is the number of wires in the x channel.
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@ -1,55 +0,0 @@
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t.ff.__clk_B t.ff._clk_B t.d t.clk t._clk_B
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[0] start test
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15221 Reset : 0
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15221 t.clk : 0
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15221 t.d : 0
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16947 t._clk_B : 1 [by t.clk:=0]
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16986 t.ff._clk_B : 0 [by t._clk_B:=1]
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17001 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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80587 t._reset_B : 1 [by Reset:=0]
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[1] reset completed
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[2] tested d = 0, clk rise
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80587 t.clk : 1
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80587 t.d : 1
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80600 t.ff._mqib : 0 [by t.d:=1]
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80640 t.ff._mqi : 1 [by t.ff._mqib:=0]
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81078 t._clk_B : 0 [by t.clk:=1]
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81493 t.ff._clk_B : 1 [by t._clk_B:=0]
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81513 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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87554 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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87570 t.q : 1 [by t.ff._sqib:=0]
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87601 t.ff._sqi : 1 [by t.ff._sqib:=0]
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131668 t.ff.q_B : 0 [by t.q:=1]
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131668 t.clk : 0
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145392 t._clk_B : 1 [by t.clk:=0]
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145396 t.ff._clk_B : 0 [by t._clk_B:=1]
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154525 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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154525 t.d : 0
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154540 t.ff._mqib : 1 [by t.d:=0]
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197788 t.ff._mqi : 0 [by t.ff._mqib:=1]
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197788 t.clk : 1
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234719 t._clk_B : 0 [by t.clk:=1]
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234774 t.ff._clk_B : 1 [by t._clk_B:=0]
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286427 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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316207 t.ff._sqib : 1 [by t.ff.__clk_B:=0]
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330056 t.ff._sqi : 0 [by t.ff._sqib:=1]
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341019 t.q : 0 [by t.ff._sqib:=1]
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355362 t.ff.q_B : 1 [by t.q:=0]
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355362 t.clk : 0
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355784 t._clk_B : 1 [by t.clk:=0]
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404498 t.ff._clk_B : 0 [by t._clk_B:=1]
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404499 t.ff.__clk_B : 1 [by t.ff._clk_B:=0]
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404499 t.d : 1
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404500 t.ff._mqib : 0 [by t.d:=1]
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424705 t.ff._mqi : 1 [by t.ff._mqib:=0]
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[3] tested d = 1, clk rise and fall
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424705 t.clk : 1
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424987 t._clk_B : 0 [by t.clk:=1]
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425755 t.ff._clk_B : 1 [by t._clk_B:=0]
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425758 t.ff.__clk_B : 0 [by t.ff._clk_B:=1]
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448196 t.ff._sqib : 0 [by t.ff._clk_B:=1]
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448747 t.ff._sqi : 1 [by t.ff._sqib:=0]
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449267 t.q : 1 [by t.ff._sqib:=0]
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450221 t.ff.q_B : 0 [by t.q:=1]
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450221 t.d : 0
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@ -1,29 +0,0 @@
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= "GND" "GND"
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= "Vdd" "Vdd"
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= "Reset" "Reset"
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"Reset"->"t._reset_B"-
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~("Reset")->"t._reset_B"+
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"t.clk"->"t._clk_B"-
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~("t.clk")->"t._clk_B"+
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= "t._reset_B" "t.ff.reset_B"
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"t.ff.clk_B"->"t.ff._clk_B"-
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~("t.ff.clk_B")->"t.ff._clk_B"+
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"t.ff._clk_B"->"t.ff.__clk_B"-
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~("t.ff._clk_B")->"t.ff.__clk_B"+
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~"t.ff.d"&~"t.ff._clk_B"|~"t.ff.reset_B"|~"t.ff.__clk_B"&~"t.ff._mqi"->"t.ff._mqib"+
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("t.ff.d"&"t.ff.__clk_B"|"t.ff._mqi"&"t.ff._clk_B")&"t.ff.reset_B"->"t.ff._mqib"-
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"t.ff._mqib"->"t.ff._mqi"-
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~("t.ff._mqib")->"t.ff._mqi"+
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~"t.ff._mqi"&~"t.ff.__clk_B"|~"t.ff.reset_B"|~"t.ff._sqi"&~"t.ff._clk_B"->"t.ff._sqib"+
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("t.ff._mqi"&"t.ff._clk_B"|"t.ff._sqi"&"t.ff.__clk_B")&"t.ff.reset_B"->"t.ff._sqib"-
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"t.ff._sqib"->"t.ff._sqi"-
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~("t.ff._sqib")->"t.ff._sqi"+
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"t.ff._sqib"->"t.ff.q"-
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~("t.ff._sqib")->"t.ff.q"+
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"t.ff.q"->"t.ff.q_B"-
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~("t.ff.q")->"t.ff.q_B"+
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= "Vdd" "t.ff.vdd"
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= "GND" "t.ff.vss"
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= "t.q" "t.ff.q"
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= "t._clk_B" "t.ff.clk_B"
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= "t.d" "t.ff.d"
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@ -1,50 +0,0 @@
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/primitives.act";
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import globals;
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open tmpl::dataflow_neuro;
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defproc flipflop_test (bool! q; bool? d,clk){
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bool _clk_B;
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DFFQ_R_X1 ff(.d=d,.clk_B = _clk_B, .q = q);
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//Low active Reset
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bool _reset_B;
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prs {
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Reset => _reset_B-
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clk => _clk_B-
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}
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ff.vss = GND;
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ff.vdd = Vdd;
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ff.reset_B = _reset_B;
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}
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flipflop_test t;
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@ -1,51 +0,0 @@
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watchall
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system "echo '[0] start test'"
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set Reset 0
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set t.d 0
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set t.clk 0
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cycle
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status X
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mode run
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assert t.q 0
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system "echo '[1] reset completed'"
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system "echo '[2] tested d = 0, clk rise'"
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set t.clk 1
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set t.d 1
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cycle
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set t.clk 0
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cycle
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set t.d 0
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cycle
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assert t.q 1
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set t.clk 1
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cycle
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assert t.q 0
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set t.d 0
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set t.clk 0
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cycle
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assert t.q 0
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set t.d 1
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cycle
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set t.clk 0
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cycle
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assert t.q 0
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system "echo '[3] tested d = 1, clk rise and fall'"
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set t.d 1
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cycle
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set t.clk 1
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cycle
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set t.d 0
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cycle
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assert t.q 1
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@ -28,7 +28,13 @@
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import "../../dataflow_neuro/cell_lib_std.act";
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open std_cell_template::dataflow_neuro;
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open tmpl::dataflow_neuro;
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// open actlib_dataflow_neuro::dataflow_neuro;
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// namespace tmpl {
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// namespace dataflow_neuro {
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TIELO_X1 cell1;
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TIEHI_X1 cell2;
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@ -36,9 +42,9 @@ INV_X1 cell4;
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INV_X2 cell5;
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INV_X4 cell6;
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INV_X8 cell7;
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CLKBUF1 cell8;
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CLKBUF2 cell9;
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CLKBUF3 cell10;
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// CLKBUF1 cell8;
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// CLKBUF2 cell9;
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// CLKBUF3 cell10;
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NOR2_X1 cell11;
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NOR3_X1 cell12;
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OR2_X1 cell13;
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@ -57,3 +63,4 @@ AOI22_X1 cell29;
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TBUF1_X1 cell30;
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TBUF_X2 cell31;
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// }}
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File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -1,2 +0,0 @@
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-- Master.tag File, Rev:1.0
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verilog.v
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File diff suppressed because one or more lines are too long
@ -1,2 +0,0 @@
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-- Master.tag File, Rev:1.0
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verilog.v
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File diff suppressed because one or more lines are too long
@ -1,2 +0,0 @@
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-- Master.tag File, Rev:1.0
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verilog.v
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@ -1,17 +0,0 @@
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module tmpl_0_0dataflow__neuro_0_0andtree_33_4(Iin0 , Iin1 , Iin2 , out, vdd, vss);
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input vdd;
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input vss;
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input Iin0 ;
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input Iin1 ;
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input Iin2 ;
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output out;
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// -- signals ---
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wire out ;
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wire Iin0 ;
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wire Iin1 ;
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wire Iin2 ;
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// --- instances
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AND3_X1 Iand3s0 (.y(out), .a(Iin0 ), .b(Iin1 ), .c(Iin2 ), .vdd(vdd), .vss(vss));
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endmodule
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@ -1,2 +0,0 @@
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-- Master.tag File, Rev:1.0
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verilog.v
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@ -1,23 +0,0 @@
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module tmpl_0_0dataflow__neuro_0_0andtree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out, vdd, vss);
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input vdd;
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input vss;
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input Iin0 ;
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input Iin1 ;
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input Iin2 ;
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input Iin3 ;
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output out;
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// -- signals ---
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wire Iin1 ;
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wire Itmp5 ;
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wire out ;
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wire Iin2 ;
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wire Itmp4 ;
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wire Iin3 ;
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wire Iin0 ;
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// --- instances
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AND2_X1 Iand2s0 (.y(Itmp4 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s1 (.y(Itmp5 ), .a(Iin2 ), .b(Iin3 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s2 (.y(out), .a(Itmp4 ), .b(Itmp5 ), .vdd(vdd), .vss(vss));
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endmodule
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@ -1,2 +0,0 @@
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-- Master.tag File, Rev:1.0
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verilog.v
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@ -1,25 +0,0 @@
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module tmpl_0_0dataflow__neuro_0_0andtree_35_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , out, vdd, vss);
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input vdd;
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input vss;
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input Iin0 ;
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input Iin1 ;
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input Iin2 ;
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input Iin3 ;
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input Iin4 ;
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output out;
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// -- signals ---
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wire Iin3 ;
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wire Iin0 ;
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wire Iin4 ;
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wire Iin1 ;
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wire Iin2 ;
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wire Itmp5 ;
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wire Itmp6 ;
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wire out ;
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// --- instances
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AND3_X1 Iand3s0 (.y(Itmp6 ), .a(Iin2 ), .b(Iin3 ), .c(Iin4 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s0 (.y(Itmp5 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s1 (.y(out), .a(Itmp5 ), .b(Itmp6 ), .vdd(vdd), .vss(vss));
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endmodule
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@ -1,2 +0,0 @@
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-- Master.tag File, Rev:1.0
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verilog.v
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@ -1,29 +0,0 @@
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module tmpl_0_0dataflow__neuro_0_0andtree_36_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , out, vdd, vss);
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input vdd;
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input vss;
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input Iin0 ;
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input Iin1 ;
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input Iin2 ;
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input Iin3 ;
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input Iin4 ;
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input Iin5 ;
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output out;
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// -- signals ---
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wire Iin3 ;
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wire Iin1 ;
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wire Itmp8 ;
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wire Itmp7 ;
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wire Iin5 ;
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wire Iin4 ;
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wire Itmp6 ;
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wire Iin2 ;
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wire out ;
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wire Iin0 ;
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// --- instances
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AND3_X1 Iand3s0 (.y(out), .a(Itmp6 ), .b(Itmp7 ), .c(Itmp8 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s0 (.y(Itmp6 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s1 (.y(Itmp7 ), .a(Iin2 ), .b(Iin3 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s2 (.y(Itmp8 ), .a(Iin4 ), .b(Iin5 ), .vdd(vdd), .vss(vss));
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endmodule
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@ -1,2 +0,0 @@
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-- Master.tag File, Rev:1.0
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verilog.v
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@ -1,41 +0,0 @@
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module tmpl_0_0dataflow__neuro_0_0andtree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , out, vdd, vss);
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input vdd;
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input vss;
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input Iin0 ;
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input Iin1 ;
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input Iin2 ;
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input Iin3 ;
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input Iin4 ;
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input Iin5 ;
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input Iin6 ;
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input Iin7 ;
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input Iin8 ;
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output out;
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// -- signals ---
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wire Itmp12 ;
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wire Itmp14 ;
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wire Iin8 ;
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wire Itmp13 ;
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wire Itmp10 ;
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wire Iin0 ;
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wire Iin7 ;
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wire Iin1 ;
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wire Itmp11 ;
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wire Iin2 ;
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wire Iin3 ;
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wire out ;
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wire Itmp9 ;
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wire Iin5 ;
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wire Iin6 ;
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wire Iin4 ;
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// --- instances
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AND3_X1 Iand3s0 (.y(Itmp12 ), .a(Iin6 ), .b(Iin7 ), .c(Iin8 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s0 (.y(Itmp9 ), .a(Iin0 ), .b(Iin1 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s1 (.y(Itmp10 ), .a(Iin2 ), .b(Iin3 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s2 (.y(Itmp11 ), .a(Iin4 ), .b(Iin5 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s3 (.y(Itmp13 ), .a(Itmp9 ), .b(Itmp10 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s4 (.y(Itmp14 ), .a(Itmp11 ), .b(Itmp12 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand2s5 (.y(out), .a(Itmp13 ), .b(Itmp14 ), .vdd(vdd), .vss(vss));
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endmodule
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||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
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@ -1,137 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0append_329_72_72_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Isupply_vss , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d_d0_d0 ;
|
||||
input Iin_d_d0_d1 ;
|
||||
input Iin_d_d1_d0 ;
|
||||
input Iin_d_d1_d1 ;
|
||||
input Iin_d_d2_d0 ;
|
||||
input Iin_d_d2_d1 ;
|
||||
input Iin_d_d3_d0 ;
|
||||
input Iin_d_d3_d1 ;
|
||||
input Iin_d_d4_d0 ;
|
||||
input Iin_d_d4_d1 ;
|
||||
input Iin_d_d5_d0 ;
|
||||
input Iin_d_d5_d1 ;
|
||||
input Iin_d_d6_d0 ;
|
||||
input Iin_d_d6_d1 ;
|
||||
input Iin_d_d7_d0 ;
|
||||
input Iin_d_d7_d1 ;
|
||||
input Iin_d_d8_d0 ;
|
||||
input Iin_d_d8_d1 ;
|
||||
input Iin_d_d9_d0 ;
|
||||
input Iin_d_d9_d1 ;
|
||||
input Iin_d_d10_d0 ;
|
||||
input Iin_d_d10_d1 ;
|
||||
input Iin_d_d11_d0 ;
|
||||
input Iin_d_d11_d1 ;
|
||||
input Iin_d_d12_d0 ;
|
||||
input Iin_d_d12_d1 ;
|
||||
input Iin_d_d13_d0 ;
|
||||
input Iin_d_d13_d1 ;
|
||||
input Iin_d_d14_d0 ;
|
||||
input Iin_d_d14_d1 ;
|
||||
input Iin_d_d15_d0 ;
|
||||
input Iin_d_d15_d1 ;
|
||||
input Iin_d_d16_d0 ;
|
||||
input Iin_d_d16_d1 ;
|
||||
input Iin_d_d17_d0 ;
|
||||
input Iin_d_d17_d1 ;
|
||||
input Iin_d_d18_d0 ;
|
||||
input Iin_d_d18_d1 ;
|
||||
input Iin_d_d19_d0 ;
|
||||
input Iin_d_d19_d1 ;
|
||||
input Iin_d_d20_d0 ;
|
||||
input Iin_d_d20_d1 ;
|
||||
input Iin_d_d21_d0 ;
|
||||
input Iin_d_d21_d1 ;
|
||||
input Iin_d_d22_d0 ;
|
||||
input Iin_d_d22_d1 ;
|
||||
input Iin_d_d23_d0 ;
|
||||
input Iin_d_d23_d1 ;
|
||||
input Iin_d_d24_d0 ;
|
||||
input Iin_d_d24_d1 ;
|
||||
input Iin_d_d25_d0 ;
|
||||
input Iin_d_d25_d1 ;
|
||||
input Iin_d_d26_d0 ;
|
||||
input Iin_d_d26_d1 ;
|
||||
input Iin_d_d27_d0 ;
|
||||
input Iin_d_d27_d1 ;
|
||||
input Iin_d_d28_d0 ;
|
||||
input Iin_d_d28_d1 ;
|
||||
|
||||
|
||||
|
||||
input Isupply_vss ;
|
||||
|
||||
// -- signals ---
|
||||
wire Iin_d_d28_d1 ;
|
||||
wire Iin_d_d25_d0 ;
|
||||
wire Iin_d_d5_d0 ;
|
||||
wire Isupply_vss ;
|
||||
output Iout_d_d29_d0 ;
|
||||
wire Iin_d_d27_d0 ;
|
||||
wire Iin_d_d0_d1 ;
|
||||
wire Iin_d_d26_d0 ;
|
||||
wire Iin_d_d23_d1 ;
|
||||
wire Iin_d_d20_d1 ;
|
||||
wire Iin_d_d27_d1 ;
|
||||
wire Iin_d_d3_d1 ;
|
||||
wire Iin_d_d12_d1 ;
|
||||
wire Iin_d_d9_d1 ;
|
||||
wire Iin_d_d15_d0 ;
|
||||
wire Iin_d_d7_d1 ;
|
||||
wire Iin_d_d6_d1 ;
|
||||
wire Iin_d_d11_d0 ;
|
||||
wire Iin_d_d10_d1 ;
|
||||
wire Iin_d_d1_d0 ;
|
||||
wire Iin_d_d0_d0 ;
|
||||
wire Iin_d_d25_d1 ;
|
||||
wire Iin_d_d19_d1 ;
|
||||
wire Iin_d_d17_d1 ;
|
||||
wire Iin_d_d15_d1 ;
|
||||
wire Iin_d_d7_d0 ;
|
||||
wire Iin_d_d4_d0 ;
|
||||
output Iout_d_d29_d1 ;
|
||||
wire Iin_d_d21_d0 ;
|
||||
wire Iin_d_d20_d0 ;
|
||||
wire Iin_d_d4_d1 ;
|
||||
wire Iin_d_d26_d1 ;
|
||||
wire Iin_d_d18_d0 ;
|
||||
wire Iin_d_d5_d1 ;
|
||||
wire Iin_d_d3_d0 ;
|
||||
wire Iin_d_d22_d0 ;
|
||||
wire Iin_d_d2_d1 ;
|
||||
wire Iin_d_d16_d1 ;
|
||||
wire Iin_d_d13_d1 ;
|
||||
wire Iin_d_d6_d0 ;
|
||||
wire Iin_d_d22_d1 ;
|
||||
wire Iin_d_d21_d1 ;
|
||||
wire Iin_d_d14_d0 ;
|
||||
wire Iin_d_d11_d1 ;
|
||||
wire Iin_d_d8_d1 ;
|
||||
wire Iin_d_d19_d0 ;
|
||||
wire Iin_d_d14_d1 ;
|
||||
wire Iin_d_d24_d1 ;
|
||||
wire Iin_d_d9_d0 ;
|
||||
wire Iin_d_d18_d1 ;
|
||||
wire Iin_d_d13_d0 ;
|
||||
wire Iin_d_d12_d0 ;
|
||||
output Iout_d_d30_d0 ;
|
||||
wire Iin_d_d24_d0 ;
|
||||
wire Iin_d_d17_d0 ;
|
||||
wire Iin_d_d1_d1 ;
|
||||
wire Isb_in ;
|
||||
wire Iin_d_d10_d0 ;
|
||||
wire Iin_d_d8_d0 ;
|
||||
wire Iin_d_d28_d0 ;
|
||||
wire Iin_d_d23_d0 ;
|
||||
wire Iin_d_d16_d0 ;
|
||||
wire Iin_d_d2_d0 ;
|
||||
|
||||
// --- instances
|
||||
TIELO_X1 Itielows0 (.y(Iout_d_d29_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows1 (.y(Iout_d_d30_d0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0vtree_329_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_32_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d29_d0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,142 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0append_331_71_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Isupply_vss , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d_d0_d0 ;
|
||||
input Iin_d_d0_d1 ;
|
||||
input Iin_d_d1_d0 ;
|
||||
input Iin_d_d1_d1 ;
|
||||
input Iin_d_d2_d0 ;
|
||||
input Iin_d_d2_d1 ;
|
||||
input Iin_d_d3_d0 ;
|
||||
input Iin_d_d3_d1 ;
|
||||
input Iin_d_d4_d0 ;
|
||||
input Iin_d_d4_d1 ;
|
||||
input Iin_d_d5_d0 ;
|
||||
input Iin_d_d5_d1 ;
|
||||
input Iin_d_d6_d0 ;
|
||||
input Iin_d_d6_d1 ;
|
||||
input Iin_d_d7_d0 ;
|
||||
input Iin_d_d7_d1 ;
|
||||
input Iin_d_d8_d0 ;
|
||||
input Iin_d_d8_d1 ;
|
||||
input Iin_d_d9_d0 ;
|
||||
input Iin_d_d9_d1 ;
|
||||
input Iin_d_d10_d0 ;
|
||||
input Iin_d_d10_d1 ;
|
||||
input Iin_d_d11_d0 ;
|
||||
input Iin_d_d11_d1 ;
|
||||
input Iin_d_d12_d0 ;
|
||||
input Iin_d_d12_d1 ;
|
||||
input Iin_d_d13_d0 ;
|
||||
input Iin_d_d13_d1 ;
|
||||
input Iin_d_d14_d0 ;
|
||||
input Iin_d_d14_d1 ;
|
||||
input Iin_d_d15_d0 ;
|
||||
input Iin_d_d15_d1 ;
|
||||
input Iin_d_d16_d0 ;
|
||||
input Iin_d_d16_d1 ;
|
||||
input Iin_d_d17_d0 ;
|
||||
input Iin_d_d17_d1 ;
|
||||
input Iin_d_d18_d0 ;
|
||||
input Iin_d_d18_d1 ;
|
||||
input Iin_d_d19_d0 ;
|
||||
input Iin_d_d19_d1 ;
|
||||
input Iin_d_d20_d0 ;
|
||||
input Iin_d_d20_d1 ;
|
||||
input Iin_d_d21_d0 ;
|
||||
input Iin_d_d21_d1 ;
|
||||
input Iin_d_d22_d0 ;
|
||||
input Iin_d_d22_d1 ;
|
||||
input Iin_d_d23_d0 ;
|
||||
input Iin_d_d23_d1 ;
|
||||
input Iin_d_d24_d0 ;
|
||||
input Iin_d_d24_d1 ;
|
||||
input Iin_d_d25_d0 ;
|
||||
input Iin_d_d25_d1 ;
|
||||
input Iin_d_d26_d0 ;
|
||||
input Iin_d_d26_d1 ;
|
||||
input Iin_d_d27_d0 ;
|
||||
input Iin_d_d27_d1 ;
|
||||
input Iin_d_d28_d0 ;
|
||||
input Iin_d_d28_d1 ;
|
||||
input Iin_d_d29_d0 ;
|
||||
input Iin_d_d29_d1 ;
|
||||
input Iin_d_d30_d0 ;
|
||||
input Iin_d_d30_d1 ;
|
||||
|
||||
|
||||
input Isupply_vss ;
|
||||
|
||||
// -- signals ---
|
||||
wire Iin_d_d17_d1 ;
|
||||
wire Iin_d_d11_d0 ;
|
||||
wire Iin_d_d0_d0 ;
|
||||
wire Iin_d_d2_d1 ;
|
||||
wire Iin_d_d27_d0 ;
|
||||
wire Iin_d_d6_d0 ;
|
||||
wire Iin_d_d13_d1 ;
|
||||
wire Iin_d_d9_d1 ;
|
||||
wire Iin_d_d8_d0 ;
|
||||
wire Iin_d_d3_d0 ;
|
||||
wire Iin_d_d30_d1 ;
|
||||
wire Iin_d_d10_d1 ;
|
||||
wire Isupply_vss ;
|
||||
wire Iin_d_d23_d1 ;
|
||||
wire Iin_d_d20_d1 ;
|
||||
wire Iin_d_d7_d1 ;
|
||||
wire Iin_d_d28_d1 ;
|
||||
wire Iin_d_d11_d1 ;
|
||||
wire Iin_d_d28_d0 ;
|
||||
wire Iin_d_d24_d0 ;
|
||||
wire Iin_d_d26_d0 ;
|
||||
wire Iin_d_d25_d1 ;
|
||||
wire Iin_d_d8_d1 ;
|
||||
wire Iin_d_d4_d0 ;
|
||||
wire Iin_d_d23_d0 ;
|
||||
wire Iin_d_d9_d0 ;
|
||||
wire Iin_d_d21_d0 ;
|
||||
wire Iin_d_d13_d0 ;
|
||||
wire Iin_d_d3_d1 ;
|
||||
output Iout_d_d31_d0 ;
|
||||
wire Iin_d_d25_d0 ;
|
||||
wire Iin_d_d19_d0 ;
|
||||
wire Iin_d_d17_d0 ;
|
||||
wire Iin_d_d4_d1 ;
|
||||
wire Iin_d_d6_d1 ;
|
||||
wire Iin_d_d5_d1 ;
|
||||
wire Iin_d_d24_d1 ;
|
||||
wire Iin_d_d5_d0 ;
|
||||
wire Iin_d_d10_d0 ;
|
||||
wire Iin_d_d7_d0 ;
|
||||
wire Iin_d_d0_d1 ;
|
||||
wire Iin_d_d27_d1 ;
|
||||
wire Iin_d_d22_d0 ;
|
||||
wire Iin_d_d16_d0 ;
|
||||
wire Iin_d_d18_d0 ;
|
||||
wire Iin_d_d15_d1 ;
|
||||
wire Iin_d_d29_d1 ;
|
||||
wire Iin_d_d30_d0 ;
|
||||
wire Iin_d_d15_d0 ;
|
||||
wire Iin_d_d29_d0 ;
|
||||
wire Iin_d_d26_d1 ;
|
||||
wire Iin_d_d22_d1 ;
|
||||
wire Iin_d_d18_d1 ;
|
||||
wire Iin_d_d2_d0 ;
|
||||
wire Iin_d_d12_d1 ;
|
||||
wire Iin_d_d1_d1 ;
|
||||
wire Iin_d_d1_d0 ;
|
||||
wire Isb_in ;
|
||||
wire Iin_d_d21_d1 ;
|
||||
wire Iin_d_d19_d1 ;
|
||||
wire Iin_d_d16_d1 ;
|
||||
wire Iin_d_d14_d1 ;
|
||||
wire Iin_d_d14_d0 ;
|
||||
output Iout_d_d31_d1 ;
|
||||
wire Iin_d_d20_d0 ;
|
||||
wire Iin_d_d12_d0 ;
|
||||
|
||||
// --- instances
|
||||
TIELO_X1 Itielows0 (.y(Iout_d_d31_d1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_31_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d31_d0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,142 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0append_331_71_71_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Isupply_vss , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d_d0_d0 ;
|
||||
input Iin_d_d0_d1 ;
|
||||
input Iin_d_d1_d0 ;
|
||||
input Iin_d_d1_d1 ;
|
||||
input Iin_d_d2_d0 ;
|
||||
input Iin_d_d2_d1 ;
|
||||
input Iin_d_d3_d0 ;
|
||||
input Iin_d_d3_d1 ;
|
||||
input Iin_d_d4_d0 ;
|
||||
input Iin_d_d4_d1 ;
|
||||
input Iin_d_d5_d0 ;
|
||||
input Iin_d_d5_d1 ;
|
||||
input Iin_d_d6_d0 ;
|
||||
input Iin_d_d6_d1 ;
|
||||
input Iin_d_d7_d0 ;
|
||||
input Iin_d_d7_d1 ;
|
||||
input Iin_d_d8_d0 ;
|
||||
input Iin_d_d8_d1 ;
|
||||
input Iin_d_d9_d0 ;
|
||||
input Iin_d_d9_d1 ;
|
||||
input Iin_d_d10_d0 ;
|
||||
input Iin_d_d10_d1 ;
|
||||
input Iin_d_d11_d0 ;
|
||||
input Iin_d_d11_d1 ;
|
||||
input Iin_d_d12_d0 ;
|
||||
input Iin_d_d12_d1 ;
|
||||
input Iin_d_d13_d0 ;
|
||||
input Iin_d_d13_d1 ;
|
||||
input Iin_d_d14_d0 ;
|
||||
input Iin_d_d14_d1 ;
|
||||
input Iin_d_d15_d0 ;
|
||||
input Iin_d_d15_d1 ;
|
||||
input Iin_d_d16_d0 ;
|
||||
input Iin_d_d16_d1 ;
|
||||
input Iin_d_d17_d0 ;
|
||||
input Iin_d_d17_d1 ;
|
||||
input Iin_d_d18_d0 ;
|
||||
input Iin_d_d18_d1 ;
|
||||
input Iin_d_d19_d0 ;
|
||||
input Iin_d_d19_d1 ;
|
||||
input Iin_d_d20_d0 ;
|
||||
input Iin_d_d20_d1 ;
|
||||
input Iin_d_d21_d0 ;
|
||||
input Iin_d_d21_d1 ;
|
||||
input Iin_d_d22_d0 ;
|
||||
input Iin_d_d22_d1 ;
|
||||
input Iin_d_d23_d0 ;
|
||||
input Iin_d_d23_d1 ;
|
||||
input Iin_d_d24_d0 ;
|
||||
input Iin_d_d24_d1 ;
|
||||
input Iin_d_d25_d0 ;
|
||||
input Iin_d_d25_d1 ;
|
||||
input Iin_d_d26_d0 ;
|
||||
input Iin_d_d26_d1 ;
|
||||
input Iin_d_d27_d0 ;
|
||||
input Iin_d_d27_d1 ;
|
||||
input Iin_d_d28_d0 ;
|
||||
input Iin_d_d28_d1 ;
|
||||
input Iin_d_d29_d0 ;
|
||||
input Iin_d_d29_d1 ;
|
||||
input Iin_d_d30_d0 ;
|
||||
input Iin_d_d30_d1 ;
|
||||
|
||||
|
||||
input Isupply_vss ;
|
||||
|
||||
// -- signals ---
|
||||
wire Iin_d_d18_d0 ;
|
||||
wire Iin_d_d4_d0 ;
|
||||
wire Iin_d_d26_d1 ;
|
||||
wire Iin_d_d25_d0 ;
|
||||
wire Iin_d_d3_d0 ;
|
||||
wire Iin_d_d0_d0 ;
|
||||
wire Iin_d_d17_d1 ;
|
||||
wire Iin_d_d17_d0 ;
|
||||
wire Iin_d_d5_d1 ;
|
||||
wire Iin_d_d30_d0 ;
|
||||
wire Iin_d_d15_d1 ;
|
||||
wire Iin_d_d14_d1 ;
|
||||
output Iout_d_d31_d1 ;
|
||||
wire Iin_d_d16_d1 ;
|
||||
wire Iin_d_d4_d1 ;
|
||||
wire Iin_d_d14_d0 ;
|
||||
wire Iin_d_d6_d1 ;
|
||||
wire Iin_d_d2_d0 ;
|
||||
wire Iin_d_d19_d0 ;
|
||||
wire Iin_d_d13_d1 ;
|
||||
output Iout_d_d31_d0 ;
|
||||
wire Iin_d_d0_d1 ;
|
||||
wire Iin_d_d21_d1 ;
|
||||
wire Iin_d_d7_d0 ;
|
||||
wire Iin_d_d24_d1 ;
|
||||
wire Iin_d_d22_d0 ;
|
||||
wire Iin_d_d23_d0 ;
|
||||
wire Iin_d_d11_d0 ;
|
||||
wire Iin_d_d9_d1 ;
|
||||
wire Iin_d_d13_d0 ;
|
||||
wire Iin_d_d16_d0 ;
|
||||
wire Iin_d_d3_d1 ;
|
||||
wire Iin_d_d22_d1 ;
|
||||
wire Iin_d_d12_d1 ;
|
||||
wire Iin_d_d9_d0 ;
|
||||
wire Iin_d_d8_d0 ;
|
||||
wire Iin_d_d19_d1 ;
|
||||
wire Iin_d_d8_d1 ;
|
||||
wire Iin_d_d1_d1 ;
|
||||
wire Iin_d_d26_d0 ;
|
||||
wire Iin_d_d24_d0 ;
|
||||
wire Iin_d_d21_d0 ;
|
||||
wire Iin_d_d6_d0 ;
|
||||
wire Iin_d_d28_d0 ;
|
||||
wire Iin_d_d27_d1 ;
|
||||
wire Isb_in ;
|
||||
wire Iin_d_d15_d0 ;
|
||||
wire Iin_d_d10_d1 ;
|
||||
wire Iin_d_d25_d1 ;
|
||||
wire Iin_d_d20_d1 ;
|
||||
wire Iin_d_d20_d0 ;
|
||||
wire Iin_d_d18_d1 ;
|
||||
wire Iin_d_d1_d0 ;
|
||||
wire Iin_d_d29_d0 ;
|
||||
wire Iin_d_d28_d1 ;
|
||||
wire Iin_d_d27_d0 ;
|
||||
wire Iin_d_d2_d1 ;
|
||||
wire Iin_d_d30_d1 ;
|
||||
wire Iin_d_d12_d0 ;
|
||||
wire Iin_d_d10_d0 ;
|
||||
wire Iin_d_d23_d1 ;
|
||||
wire Iin_d_d5_d0 ;
|
||||
wire Iin_d_d29_d1 ;
|
||||
wire Iin_d_d11_d1 ;
|
||||
wire Iin_d_d7_d1 ;
|
||||
wire Isupply_vss ;
|
||||
|
||||
// --- instances
|
||||
TIELO_X1 Itielows0 (.y(Iout_d_d31_d0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_31_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d31_d1 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,115 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0append_37_724_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d1 , Iout_d_d9_d1 , Iout_d_d10_d1 , Iout_d_d11_d1 , Iout_d_d12_d1 , Iout_d_d13_d1 , Iout_d_d14_d1 , Iout_d_d15_d1 , Iout_d_d16_d1 , Iout_d_d17_d1 , Iout_d_d18_d1 , Iout_d_d19_d1 , Iout_d_d20_d1 , Iout_d_d21_d1 , Iout_d_d22_d1 , Iout_d_d23_d1 , Iout_d_d24_d1 , Iout_d_d25_d1 , Iout_d_d26_d1 , Iout_d_d27_d1 , Iout_d_d28_d1 , Iout_d_d29_d1 , Iout_d_d30_d1 , Isupply_vss , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d_d0_d0 ;
|
||||
input Iin_d_d0_d1 ;
|
||||
input Iin_d_d1_d0 ;
|
||||
input Iin_d_d1_d1 ;
|
||||
input Iin_d_d2_d0 ;
|
||||
input Iin_d_d2_d1 ;
|
||||
input Iin_d_d3_d0 ;
|
||||
input Iin_d_d3_d1 ;
|
||||
input Iin_d_d4_d0 ;
|
||||
input Iin_d_d4_d1 ;
|
||||
input Iin_d_d5_d0 ;
|
||||
input Iin_d_d5_d1 ;
|
||||
input Iin_d_d6_d0 ;
|
||||
input Iin_d_d6_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
input Isupply_vss ;
|
||||
|
||||
// -- signals ---
|
||||
wire Iin_d_d0_d1 ;
|
||||
output Iout_d_d20_d1 ;
|
||||
wire Iin_d_d6_d0 ;
|
||||
output Iout_d_d30_d1 ;
|
||||
output Iout_d_d15_d1 ;
|
||||
wire Iin_d_d5_d0 ;
|
||||
output Iout_d_d22_d1 ;
|
||||
output Iout_d_d24_d1 ;
|
||||
wire Iin_d_d4_d0 ;
|
||||
output Iout_d_d29_d1 ;
|
||||
output Iout_d_d12_d1 ;
|
||||
output Iout_d_d11_d1 ;
|
||||
wire Iin_d_d2_d0 ;
|
||||
output Iout_d_d21_d1 ;
|
||||
output Iout_d_d18_d1 ;
|
||||
wire Iin_d_d0_d0 ;
|
||||
wire Iin_d_d5_d1 ;
|
||||
output Iout_d_d27_d1 ;
|
||||
output Iout_d_d19_d1 ;
|
||||
output Iout_d_d7_d0 ;
|
||||
wire Iin_d_d2_d1 ;
|
||||
wire Iin_d_d1_d0 ;
|
||||
output Iout_d_d17_d1 ;
|
||||
wire Iin_d_d6_d1 ;
|
||||
wire Isupply_vss ;
|
||||
output Iout_d_d26_d1 ;
|
||||
output Iout_d_d14_d1 ;
|
||||
output Iout_d_d13_d1 ;
|
||||
output Iout_d_d9_d1 ;
|
||||
wire Iin_d_d1_d1 ;
|
||||
wire Iin_d_d4_d1 ;
|
||||
output Iout_d_d28_d1 ;
|
||||
output Iout_d_d16_d1 ;
|
||||
wire Isb_in ;
|
||||
output Iout_d_d25_d1 ;
|
||||
output Iout_d_d8_d1 ;
|
||||
wire Iin_d_d3_d0 ;
|
||||
output Iout_d_d23_d1 ;
|
||||
output Iout_d_d7_d1 ;
|
||||
wire Iin_d_d3_d1 ;
|
||||
output Iout_d_d10_d1 ;
|
||||
|
||||
// --- instances
|
||||
TIELO_X1 Itielows0 (.y(Iout_d_d7_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows1 (.y(Iout_d_d8_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows2 (.y(Iout_d_d9_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows3 (.y(Iout_d_d10_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows4 (.y(Iout_d_d11_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows5 (.y(Iout_d_d12_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows6 (.y(Iout_d_d13_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows7 (.y(Iout_d_d14_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows8 (.y(Iout_d_d15_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows9 (.y(Iout_d_d16_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows10 (.y(Iout_d_d17_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows11 (.y(Iout_d_d18_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows12 (.y(Iout_d_d19_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows13 (.y(Iout_d_d20_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows14 (.y(Iout_d_d21_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows15 (.y(Iout_d_d22_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows16 (.y(Iout_d_d23_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows17 (.y(Iout_d_d24_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows18 (.y(Iout_d_d25_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows19 (.y(Iout_d_d26_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows20 (.y(Iout_d_d27_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows21 (.y(Iout_d_d28_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows22 (.y(Iout_d_d29_d1 ), .vdd(vdd), .vss(vss));
|
||||
TIELO_X1 Itielows23 (.y(Iout_d_d30_d1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0vtree_37_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_324_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d7_d0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,26 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0arbiter__handshake(Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iout_d_d0 , Iout_a , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin1_d_d0 ;
|
||||
|
||||
input Iin2_d_d0 ;
|
||||
|
||||
|
||||
input Iout_a ;
|
||||
|
||||
// -- signals ---
|
||||
wire _y2_arb ;
|
||||
wire _y1_arb ;
|
||||
wire Iout_a ;
|
||||
output Iin1_a ;
|
||||
output Iout_d_d0 ;
|
||||
wire Iin1_d_d0 ;
|
||||
output Iin2_a ;
|
||||
wire Iin2_d_d0 ;
|
||||
|
||||
// --- instances
|
||||
A_2C_B_X1 Iack_cell1 (.y(Iin1_a ), .c1(Iout_a ), .c2(_y1_arb), .vdd(vdd), .vss(vss));
|
||||
ARBITER Iarbiter (.a(Iin1_d_d0 ), .b(Iin2_d_d0 ), .c(Iin2_a ), .d(Iin1_a ), .y1(_y1_arb), .y2(_y2_arb), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 Iack_cell2 (.y(Iin2_a ), .c1(Iout_a ), .c2(_y2_arb), .vdd(vdd), .vss(vss));
|
||||
OR2_X1 Ior_cell (.y(Iout_d_d0 ), .a(_y1_arb), .b(_y2_arb), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,112 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0arbtree_315_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iin6_d_d0 , Iin6_a , Iin7_d_d0 , Iin7_a , Iin8_d_d0 , Iin8_a , Iin9_d_d0 , Iin9_a , Iin10_d_d0 , Iin10_a , Iin11_d_d0 , Iin11_a , Iin12_d_d0 , Iin12_a , Iin13_d_d0 , Iin13_a , Iin14_d_d0 , Iin14_a , Iout_d_d0 , Iout_a , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin0_d_d0 ;
|
||||
|
||||
input Iin1_d_d0 ;
|
||||
|
||||
input Iin2_d_d0 ;
|
||||
|
||||
input Iin3_d_d0 ;
|
||||
|
||||
input Iin4_d_d0 ;
|
||||
|
||||
input Iin5_d_d0 ;
|
||||
|
||||
input Iin6_d_d0 ;
|
||||
|
||||
input Iin7_d_d0 ;
|
||||
|
||||
input Iin8_d_d0 ;
|
||||
|
||||
input Iin9_d_d0 ;
|
||||
|
||||
input Iin10_d_d0 ;
|
||||
|
||||
input Iin11_d_d0 ;
|
||||
|
||||
input Iin12_d_d0 ;
|
||||
|
||||
input Iin13_d_d0 ;
|
||||
|
||||
input Iin14_d_d0 ;
|
||||
|
||||
|
||||
input Iout_a ;
|
||||
|
||||
// -- signals ---
|
||||
output Iin14_a ;
|
||||
output Iin11_a ;
|
||||
wire Itmp24_d_d0 ;
|
||||
wire Itmp23_d_d0 ;
|
||||
output Iin7_a ;
|
||||
wire Itmp24_a ;
|
||||
wire Itmp17_a ;
|
||||
wire Iout_a ;
|
||||
wire Itmp27_d_d0 ;
|
||||
wire Iin8_d_d0 ;
|
||||
wire Iin5_d_d0 ;
|
||||
output Iin1_a ;
|
||||
wire Itmp16_a ;
|
||||
output Iin12_a ;
|
||||
wire Iin0_d_d0 ;
|
||||
output Iin9_a ;
|
||||
wire Itmp28_d_d0 ;
|
||||
wire Itmp26_a ;
|
||||
wire Itmp21_a ;
|
||||
wire Itmp17_d_d0 ;
|
||||
wire Itmp15_a ;
|
||||
wire Itmp25_a ;
|
||||
output Iin4_a ;
|
||||
output Iin8_a ;
|
||||
output Iin0_a ;
|
||||
wire Itmp20_a ;
|
||||
wire Itmp18_a ;
|
||||
wire Iin2_d_d0 ;
|
||||
output Iin2_a ;
|
||||
wire Itmp21_d_d0 ;
|
||||
wire Itmp16_d_d0 ;
|
||||
wire Iin12_d_d0 ;
|
||||
wire Itmp19_a ;
|
||||
wire Itmp15_d_d0 ;
|
||||
wire Iin4_d_d0 ;
|
||||
wire Itmp23_a ;
|
||||
output Iin10_a ;
|
||||
output Iin3_a ;
|
||||
wire Itmp28_a ;
|
||||
wire Itmp26_d_d0 ;
|
||||
output Iin13_a ;
|
||||
output Iout_d_d0 ;
|
||||
wire Iin6_d_d0 ;
|
||||
wire Iin1_d_d0 ;
|
||||
wire Iin14_d_d0 ;
|
||||
wire Itmp25_d_d0 ;
|
||||
wire Itmp20_d_d0 ;
|
||||
wire Iin9_d_d0 ;
|
||||
output Iin5_a ;
|
||||
wire Itmp19_d_d0 ;
|
||||
wire Iin7_d_d0 ;
|
||||
output Iin6_a ;
|
||||
wire Iin13_d_d0 ;
|
||||
wire Iin10_d_d0 ;
|
||||
wire Iin3_d_d0 ;
|
||||
wire Itmp27_a ;
|
||||
wire Iin11_d_d0 ;
|
||||
wire Itmp18_d_d0 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0 (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp15_d_d0 ), .Iout_a (Itmp15_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs1 (.Iin1_d_d0 (Iin2_d_d0 ), .Iin1_a (Iin2_a ), .Iin2_d_d0 (Iin3_d_d0 ), .Iin2_a (Iin3_a ), .Iout_d_d0 (Itmp16_d_d0 ), .Iout_a (Itmp16_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs2 (.Iin1_d_d0 (Iin4_d_d0 ), .Iin1_a (Iin4_a ), .Iin2_d_d0 (Iin5_d_d0 ), .Iin2_a (Iin5_a ), .Iout_d_d0 (Itmp17_d_d0 ), .Iout_a (Itmp17_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs3 (.Iin1_d_d0 (Iin6_d_d0 ), .Iin1_a (Iin6_a ), .Iin2_d_d0 (Iin7_d_d0 ), .Iin2_a (Iin7_a ), .Iout_d_d0 (Itmp18_d_d0 ), .Iout_a (Itmp18_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs4 (.Iin1_d_d0 (Iin8_d_d0 ), .Iin1_a (Iin8_a ), .Iin2_d_d0 (Iin9_d_d0 ), .Iin2_a (Iin9_a ), .Iout_d_d0 (Itmp19_d_d0 ), .Iout_a (Itmp19_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs5 (.Iin1_d_d0 (Iin10_d_d0 ), .Iin1_a (Iin10_a ), .Iin2_d_d0 (Iin11_d_d0 ), .Iin2_a (Iin11_a ), .Iout_d_d0 (Itmp20_d_d0 ), .Iout_a (Itmp20_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs6 (.Iin1_d_d0 (Iin12_d_d0 ), .Iin1_a (Iin12_a ), .Iin2_d_d0 (Iin13_d_d0 ), .Iin2_a (Iin13_a ), .Iout_d_d0 (Itmp21_d_d0 ), .Iout_a (Itmp21_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs7 (.Iin1_d_d0 (Itmp15_d_d0 ), .Iin1_a (Itmp15_a ), .Iin2_d_d0 (Itmp16_d_d0 ), .Iin2_a (Itmp16_a ), .Iout_d_d0 (Itmp23_d_d0 ), .Iout_a (Itmp23_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs8 (.Iin1_d_d0 (Itmp17_d_d0 ), .Iin1_a (Itmp17_a ), .Iin2_d_d0 (Itmp18_d_d0 ), .Iin2_a (Itmp18_a ), .Iout_d_d0 (Itmp24_d_d0 ), .Iout_a (Itmp24_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs9 (.Iin1_d_d0 (Itmp19_d_d0 ), .Iin1_a (Itmp19_a ), .Iin2_d_d0 (Itmp20_d_d0 ), .Iin2_a (Itmp20_a ), .Iout_d_d0 (Itmp25_d_d0 ), .Iout_a (Itmp25_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs10 (.Iin1_d_d0 (Itmp21_d_d0 ), .Iin1_a (Itmp21_a ), .Iin2_d_d0 (Iin14_d_d0 ), .Iin2_a (Iin14_a ), .Iout_d_d0 (Itmp26_d_d0 ), .Iout_a (Itmp26_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs11 (.Iin1_d_d0 (Itmp23_d_d0 ), .Iin1_a (Itmp23_a ), .Iin2_d_d0 (Itmp24_d_d0 ), .Iin2_a (Itmp24_a ), .Iout_d_d0 (Itmp27_d_d0 ), .Iout_a (Itmp27_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs12 (.Iin1_d_d0 (Itmp25_d_d0 ), .Iin1_a (Itmp25_a ), .Iin2_d_d0 (Itmp26_d_d0 ), .Iin2_a (Itmp26_a ), .Iout_d_d0 (Itmp28_d_d0 ), .Iout_a (Itmp28_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs13 (.Iin1_d_d0 (Itmp27_d_d0 ), .Iin1_a (Itmp27_a ), .Iin2_d_d0 (Itmp28_d_d0 ), .Iin2_a (Itmp28_a ), .Iout_d_d0 (Iout_d_d0 ), .Iout_a (Iout_a ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,49 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0arbtree_36_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iout_d_d0 , Iout_a , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin0_d_d0 ;
|
||||
|
||||
input Iin1_d_d0 ;
|
||||
|
||||
input Iin2_d_d0 ;
|
||||
|
||||
input Iin3_d_d0 ;
|
||||
|
||||
input Iin4_d_d0 ;
|
||||
|
||||
input Iin5_d_d0 ;
|
||||
|
||||
|
||||
input Iout_a ;
|
||||
|
||||
// -- signals ---
|
||||
output Iin3_a ;
|
||||
wire Itmp10_a ;
|
||||
wire Iin5_d_d0 ;
|
||||
wire Iin1_d_d0 ;
|
||||
output Iin2_a ;
|
||||
output Iout_d_d0 ;
|
||||
wire Iin3_d_d0 ;
|
||||
wire Iin2_d_d0 ;
|
||||
wire Iin0_d_d0 ;
|
||||
output Iin1_a ;
|
||||
wire Itmp6_d_d0 ;
|
||||
wire Itmp9_a ;
|
||||
output Iin5_a ;
|
||||
output Iin4_a ;
|
||||
wire Iin4_d_d0 ;
|
||||
wire Itmp10_d_d0 ;
|
||||
wire Itmp7_d_d0 ;
|
||||
wire Itmp6_a ;
|
||||
output Iin0_a ;
|
||||
wire Iout_a ;
|
||||
wire Itmp9_d_d0 ;
|
||||
wire Itmp7_a ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0 (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp6_d_d0 ), .Iout_a (Itmp6_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs1 (.Iin1_d_d0 (Iin2_d_d0 ), .Iin1_a (Iin2_a ), .Iin2_d_d0 (Iin3_d_d0 ), .Iin2_a (Iin3_a ), .Iout_d_d0 (Itmp7_d_d0 ), .Iout_a (Itmp7_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs2 (.Iin1_d_d0 (Iin4_d_d0 ), .Iin1_a (Iin4_a ), .Iin2_d_d0 (Iin5_d_d0 ), .Iin2_a (Iin5_a ), .Iout_d_d0 (Itmp10_d_d0 ), .Iout_a (Itmp10_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs3 (.Iin1_d_d0 (Itmp6_d_d0 ), .Iin1_a (Itmp6_a ), .Iin2_d_d0 (Itmp7_d_d0 ), .Iin2_a (Itmp7_a ), .Iout_d_d0 (Itmp9_d_d0 ), .Iout_a (Itmp9_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs4 (.Iin1_d_d0 (Itmp9_d_d0 ), .Iin1_a (Itmp9_a ), .Iin2_d_d0 (Itmp10_d_d0 ), .Iin2_a (Itmp10_a ), .Iout_d_d0 (Iout_d_d0 ), .Iout_a (Iout_a ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,373 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0bd2qdi_332_74_72_4(Iin_d0 , Iin_d1 , Iin_d2 , Iin_d3 , Iin_d4 , Iin_d5 , Iin_d6 , Iin_d7 , Iin_d8 , Iin_d9 , Iin_d10 , Iin_d11 , Iin_d12 , Iin_d13 , Iin_d14 , Iin_d15 , Iin_d16 , Iin_d17 , Iin_d18 , Iin_d19 , Iin_d20 , Iin_d21 , Iin_d22 , Iin_d23 , Iin_d24 , Iin_d25 , Iin_d26 , Iin_d27 , Iin_d28 , Iin_d29 , Iin_d30 , Iin_d31 , Iin_r , Iin_a , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Iout_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Iout_a , Iout_v , Idly_cfg0 , Idly_cfg1 , Idly_cfg2 , Idly_cfg3 , Idly_cfg20 , Idly_cfg21 , reset_B, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d0 ;
|
||||
input Iin_d1 ;
|
||||
input Iin_d2 ;
|
||||
input Iin_d3 ;
|
||||
input Iin_d4 ;
|
||||
input Iin_d5 ;
|
||||
input Iin_d6 ;
|
||||
input Iin_d7 ;
|
||||
input Iin_d8 ;
|
||||
input Iin_d9 ;
|
||||
input Iin_d10 ;
|
||||
input Iin_d11 ;
|
||||
input Iin_d12 ;
|
||||
input Iin_d13 ;
|
||||
input Iin_d14 ;
|
||||
input Iin_d15 ;
|
||||
input Iin_d16 ;
|
||||
input Iin_d17 ;
|
||||
input Iin_d18 ;
|
||||
input Iin_d19 ;
|
||||
input Iin_d20 ;
|
||||
input Iin_d21 ;
|
||||
input Iin_d22 ;
|
||||
input Iin_d23 ;
|
||||
input Iin_d24 ;
|
||||
input Iin_d25 ;
|
||||
input Iin_d26 ;
|
||||
input Iin_d27 ;
|
||||
input Iin_d28 ;
|
||||
input Iin_d29 ;
|
||||
input Iin_d30 ;
|
||||
input Iin_d31 ;
|
||||
input Iin_r ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
input Iout_a ;
|
||||
input Iout_v ;
|
||||
input Idly_cfg0 ;
|
||||
input Idly_cfg1 ;
|
||||
input Idly_cfg2 ;
|
||||
input Idly_cfg3 ;
|
||||
input Idly_cfg20 ;
|
||||
input Idly_cfg21 ;
|
||||
input reset_B;
|
||||
|
||||
// -- signals ---
|
||||
output Iout_d_d13_d1 ;
|
||||
wire I_inB9 ;
|
||||
wire I_inB10 ;
|
||||
output Iout_d_d4_d1 ;
|
||||
wire I_inB6 ;
|
||||
wire I_inB20 ;
|
||||
output Iout_d_d8_d0 ;
|
||||
output Iout_d_d31_d0 ;
|
||||
wire _reqX ;
|
||||
wire Idly_cfg21 ;
|
||||
wire _req_slowfall ;
|
||||
wire Ien_buf_out0 ;
|
||||
wire I_inB21 ;
|
||||
wire If_buf_func31_c2 ;
|
||||
output Iout_d_d24_d1 ;
|
||||
output Iout_d_d4_d0 ;
|
||||
output Iout_d_d16_d1 ;
|
||||
output Iout_d_d21_d0 ;
|
||||
output Iout_d_d23_d0 ;
|
||||
output Iout_d_d20_d1 ;
|
||||
output Iout_d_d14_d1 ;
|
||||
output Iout_d_d5_d1 ;
|
||||
wire Iin_d11 ;
|
||||
wire Iin_d20 ;
|
||||
wire Iin_d12 ;
|
||||
wire Iin_d15 ;
|
||||
wire I_inB25 ;
|
||||
wire Iout_a ;
|
||||
wire Iin_d27 ;
|
||||
output Iout_d_d12_d0 ;
|
||||
output Iout_d_d27_d1 ;
|
||||
output Iout_d_d5_d0 ;
|
||||
output Iout_d_d6_d0 ;
|
||||
output Iout_d_d25_d0 ;
|
||||
wire I_reqXX0 ;
|
||||
output Iout_d_d25_d1 ;
|
||||
wire Idly_cfg2 ;
|
||||
wire Iin_d22 ;
|
||||
wire Iin_r ;
|
||||
wire Iin_d2 ;
|
||||
wire I_inB8 ;
|
||||
output Iout_d_d15_d1 ;
|
||||
wire Iin_d29 ;
|
||||
output Iout_d_d1_d0 ;
|
||||
output Iout_d_d16_d0 ;
|
||||
wire reset_B;
|
||||
output Iout_d_d15_d0 ;
|
||||
output Iout_d_d19_d0 ;
|
||||
output Iout_d_d24_d0 ;
|
||||
wire Idly2_out ;
|
||||
wire I_inB2 ;
|
||||
wire Iin_d8 ;
|
||||
wire Iin_d7 ;
|
||||
output Iout_d_d9_d0 ;
|
||||
output Iout_d_d19_d1 ;
|
||||
wire Iin_d4 ;
|
||||
wire I_inB5 ;
|
||||
output Iout_d_d7_d0 ;
|
||||
output Iout_d_d27_d0 ;
|
||||
output Iout_d_d28_d0 ;
|
||||
wire I_reset_BXX0 ;
|
||||
output Iin_a ;
|
||||
output Iout_d_d20_d0 ;
|
||||
wire I_inB4 ;
|
||||
output Iout_d_d10_d0 ;
|
||||
wire I_inB7 ;
|
||||
output Iout_d_d14_d0 ;
|
||||
output Iout_d_d29_d0 ;
|
||||
output Iout_d_d3_d0 ;
|
||||
output Iout_d_d29_d1 ;
|
||||
output Iout_d_d28_d1 ;
|
||||
wire Iin_d14 ;
|
||||
wire I_inB31 ;
|
||||
output Iout_d_d11_d0 ;
|
||||
wire Iout_v ;
|
||||
wire I_inB12 ;
|
||||
output Iout_d_d21_d1 ;
|
||||
wire Iin_d5 ;
|
||||
output Iout_d_d13_d0 ;
|
||||
output Iout_d_d1_d1 ;
|
||||
wire I_inB22 ;
|
||||
wire Iin_d24 ;
|
||||
output Iout_d_d26_d1 ;
|
||||
wire Idly_cfg0 ;
|
||||
wire I_inB11 ;
|
||||
wire I_inB27 ;
|
||||
wire I_inB28 ;
|
||||
output Iout_d_d18_d0 ;
|
||||
wire I_inB0 ;
|
||||
wire Iin_d10 ;
|
||||
wire I_inB19 ;
|
||||
wire I_inB30 ;
|
||||
output Iout_d_d26_d0 ;
|
||||
wire Iin_d13 ;
|
||||
wire I_inB15 ;
|
||||
wire Iin_d28 ;
|
||||
output Iout_d_d10_d1 ;
|
||||
output Iout_d_d11_d1 ;
|
||||
wire I_inB16 ;
|
||||
wire Iin_d18 ;
|
||||
wire _en ;
|
||||
wire Iin_d0 ;
|
||||
wire Iin_d3 ;
|
||||
wire I_inB26 ;
|
||||
output Iout_d_d17_d0 ;
|
||||
output Iout_d_d23_d1 ;
|
||||
wire Iin_d1 ;
|
||||
wire Iin_d23 ;
|
||||
wire Iin_d31 ;
|
||||
output Iout_d_d3_d1 ;
|
||||
wire Iin_d6 ;
|
||||
wire _out_a_B ;
|
||||
wire Iin_d25 ;
|
||||
output Iout_d_d0_d1 ;
|
||||
output Iout_d_d2_d1 ;
|
||||
wire I_inB13 ;
|
||||
output Iout_d_d0_d0 ;
|
||||
output Iout_d_d7_d1 ;
|
||||
output Iout_d_d12_d1 ;
|
||||
wire I_inB1 ;
|
||||
wire Iin_d21 ;
|
||||
output Iout_d_d6_d1 ;
|
||||
output Iout_d_d30_d1 ;
|
||||
wire _req ;
|
||||
wire I_inB18 ;
|
||||
output Iout_d_d2_d0 ;
|
||||
output Iout_d_d17_d1 ;
|
||||
wire I_inB14 ;
|
||||
output Iout_d_d22_d0 ;
|
||||
wire Idly_cfg1 ;
|
||||
wire _reset_BX ;
|
||||
wire Idly_cfg20 ;
|
||||
wire I_inB24 ;
|
||||
wire Iin_d26 ;
|
||||
wire I_inB29 ;
|
||||
output Iout_d_d18_d1 ;
|
||||
wire Iin_d17 ;
|
||||
output Iout_d_d8_d1 ;
|
||||
output Iout_d_d22_d1 ;
|
||||
wire Iin_d16 ;
|
||||
output Iout_d_d30_d0 ;
|
||||
output Iout_d_d31_d1 ;
|
||||
wire Idly_cfg3 ;
|
||||
wire Iin_d9 ;
|
||||
wire I_inB17 ;
|
||||
output Iout_d_d9_d1 ;
|
||||
wire I_inB3 ;
|
||||
wire Iin_d19 ;
|
||||
wire I_inB23 ;
|
||||
wire Iin_d30 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(_req_slowfall), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0delayprog_34_4 Idly (.out(_req), .in(Iin_r ), .Is0 (Idly_cfg0 ), .Is1 (Idly_cfg1 ), .Is2 (Idly_cfg2 ), .Is3 (Idly_cfg3 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0delayprog_32_4 Idly2 (.out(Idly2_out ), .in(_reqX), .Is0 (Idly_cfg20 ), .Is1 (Idly_cfg21 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X4 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs0 (.y(I_inB0 ), .a(Iin_d0 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs1 (.y(I_inB1 ), .a(Iin_d1 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs2 (.y(I_inB2 ), .a(Iin_d2 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs3 (.y(I_inB3 ), .a(Iin_d3 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs4 (.y(I_inB4 ), .a(Iin_d4 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs5 (.y(I_inB5 ), .a(Iin_d5 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs6 (.y(I_inB6 ), .a(Iin_d6 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs7 (.y(I_inB7 ), .a(Iin_d7 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs8 (.y(I_inB8 ), .a(Iin_d8 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs9 (.y(I_inB9 ), .a(Iin_d9 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs10 (.y(I_inB10 ), .a(Iin_d10 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs11 (.y(I_inB11 ), .a(Iin_d11 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs12 (.y(I_inB12 ), .a(Iin_d12 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs13 (.y(I_inB13 ), .a(Iin_d13 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs14 (.y(I_inB14 ), .a(Iin_d14 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs15 (.y(I_inB15 ), .a(Iin_d15 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs16 (.y(I_inB16 ), .a(Iin_d16 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs17 (.y(I_inB17 ), .a(Iin_d17 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs18 (.y(I_inB18 ), .a(Iin_d18 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs19 (.y(I_inB19 ), .a(Iin_d19 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs20 (.y(I_inB20 ), .a(Iin_d20 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs21 (.y(I_inB21 ), .a(Iin_d21 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs22 (.y(I_inB22 ), .a(Iin_d22 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs23 (.y(I_inB23 ), .a(Iin_d23 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs24 (.y(I_inB24 ), .a(Iin_d24 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs25 (.y(I_inB25 ), .a(Iin_d25 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs26 (.y(I_inB26 ), .a(Iin_d26 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs27 (.y(I_inB27 ), .a(Iin_d27 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs28 (.y(I_inB28 ), .a(Iin_d28 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs29 (.y(I_inB29 ), .a(Iin_d29 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs30 (.y(I_inB30 ), .a(Iin_d30 ), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iinput_invs31 (.y(I_inB31 ), .a(Iin_d31 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (If_buf_func31_c2 ), .vdd(vdd), .vss(vss));
|
||||
OR2_X1 Ireq_dly_or (.y(_req_slowfall), .a(_reqX), .b(Idly2_out ), .vdd(vdd), .vss(vss));
|
||||
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireq_bufarray (.in(_reqX), .Iout0 (I_reqXX0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X4 Ireq_buf (.y(_reqX), .a(_req), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB0 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB1 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB2 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB3 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB4 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB5 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB6 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func7 (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB7 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func8 (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB8 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func9 (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB9 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func10 (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB10 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func11 (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB11 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func12 (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB12 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func13 (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB13 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func14 (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB14 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func15 (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB15 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func16 (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB16 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func17 (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB17 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func18 (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB18 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func19 (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB19 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func20 (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB20 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func21 (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB21 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func22 (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB22 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func23 (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB23 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func24 (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB24 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func25 (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB25 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func26 (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB26 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func27 (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB27 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func28 (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB28 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func29 (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB29 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func30 (.y(Iout_d_d30_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB30 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 If_buf_func31 (.y(Iout_d_d31_d0 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(I_inB31 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d0 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d1 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d2 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d3 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d4 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d5 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d6 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func7 (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d7 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func8 (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d8 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func9 (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d9 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func10 (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d10 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func11 (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d11 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func12 (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d12 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func13 (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d13 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func14 (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d14 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func15 (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d15 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func16 (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d16 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func17 (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d17 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func18 (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d18 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func19 (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d19 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func20 (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d20 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func21 (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d21 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func22 (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d22 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func23 (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d23 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func24 (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d24 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func25 (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d25 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func26 (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d26 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func27 (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d27 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func28 (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d28 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func29 (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d29 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func30 (.y(Iout_d_d30_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d30 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C2N_RB_X4 It_buf_func31 (.y(Iout_d_d31_d1 ), .c1(Ien_buf_out0 ), .c2(If_buf_func31_c2 ), .n1(Iin_d31 ), .n2(I_reqXX0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,164 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0buffer_313_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d_d0_d0 ;
|
||||
input Iin_d_d0_d1 ;
|
||||
input Iin_d_d1_d0 ;
|
||||
input Iin_d_d1_d1 ;
|
||||
input Iin_d_d2_d0 ;
|
||||
input Iin_d_d2_d1 ;
|
||||
input Iin_d_d3_d0 ;
|
||||
input Iin_d_d3_d1 ;
|
||||
input Iin_d_d4_d0 ;
|
||||
input Iin_d_d4_d1 ;
|
||||
input Iin_d_d5_d0 ;
|
||||
input Iin_d_d5_d1 ;
|
||||
input Iin_d_d6_d0 ;
|
||||
input Iin_d_d6_d1 ;
|
||||
input Iin_d_d7_d0 ;
|
||||
input Iin_d_d7_d1 ;
|
||||
input Iin_d_d8_d0 ;
|
||||
input Iin_d_d8_d1 ;
|
||||
input Iin_d_d9_d0 ;
|
||||
input Iin_d_d9_d1 ;
|
||||
input Iin_d_d10_d0 ;
|
||||
input Iin_d_d10_d1 ;
|
||||
input Iin_d_d11_d0 ;
|
||||
input Iin_d_d11_d1 ;
|
||||
input Iin_d_d12_d0 ;
|
||||
input Iin_d_d12_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
input Iout_a ;
|
||||
input Iout_v ;
|
||||
input reset_B;
|
||||
|
||||
// -- signals ---
|
||||
wire Iin_d_d10_d1 ;
|
||||
wire Iin_d_d3_d1 ;
|
||||
wire Iin_d_d9_d0 ;
|
||||
wire _reset_BX ;
|
||||
output Iout_d_d3_d0 ;
|
||||
wire Ien_buf_out0 ;
|
||||
output Iout_d_d2_d0 ;
|
||||
output Iout_d_d6_d1 ;
|
||||
wire Iin_d_d0_d1 ;
|
||||
wire Iin_d_d9_d1 ;
|
||||
output Iout_d_d12_d1 ;
|
||||
output Iout_d_d8_d1 ;
|
||||
output Iout_d_d7_d1 ;
|
||||
wire Iin_d_d6_d0 ;
|
||||
output Iout_d_d8_d0 ;
|
||||
output Iout_d_d5_d0 ;
|
||||
wire Iout_v ;
|
||||
wire _en ;
|
||||
output Iin_a ;
|
||||
output Iout_d_d12_d0 ;
|
||||
output Iout_d_d10_d0 ;
|
||||
wire Iout_a ;
|
||||
wire Iin_d_d8_d0 ;
|
||||
output Iout_d_d9_d1 ;
|
||||
wire Iin_d_d4_d1 ;
|
||||
wire Iin_d_d0_d0 ;
|
||||
output Iout_d_d0_d1 ;
|
||||
output Iout_d_d5_d1 ;
|
||||
output Iout_d_d1_d1 ;
|
||||
wire Iin_d_d12_d1 ;
|
||||
wire Iin_d_d1_d0 ;
|
||||
output Iout_d_d11_d0 ;
|
||||
output Iout_d_d10_d1 ;
|
||||
wire Iin_d_d12_d0 ;
|
||||
wire Iin_d_d10_d0 ;
|
||||
output Iout_d_d4_d0 ;
|
||||
wire reset_B;
|
||||
wire Iin_d_d5_d0 ;
|
||||
output Iout_d_d3_d1 ;
|
||||
output Iout_d_d2_d1 ;
|
||||
wire _in_v ;
|
||||
output Iout_d_d6_d0 ;
|
||||
output Iout_d_d0_d0 ;
|
||||
wire _out_a_B ;
|
||||
wire Iin_d_d6_d1 ;
|
||||
wire Iin_d_d2_d1 ;
|
||||
wire Iin_d_d8_d1 ;
|
||||
wire Iin_d_d4_d0 ;
|
||||
wire I_out_a_BX0 ;
|
||||
output Iout_d_d4_d1 ;
|
||||
wire Iin_d_d11_d0 ;
|
||||
wire Iin_d_d7_d1 ;
|
||||
wire Iin_d_d3_d0 ;
|
||||
wire Iin_d_d1_d1 ;
|
||||
output Iout_d_d11_d1 ;
|
||||
wire I_reset_BXX0 ;
|
||||
output Iin_v ;
|
||||
output Iout_d_d9_d0 ;
|
||||
wire Iin_d_d7_d0 ;
|
||||
wire Iin_d_d2_d0 ;
|
||||
output Iout_d_d7_d0 ;
|
||||
output Iout_d_d1_d0 ;
|
||||
wire Iin_d_d11_d1 ;
|
||||
wire Iin_d_d5_d1 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X4 Iin_v_buf (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0vtree_313_4 Ivc (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
|
||||
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_326_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func7 (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func8 (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func9 (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func10 (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func11 (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func12 (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func7 (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func8 (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func9 (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func10 (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func11 (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func12 (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,324 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0buffer_329_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d_d0_d0 ;
|
||||
input Iin_d_d0_d1 ;
|
||||
input Iin_d_d1_d0 ;
|
||||
input Iin_d_d1_d1 ;
|
||||
input Iin_d_d2_d0 ;
|
||||
input Iin_d_d2_d1 ;
|
||||
input Iin_d_d3_d0 ;
|
||||
input Iin_d_d3_d1 ;
|
||||
input Iin_d_d4_d0 ;
|
||||
input Iin_d_d4_d1 ;
|
||||
input Iin_d_d5_d0 ;
|
||||
input Iin_d_d5_d1 ;
|
||||
input Iin_d_d6_d0 ;
|
||||
input Iin_d_d6_d1 ;
|
||||
input Iin_d_d7_d0 ;
|
||||
input Iin_d_d7_d1 ;
|
||||
input Iin_d_d8_d0 ;
|
||||
input Iin_d_d8_d1 ;
|
||||
input Iin_d_d9_d0 ;
|
||||
input Iin_d_d9_d1 ;
|
||||
input Iin_d_d10_d0 ;
|
||||
input Iin_d_d10_d1 ;
|
||||
input Iin_d_d11_d0 ;
|
||||
input Iin_d_d11_d1 ;
|
||||
input Iin_d_d12_d0 ;
|
||||
input Iin_d_d12_d1 ;
|
||||
input Iin_d_d13_d0 ;
|
||||
input Iin_d_d13_d1 ;
|
||||
input Iin_d_d14_d0 ;
|
||||
input Iin_d_d14_d1 ;
|
||||
input Iin_d_d15_d0 ;
|
||||
input Iin_d_d15_d1 ;
|
||||
input Iin_d_d16_d0 ;
|
||||
input Iin_d_d16_d1 ;
|
||||
input Iin_d_d17_d0 ;
|
||||
input Iin_d_d17_d1 ;
|
||||
input Iin_d_d18_d0 ;
|
||||
input Iin_d_d18_d1 ;
|
||||
input Iin_d_d19_d0 ;
|
||||
input Iin_d_d19_d1 ;
|
||||
input Iin_d_d20_d0 ;
|
||||
input Iin_d_d20_d1 ;
|
||||
input Iin_d_d21_d0 ;
|
||||
input Iin_d_d21_d1 ;
|
||||
input Iin_d_d22_d0 ;
|
||||
input Iin_d_d22_d1 ;
|
||||
input Iin_d_d23_d0 ;
|
||||
input Iin_d_d23_d1 ;
|
||||
input Iin_d_d24_d0 ;
|
||||
input Iin_d_d24_d1 ;
|
||||
input Iin_d_d25_d0 ;
|
||||
input Iin_d_d25_d1 ;
|
||||
input Iin_d_d26_d0 ;
|
||||
input Iin_d_d26_d1 ;
|
||||
input Iin_d_d27_d0 ;
|
||||
input Iin_d_d27_d1 ;
|
||||
input Iin_d_d28_d0 ;
|
||||
input Iin_d_d28_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
input Iout_a ;
|
||||
input Iout_v ;
|
||||
input reset_B;
|
||||
|
||||
// -- signals ---
|
||||
output Iout_d_d4_d1 ;
|
||||
wire Iin_d_d17_d1 ;
|
||||
wire Iout_a ;
|
||||
output Iout_d_d3_d0 ;
|
||||
output Iout_d_d13_d1 ;
|
||||
output Iout_d_d5_d1 ;
|
||||
wire Iin_d_d19_d1 ;
|
||||
wire Iin_d_d5_d0 ;
|
||||
output Iout_d_d15_d0 ;
|
||||
output Iout_d_d6_d0 ;
|
||||
output Iout_d_d23_d1 ;
|
||||
wire Ien_buf_out0 ;
|
||||
wire I_out_a_BX0 ;
|
||||
output Iout_d_d24_d0 ;
|
||||
wire Iin_d_d26_d0 ;
|
||||
wire Iin_d_d8_d0 ;
|
||||
wire Iin_d_d2_d0 ;
|
||||
output Iout_d_d19_d1 ;
|
||||
output Iout_d_d14_d1 ;
|
||||
wire I_reset_BXX0 ;
|
||||
output Iout_d_d11_d1 ;
|
||||
wire Iin_d_d23_d0 ;
|
||||
wire Iin_d_d22_d0 ;
|
||||
wire Iin_d_d16_d0 ;
|
||||
wire Iin_d_d2_d1 ;
|
||||
output Iout_d_d25_d0 ;
|
||||
output Iout_d_d16_d0 ;
|
||||
output Iout_d_d24_d1 ;
|
||||
output Iout_d_d16_d1 ;
|
||||
wire Iin_d_d27_d0 ;
|
||||
wire Iin_d_d15_d1 ;
|
||||
wire Iin_d_d13_d1 ;
|
||||
wire Iin_d_d0_d1 ;
|
||||
wire Iout_v ;
|
||||
output Iout_d_d28_d1 ;
|
||||
output Iout_d_d20_d1 ;
|
||||
output Iout_d_d6_d1 ;
|
||||
wire Iin_d_d13_d0 ;
|
||||
wire Iin_d_d12_d1 ;
|
||||
output Iout_d_d27_d0 ;
|
||||
output Iout_d_d20_d0 ;
|
||||
output Iout_d_d3_d1 ;
|
||||
wire Iin_d_d28_d1 ;
|
||||
wire Iin_d_d8_d1 ;
|
||||
wire Iin_d_d7_d1 ;
|
||||
wire _en ;
|
||||
output Iout_d_d21_d1 ;
|
||||
wire Iin_d_d10_d0 ;
|
||||
output Iout_d_d17_d0 ;
|
||||
output Iout_d_d1_d0 ;
|
||||
wire Iin_d_d19_d0 ;
|
||||
output Iout_d_d9_d1 ;
|
||||
wire Iin_d_d18_d1 ;
|
||||
output Iout_d_d9_d0 ;
|
||||
output Iout_d_d0_d1 ;
|
||||
wire reset_B;
|
||||
wire Iin_d_d23_d1 ;
|
||||
wire Iin_d_d22_d1 ;
|
||||
wire Iin_d_d18_d0 ;
|
||||
wire Iin_d_d17_d0 ;
|
||||
wire Iin_d_d7_d0 ;
|
||||
wire Iin_d_d21_d1 ;
|
||||
wire Iin_d_d1_d1 ;
|
||||
output Iout_d_d11_d0 ;
|
||||
output Iout_d_d22_d1 ;
|
||||
wire Iin_d_d16_d1 ;
|
||||
output Iout_d_d4_d0 ;
|
||||
output Iout_d_d2_d0 ;
|
||||
wire Iin_d_d21_d0 ;
|
||||
output Iout_d_d14_d0 ;
|
||||
output Iout_d_d10_d0 ;
|
||||
wire Iin_d_d9_d0 ;
|
||||
wire Iin_d_d6_d0 ;
|
||||
wire Iin_d_d4_d1 ;
|
||||
output Iin_a ;
|
||||
output Iout_d_d18_d0 ;
|
||||
wire Iin_d_d25_d1 ;
|
||||
wire Iin_d_d14_d1 ;
|
||||
wire Iin_d_d3_d1 ;
|
||||
output Iout_d_d19_d0 ;
|
||||
output Iout_d_d25_d1 ;
|
||||
wire Iin_d_d24_d1 ;
|
||||
wire _in_v ;
|
||||
wire Iin_d_d27_d1 ;
|
||||
wire Iin_d_d9_d1 ;
|
||||
output Iout_d_d8_d0 ;
|
||||
output Iout_d_d13_d0 ;
|
||||
output Iout_d_d5_d0 ;
|
||||
output Iout_d_d27_d1 ;
|
||||
output Iout_d_d12_d1 ;
|
||||
wire Iin_d_d14_d0 ;
|
||||
wire Iin_d_d6_d1 ;
|
||||
wire Iin_d_d4_d0 ;
|
||||
wire Iin_d_d24_d0 ;
|
||||
wire Iin_d_d20_d0 ;
|
||||
wire Iin_d_d11_d0 ;
|
||||
output Iout_d_d23_d0 ;
|
||||
output Iout_d_d22_d0 ;
|
||||
output Iout_d_d21_d0 ;
|
||||
output Iout_d_d12_d0 ;
|
||||
output Iout_d_d26_d1 ;
|
||||
output Iout_d_d15_d1 ;
|
||||
output Iout_d_d1_d1 ;
|
||||
wire Iin_d_d26_d1 ;
|
||||
output Iout_d_d26_d0 ;
|
||||
output Iout_d_d2_d1 ;
|
||||
wire Iin_d_d12_d0 ;
|
||||
wire Iin_d_d11_d1 ;
|
||||
wire Iin_d_d5_d1 ;
|
||||
wire _reset_BX ;
|
||||
output Iout_d_d28_d0 ;
|
||||
output Iout_d_d0_d0 ;
|
||||
output Iout_d_d18_d1 ;
|
||||
wire Iin_d_d25_d0 ;
|
||||
wire Iin_d_d3_d0 ;
|
||||
wire Iin_d_d1_d0 ;
|
||||
wire _out_a_B ;
|
||||
output Iout_d_d7_d0 ;
|
||||
output Iout_d_d8_d1 ;
|
||||
output Iout_d_d7_d1 ;
|
||||
wire Iin_d_d20_d1 ;
|
||||
wire Iin_d_d15_d0 ;
|
||||
wire Iin_d_d0_d0 ;
|
||||
output Iin_v ;
|
||||
output Iout_d_d17_d1 ;
|
||||
output Iout_d_d10_d1 ;
|
||||
wire Iin_d_d28_d0 ;
|
||||
wire Iin_d_d10_d1 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X4 Iin_v_buf (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0vtree_329_4 Ivc (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
|
||||
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_358_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func7 (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func8 (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func9 (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func10 (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func11 (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func12 (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func13 (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func14 (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func15 (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func16 (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func17 (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func18 (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func19 (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func20 (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func21 (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func22 (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func23 (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func24 (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func25 (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func26 (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func27 (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func28 (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func7 (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func8 (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func9 (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func10 (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func11 (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func12 (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func13 (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func14 (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func15 (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func16 (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func17 (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func18 (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func19 (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func20 (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func21 (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func22 (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func23 (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func24 (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func25 (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func26 (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func27 (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func28 (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,334 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0buffer_330_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d_d0_d0 ;
|
||||
input Iin_d_d0_d1 ;
|
||||
input Iin_d_d1_d0 ;
|
||||
input Iin_d_d1_d1 ;
|
||||
input Iin_d_d2_d0 ;
|
||||
input Iin_d_d2_d1 ;
|
||||
input Iin_d_d3_d0 ;
|
||||
input Iin_d_d3_d1 ;
|
||||
input Iin_d_d4_d0 ;
|
||||
input Iin_d_d4_d1 ;
|
||||
input Iin_d_d5_d0 ;
|
||||
input Iin_d_d5_d1 ;
|
||||
input Iin_d_d6_d0 ;
|
||||
input Iin_d_d6_d1 ;
|
||||
input Iin_d_d7_d0 ;
|
||||
input Iin_d_d7_d1 ;
|
||||
input Iin_d_d8_d0 ;
|
||||
input Iin_d_d8_d1 ;
|
||||
input Iin_d_d9_d0 ;
|
||||
input Iin_d_d9_d1 ;
|
||||
input Iin_d_d10_d0 ;
|
||||
input Iin_d_d10_d1 ;
|
||||
input Iin_d_d11_d0 ;
|
||||
input Iin_d_d11_d1 ;
|
||||
input Iin_d_d12_d0 ;
|
||||
input Iin_d_d12_d1 ;
|
||||
input Iin_d_d13_d0 ;
|
||||
input Iin_d_d13_d1 ;
|
||||
input Iin_d_d14_d0 ;
|
||||
input Iin_d_d14_d1 ;
|
||||
input Iin_d_d15_d0 ;
|
||||
input Iin_d_d15_d1 ;
|
||||
input Iin_d_d16_d0 ;
|
||||
input Iin_d_d16_d1 ;
|
||||
input Iin_d_d17_d0 ;
|
||||
input Iin_d_d17_d1 ;
|
||||
input Iin_d_d18_d0 ;
|
||||
input Iin_d_d18_d1 ;
|
||||
input Iin_d_d19_d0 ;
|
||||
input Iin_d_d19_d1 ;
|
||||
input Iin_d_d20_d0 ;
|
||||
input Iin_d_d20_d1 ;
|
||||
input Iin_d_d21_d0 ;
|
||||
input Iin_d_d21_d1 ;
|
||||
input Iin_d_d22_d0 ;
|
||||
input Iin_d_d22_d1 ;
|
||||
input Iin_d_d23_d0 ;
|
||||
input Iin_d_d23_d1 ;
|
||||
input Iin_d_d24_d0 ;
|
||||
input Iin_d_d24_d1 ;
|
||||
input Iin_d_d25_d0 ;
|
||||
input Iin_d_d25_d1 ;
|
||||
input Iin_d_d26_d0 ;
|
||||
input Iin_d_d26_d1 ;
|
||||
input Iin_d_d27_d0 ;
|
||||
input Iin_d_d27_d1 ;
|
||||
input Iin_d_d28_d0 ;
|
||||
input Iin_d_d28_d1 ;
|
||||
input Iin_d_d29_d0 ;
|
||||
input Iin_d_d29_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
input Iout_a ;
|
||||
input Iout_v ;
|
||||
input reset_B;
|
||||
|
||||
// -- signals ---
|
||||
output Iin_v ;
|
||||
output Iout_d_d25_d0 ;
|
||||
wire Iin_d_d14_d1 ;
|
||||
wire Iin_d_d10_d1 ;
|
||||
wire Iin_d_d27_d1 ;
|
||||
output Iout_d_d12_d1 ;
|
||||
wire Iin_d_d14_d0 ;
|
||||
output Iout_d_d23_d1 ;
|
||||
output Iout_d_d21_d1 ;
|
||||
output Iout_d_d8_d0 ;
|
||||
output Iout_d_d26_d0 ;
|
||||
output Iout_d_d3_d1 ;
|
||||
wire Iin_d_d18_d1 ;
|
||||
output Iout_d_d4_d0 ;
|
||||
wire Iin_d_d18_d0 ;
|
||||
output Iout_d_d28_d1 ;
|
||||
output Iout_d_d19_d0 ;
|
||||
wire Iin_d_d11_d1 ;
|
||||
output Iout_d_d2_d0 ;
|
||||
wire Iin_d_d1_d0 ;
|
||||
wire Iin_d_d9_d1 ;
|
||||
output Iout_d_d15_d0 ;
|
||||
output Iout_d_d13_d1 ;
|
||||
output Iout_d_d4_d1 ;
|
||||
wire Iin_d_d17_d0 ;
|
||||
output Iout_d_d22_d0 ;
|
||||
wire reset_B;
|
||||
output Iout_d_d1_d1 ;
|
||||
wire Iin_d_d16_d1 ;
|
||||
wire I_out_a_BX0 ;
|
||||
output Iout_d_d15_d1 ;
|
||||
output Iout_d_d27_d0 ;
|
||||
wire Iin_d_d0_d1 ;
|
||||
wire Iin_d_d28_d0 ;
|
||||
wire Iin_d_d5_d0 ;
|
||||
wire Iin_d_d23_d0 ;
|
||||
wire _en ;
|
||||
wire Iin_d_d1_d1 ;
|
||||
wire Iin_d_d12_d1 ;
|
||||
wire Iin_d_d19_d0 ;
|
||||
wire Iin_d_d8_d1 ;
|
||||
output Iout_d_d7_d1 ;
|
||||
wire Iin_d_d5_d1 ;
|
||||
wire Iin_d_d12_d0 ;
|
||||
wire Iin_d_d13_d1 ;
|
||||
wire Iin_d_d26_d1 ;
|
||||
output Iout_d_d9_d1 ;
|
||||
output Iout_d_d22_d1 ;
|
||||
output Iout_d_d10_d0 ;
|
||||
wire Iin_d_d21_d0 ;
|
||||
output Iout_d_d29_d0 ;
|
||||
output Iout_d_d5_d0 ;
|
||||
wire Iin_d_d0_d0 ;
|
||||
wire Iin_d_d22_d1 ;
|
||||
wire Iin_d_d28_d1 ;
|
||||
output Iout_d_d9_d0 ;
|
||||
output Iout_d_d23_d0 ;
|
||||
wire Iin_d_d23_d1 ;
|
||||
output Iout_d_d16_d1 ;
|
||||
output Iout_d_d28_d0 ;
|
||||
wire Iin_d_d6_d1 ;
|
||||
output Iout_d_d12_d0 ;
|
||||
wire Iin_d_d2_d0 ;
|
||||
wire Iin_d_d13_d0 ;
|
||||
output Iout_d_d5_d1 ;
|
||||
wire Ien_buf_out0 ;
|
||||
wire Iin_d_d29_d0 ;
|
||||
output Iout_d_d29_d1 ;
|
||||
output Iout_d_d3_d0 ;
|
||||
wire _in_v ;
|
||||
output Iout_d_d16_d0 ;
|
||||
output Iout_d_d18_d0 ;
|
||||
output Iout_d_d24_d0 ;
|
||||
wire Iout_a ;
|
||||
output Iout_d_d8_d1 ;
|
||||
output Iout_d_d0_d0 ;
|
||||
output Iout_d_d13_d0 ;
|
||||
wire Iin_d_d25_d0 ;
|
||||
wire Iin_d_d20_d1 ;
|
||||
wire Iin_d_d22_d0 ;
|
||||
wire Iin_d_d29_d1 ;
|
||||
wire Iin_d_d20_d0 ;
|
||||
wire Iin_d_d26_d0 ;
|
||||
wire Iin_d_d4_d1 ;
|
||||
output Iout_d_d18_d1 ;
|
||||
wire Iout_v ;
|
||||
wire Iin_d_d7_d1 ;
|
||||
output Iout_d_d14_d1 ;
|
||||
wire Iin_d_d15_d1 ;
|
||||
output Iout_d_d0_d1 ;
|
||||
wire Iin_d_d9_d0 ;
|
||||
output Iout_d_d10_d1 ;
|
||||
output Iout_d_d7_d0 ;
|
||||
wire Iin_d_d19_d1 ;
|
||||
wire Iin_d_d24_d0 ;
|
||||
wire Iin_d_d27_d0 ;
|
||||
output Iout_d_d1_d0 ;
|
||||
wire Iin_d_d3_d0 ;
|
||||
wire Iin_d_d11_d0 ;
|
||||
wire Iin_d_d6_d0 ;
|
||||
wire Iin_d_d4_d0 ;
|
||||
wire Iin_d_d24_d1 ;
|
||||
output Iout_d_d11_d1 ;
|
||||
output Iout_d_d11_d0 ;
|
||||
output Iout_d_d21_d0 ;
|
||||
wire Iin_d_d3_d1 ;
|
||||
wire Iin_d_d21_d1 ;
|
||||
output Iout_d_d26_d1 ;
|
||||
output Iout_d_d14_d0 ;
|
||||
output Iout_d_d20_d0 ;
|
||||
wire Iin_d_d15_d0 ;
|
||||
output Iout_d_d27_d1 ;
|
||||
wire Iin_d_d25_d1 ;
|
||||
wire Iin_d_d16_d0 ;
|
||||
wire _reset_BX ;
|
||||
wire Iin_d_d8_d0 ;
|
||||
wire Iin_d_d17_d1 ;
|
||||
output Iout_d_d17_d1 ;
|
||||
output Iout_d_d6_d0 ;
|
||||
wire Iin_d_d10_d0 ;
|
||||
output Iout_d_d6_d1 ;
|
||||
output Iout_d_d24_d1 ;
|
||||
output Iout_d_d17_d0 ;
|
||||
output Iout_d_d2_d1 ;
|
||||
wire Iin_d_d2_d1 ;
|
||||
output Iout_d_d20_d1 ;
|
||||
output Iout_d_d25_d1 ;
|
||||
wire _out_a_B ;
|
||||
output Iin_a ;
|
||||
wire I_reset_BXX0 ;
|
||||
wire Iin_d_d7_d0 ;
|
||||
output Iout_d_d19_d1 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X4 Iin_v_buf (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0vtree_330_4 Ivc (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
|
||||
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_360_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func7 (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func8 (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func9 (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func10 (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func11 (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func12 (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func13 (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func14 (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func15 (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func16 (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func17 (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func18 (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func19 (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func20 (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func21 (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func22 (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func23 (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func24 (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func25 (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func26 (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func27 (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func28 (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func29 (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func7 (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func8 (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func9 (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func10 (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func11 (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func12 (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func13 (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func14 (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func15 (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func16 (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func17 (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func18 (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func19 (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func20 (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func21 (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func22 (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func23 (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func24 (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func25 (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func26 (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func27 (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func28 (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func29 (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,344 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0buffer_331_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Iout_d_d30_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d_d0_d0 ;
|
||||
input Iin_d_d0_d1 ;
|
||||
input Iin_d_d1_d0 ;
|
||||
input Iin_d_d1_d1 ;
|
||||
input Iin_d_d2_d0 ;
|
||||
input Iin_d_d2_d1 ;
|
||||
input Iin_d_d3_d0 ;
|
||||
input Iin_d_d3_d1 ;
|
||||
input Iin_d_d4_d0 ;
|
||||
input Iin_d_d4_d1 ;
|
||||
input Iin_d_d5_d0 ;
|
||||
input Iin_d_d5_d1 ;
|
||||
input Iin_d_d6_d0 ;
|
||||
input Iin_d_d6_d1 ;
|
||||
input Iin_d_d7_d0 ;
|
||||
input Iin_d_d7_d1 ;
|
||||
input Iin_d_d8_d0 ;
|
||||
input Iin_d_d8_d1 ;
|
||||
input Iin_d_d9_d0 ;
|
||||
input Iin_d_d9_d1 ;
|
||||
input Iin_d_d10_d0 ;
|
||||
input Iin_d_d10_d1 ;
|
||||
input Iin_d_d11_d0 ;
|
||||
input Iin_d_d11_d1 ;
|
||||
input Iin_d_d12_d0 ;
|
||||
input Iin_d_d12_d1 ;
|
||||
input Iin_d_d13_d0 ;
|
||||
input Iin_d_d13_d1 ;
|
||||
input Iin_d_d14_d0 ;
|
||||
input Iin_d_d14_d1 ;
|
||||
input Iin_d_d15_d0 ;
|
||||
input Iin_d_d15_d1 ;
|
||||
input Iin_d_d16_d0 ;
|
||||
input Iin_d_d16_d1 ;
|
||||
input Iin_d_d17_d0 ;
|
||||
input Iin_d_d17_d1 ;
|
||||
input Iin_d_d18_d0 ;
|
||||
input Iin_d_d18_d1 ;
|
||||
input Iin_d_d19_d0 ;
|
||||
input Iin_d_d19_d1 ;
|
||||
input Iin_d_d20_d0 ;
|
||||
input Iin_d_d20_d1 ;
|
||||
input Iin_d_d21_d0 ;
|
||||
input Iin_d_d21_d1 ;
|
||||
input Iin_d_d22_d0 ;
|
||||
input Iin_d_d22_d1 ;
|
||||
input Iin_d_d23_d0 ;
|
||||
input Iin_d_d23_d1 ;
|
||||
input Iin_d_d24_d0 ;
|
||||
input Iin_d_d24_d1 ;
|
||||
input Iin_d_d25_d0 ;
|
||||
input Iin_d_d25_d1 ;
|
||||
input Iin_d_d26_d0 ;
|
||||
input Iin_d_d26_d1 ;
|
||||
input Iin_d_d27_d0 ;
|
||||
input Iin_d_d27_d1 ;
|
||||
input Iin_d_d28_d0 ;
|
||||
input Iin_d_d28_d1 ;
|
||||
input Iin_d_d29_d0 ;
|
||||
input Iin_d_d29_d1 ;
|
||||
input Iin_d_d30_d0 ;
|
||||
input Iin_d_d30_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
input Iout_a ;
|
||||
input Iout_v ;
|
||||
input reset_B;
|
||||
|
||||
// -- signals ---
|
||||
wire Iin_d_d6_d0 ;
|
||||
wire Iin_d_d20_d1 ;
|
||||
wire Iin_d_d29_d0 ;
|
||||
output Iout_d_d17_d1 ;
|
||||
output Iout_d_d19_d0 ;
|
||||
wire Iin_d_d15_d0 ;
|
||||
output Iout_d_d15_d1 ;
|
||||
wire Iin_d_d17_d1 ;
|
||||
wire _reset_BX ;
|
||||
output Iout_d_d0_d0 ;
|
||||
wire Iin_d_d13_d1 ;
|
||||
wire Iin_d_d22_d0 ;
|
||||
wire Iin_d_d26_d1 ;
|
||||
wire Iin_d_d1_d1 ;
|
||||
wire Iin_d_d26_d0 ;
|
||||
wire Iin_d_d27_d0 ;
|
||||
output Iout_d_d26_d1 ;
|
||||
output Iout_d_d26_d0 ;
|
||||
wire Iin_d_d2_d0 ;
|
||||
wire Iin_d_d28_d0 ;
|
||||
output Iout_d_d4_d1 ;
|
||||
output Iout_d_d6_d1 ;
|
||||
output Iout_d_d8_d1 ;
|
||||
output Iout_d_d27_d1 ;
|
||||
output Iin_v ;
|
||||
wire Iin_d_d8_d1 ;
|
||||
wire Iin_d_d14_d0 ;
|
||||
wire Iin_d_d21_d1 ;
|
||||
wire Iin_d_d30_d0 ;
|
||||
output Iout_d_d28_d1 ;
|
||||
output Iout_d_d12_d0 ;
|
||||
output Iout_d_d3_d1 ;
|
||||
output Iout_d_d21_d1 ;
|
||||
output Iout_d_d7_d1 ;
|
||||
wire Iin_d_d6_d1 ;
|
||||
wire Iin_d_d15_d1 ;
|
||||
wire Iin_d_d22_d1 ;
|
||||
output Iout_d_d9_d1 ;
|
||||
wire Iin_d_d27_d1 ;
|
||||
wire Iin_d_d28_d1 ;
|
||||
output Iout_d_d19_d1 ;
|
||||
output Iout_d_d20_d1 ;
|
||||
output Iout_d_d15_d0 ;
|
||||
output Iout_d_d22_d0 ;
|
||||
output Iout_d_d23_d0 ;
|
||||
wire Iin_d_d14_d1 ;
|
||||
output Iout_d_d4_d0 ;
|
||||
wire Iin_d_d7_d1 ;
|
||||
wire Iin_d_d23_d0 ;
|
||||
wire Iin_d_d18_d1 ;
|
||||
wire Iin_d_d19_d1 ;
|
||||
wire I_out_a_BX0 ;
|
||||
wire Iin_d_d12_d1 ;
|
||||
output Iout_d_d14_d1 ;
|
||||
output Iout_d_d27_d0 ;
|
||||
output Iout_d_d1_d0 ;
|
||||
wire Iout_v ;
|
||||
wire Iin_d_d19_d0 ;
|
||||
wire reset_B;
|
||||
output Iout_d_d30_d0 ;
|
||||
output Iout_d_d29_d1 ;
|
||||
output Iout_d_d30_d1 ;
|
||||
wire Iin_d_d1_d0 ;
|
||||
output Iout_d_d18_d1 ;
|
||||
output Iout_d_d25_d1 ;
|
||||
wire Iin_d_d2_d1 ;
|
||||
wire Iin_d_d24_d0 ;
|
||||
output Iout_d_d22_d1 ;
|
||||
output Iout_d_d13_d0 ;
|
||||
output Iout_d_d18_d0 ;
|
||||
wire Iin_d_d18_d0 ;
|
||||
wire Iin_d_d24_d1 ;
|
||||
wire Iin_d_d4_d0 ;
|
||||
output Iout_d_d2_d1 ;
|
||||
output Iout_d_d5_d1 ;
|
||||
wire Iin_d_d9_d1 ;
|
||||
wire Iin_d_d10_d1 ;
|
||||
wire Iin_d_d11_d0 ;
|
||||
wire Iin_d_d11_d1 ;
|
||||
output Iout_d_d16_d1 ;
|
||||
wire Iin_d_d0_d0 ;
|
||||
wire Iin_d_d16_d0 ;
|
||||
wire Iin_d_d23_d1 ;
|
||||
wire Iin_d_d30_d1 ;
|
||||
output Iout_d_d20_d0 ;
|
||||
wire Iin_d_d13_d0 ;
|
||||
wire Iin_d_d20_d0 ;
|
||||
output Iin_a ;
|
||||
wire Iin_d_d5_d0 ;
|
||||
wire Iin_d_d17_d0 ;
|
||||
output Iout_d_d10_d1 ;
|
||||
output Iout_d_d29_d0 ;
|
||||
output Iout_d_d13_d1 ;
|
||||
output Iout_d_d16_d0 ;
|
||||
output Iout_d_d28_d0 ;
|
||||
wire I_reset_BXX0 ;
|
||||
wire Iin_d_d5_d1 ;
|
||||
output Iout_d_d11_d1 ;
|
||||
output Iout_d_d12_d1 ;
|
||||
wire Iin_d_d7_d0 ;
|
||||
wire Iin_d_d3_d1 ;
|
||||
output Iout_d_d17_d0 ;
|
||||
output Iout_d_d6_d0 ;
|
||||
wire Iin_d_d4_d1 ;
|
||||
wire Iin_d_d25_d1 ;
|
||||
output Iout_d_d25_d0 ;
|
||||
wire Iin_d_d9_d0 ;
|
||||
wire Iin_d_d10_d0 ;
|
||||
output Iout_d_d24_d1 ;
|
||||
wire _en ;
|
||||
wire Iin_d_d25_d0 ;
|
||||
wire Iout_a ;
|
||||
wire Iin_d_d3_d0 ;
|
||||
wire Ien_buf_out0 ;
|
||||
output Iout_d_d5_d0 ;
|
||||
output Iout_d_d7_d0 ;
|
||||
output Iout_d_d24_d0 ;
|
||||
wire Iin_d_d12_d0 ;
|
||||
wire Iin_d_d21_d0 ;
|
||||
wire Iin_d_d29_d1 ;
|
||||
output Iout_d_d23_d1 ;
|
||||
output Iout_d_d8_d0 ;
|
||||
wire _out_a_B ;
|
||||
wire Iin_d_d8_d0 ;
|
||||
wire Iin_d_d16_d1 ;
|
||||
output Iout_d_d0_d1 ;
|
||||
wire _in_v ;
|
||||
output Iout_d_d3_d0 ;
|
||||
output Iout_d_d10_d0 ;
|
||||
output Iout_d_d11_d0 ;
|
||||
output Iout_d_d21_d0 ;
|
||||
wire Iin_d_d0_d1 ;
|
||||
output Iout_d_d1_d1 ;
|
||||
output Iout_d_d2_d0 ;
|
||||
output Iout_d_d9_d0 ;
|
||||
output Iout_d_d14_d0 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X4 Iin_v_buf (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0vtree_331_4 Ivc (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
|
||||
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_362_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func7 (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func8 (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func9 (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func10 (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func11 (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func12 (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func13 (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func14 (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func15 (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func16 (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func17 (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func18 (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func19 (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func20 (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func21 (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func22 (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func23 (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func24 (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func25 (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func26 (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func27 (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func28 (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func29 (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func30 (.y(Iout_d_d30_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func7 (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func8 (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func9 (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func10 (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func11 (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func12 (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func13 (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func14 (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func15 (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func16 (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func17 (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func18 (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func19 (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func20 (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func21 (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func22 (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func23 (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func24 (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func25 (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func26 (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func27 (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func28 (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func29 (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func30 (.y(Iout_d_d30_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,354 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0buffer_332_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iin_d_d31_d0 , Iin_d_d31_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Iout_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d_d0_d0 ;
|
||||
input Iin_d_d0_d1 ;
|
||||
input Iin_d_d1_d0 ;
|
||||
input Iin_d_d1_d1 ;
|
||||
input Iin_d_d2_d0 ;
|
||||
input Iin_d_d2_d1 ;
|
||||
input Iin_d_d3_d0 ;
|
||||
input Iin_d_d3_d1 ;
|
||||
input Iin_d_d4_d0 ;
|
||||
input Iin_d_d4_d1 ;
|
||||
input Iin_d_d5_d0 ;
|
||||
input Iin_d_d5_d1 ;
|
||||
input Iin_d_d6_d0 ;
|
||||
input Iin_d_d6_d1 ;
|
||||
input Iin_d_d7_d0 ;
|
||||
input Iin_d_d7_d1 ;
|
||||
input Iin_d_d8_d0 ;
|
||||
input Iin_d_d8_d1 ;
|
||||
input Iin_d_d9_d0 ;
|
||||
input Iin_d_d9_d1 ;
|
||||
input Iin_d_d10_d0 ;
|
||||
input Iin_d_d10_d1 ;
|
||||
input Iin_d_d11_d0 ;
|
||||
input Iin_d_d11_d1 ;
|
||||
input Iin_d_d12_d0 ;
|
||||
input Iin_d_d12_d1 ;
|
||||
input Iin_d_d13_d0 ;
|
||||
input Iin_d_d13_d1 ;
|
||||
input Iin_d_d14_d0 ;
|
||||
input Iin_d_d14_d1 ;
|
||||
input Iin_d_d15_d0 ;
|
||||
input Iin_d_d15_d1 ;
|
||||
input Iin_d_d16_d0 ;
|
||||
input Iin_d_d16_d1 ;
|
||||
input Iin_d_d17_d0 ;
|
||||
input Iin_d_d17_d1 ;
|
||||
input Iin_d_d18_d0 ;
|
||||
input Iin_d_d18_d1 ;
|
||||
input Iin_d_d19_d0 ;
|
||||
input Iin_d_d19_d1 ;
|
||||
input Iin_d_d20_d0 ;
|
||||
input Iin_d_d20_d1 ;
|
||||
input Iin_d_d21_d0 ;
|
||||
input Iin_d_d21_d1 ;
|
||||
input Iin_d_d22_d0 ;
|
||||
input Iin_d_d22_d1 ;
|
||||
input Iin_d_d23_d0 ;
|
||||
input Iin_d_d23_d1 ;
|
||||
input Iin_d_d24_d0 ;
|
||||
input Iin_d_d24_d1 ;
|
||||
input Iin_d_d25_d0 ;
|
||||
input Iin_d_d25_d1 ;
|
||||
input Iin_d_d26_d0 ;
|
||||
input Iin_d_d26_d1 ;
|
||||
input Iin_d_d27_d0 ;
|
||||
input Iin_d_d27_d1 ;
|
||||
input Iin_d_d28_d0 ;
|
||||
input Iin_d_d28_d1 ;
|
||||
input Iin_d_d29_d0 ;
|
||||
input Iin_d_d29_d1 ;
|
||||
input Iin_d_d30_d0 ;
|
||||
input Iin_d_d30_d1 ;
|
||||
input Iin_d_d31_d0 ;
|
||||
input Iin_d_d31_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
input Iout_a ;
|
||||
input Iout_v ;
|
||||
input reset_B;
|
||||
|
||||
// -- signals ---
|
||||
output Iin_a ;
|
||||
wire Iin_d_d9_d1 ;
|
||||
wire Iin_d_d23_d0 ;
|
||||
wire Iin_d_d24_d1 ;
|
||||
output Iout_d_d7_d1 ;
|
||||
output Iout_d_d29_d1 ;
|
||||
wire Iin_d_d11_d1 ;
|
||||
wire Iin_d_d30_d0 ;
|
||||
output Iout_d_d4_d0 ;
|
||||
wire Iin_d_d6_d1 ;
|
||||
output Iout_d_d4_d1 ;
|
||||
output Iout_d_d10_d1 ;
|
||||
wire Iin_d_d27_d0 ;
|
||||
output Iout_d_d15_d0 ;
|
||||
output Iout_d_d20_d0 ;
|
||||
wire Iin_d_d31_d0 ;
|
||||
wire reset_B;
|
||||
wire Iin_d_d12_d0 ;
|
||||
wire Iin_d_d28_d1 ;
|
||||
output Iout_d_d0_d1 ;
|
||||
output Iin_v ;
|
||||
wire Iin_d_d7_d0 ;
|
||||
wire Iin_d_d10_d0 ;
|
||||
output Iout_d_d9_d0 ;
|
||||
output Iout_d_d25_d0 ;
|
||||
wire Iin_d_d11_d0 ;
|
||||
output Iout_d_d12_d1 ;
|
||||
output Iout_d_d11_d0 ;
|
||||
wire Iin_d_d19_d0 ;
|
||||
output Iout_d_d16_d1 ;
|
||||
output Iout_d_d21_d1 ;
|
||||
wire _out_a_B ;
|
||||
wire _in_v ;
|
||||
wire Iin_d_d15_d1 ;
|
||||
wire Iin_d_d27_d1 ;
|
||||
wire Iin_d_d8_d1 ;
|
||||
wire Iin_d_d28_d0 ;
|
||||
output Iout_d_d0_d0 ;
|
||||
output Iout_d_d28_d0 ;
|
||||
wire Iin_d_d10_d1 ;
|
||||
wire Iin_d_d26_d1 ;
|
||||
wire Iin_d_d3_d1 ;
|
||||
output Iout_d_d22_d1 ;
|
||||
wire Iin_d_d14_d0 ;
|
||||
wire Iin_d_d31_d1 ;
|
||||
output Iout_d_d5_d1 ;
|
||||
wire Iin_d_d5_d1 ;
|
||||
wire Iin_d_d30_d1 ;
|
||||
output Iout_d_d10_d0 ;
|
||||
output Iout_d_d18_d0 ;
|
||||
output Iout_d_d19_d0 ;
|
||||
output Iout_d_d14_d1 ;
|
||||
wire Iin_d_d0_d0 ;
|
||||
wire Iin_d_d12_d1 ;
|
||||
wire Iin_d_d13_d1 ;
|
||||
wire Iin_d_d26_d0 ;
|
||||
output Iout_d_d13_d1 ;
|
||||
output Iout_d_d7_d0 ;
|
||||
output Iout_d_d13_d0 ;
|
||||
wire Iin_d_d22_d0 ;
|
||||
wire Iin_d_d2_d0 ;
|
||||
wire Iin_d_d25_d0 ;
|
||||
output Iout_d_d23_d1 ;
|
||||
wire Iin_d_d19_d1 ;
|
||||
wire Iin_d_d22_d1 ;
|
||||
output Iout_d_d17_d0 ;
|
||||
output Iout_d_d2_d0 ;
|
||||
wire I_out_a_BX0 ;
|
||||
wire Iin_d_d16_d1 ;
|
||||
wire Iin_d_d20_d0 ;
|
||||
wire Iin_d_d20_d1 ;
|
||||
wire Iin_d_d21_d1 ;
|
||||
output Iout_d_d2_d1 ;
|
||||
output Iout_d_d20_d1 ;
|
||||
wire Iin_d_d2_d1 ;
|
||||
wire Iin_d_d6_d0 ;
|
||||
wire Iin_d_d17_d1 ;
|
||||
output Iout_d_d17_d1 ;
|
||||
wire Iin_d_d3_d0 ;
|
||||
output Iout_d_d11_d1 ;
|
||||
output Iout_d_d18_d1 ;
|
||||
wire Iin_d_d8_d0 ;
|
||||
output Iout_d_d8_d1 ;
|
||||
output Iout_d_d14_d0 ;
|
||||
output Iout_d_d22_d0 ;
|
||||
wire Iin_d_d18_d0 ;
|
||||
wire Iin_d_d18_d1 ;
|
||||
output Iout_d_d1_d1 ;
|
||||
output Iout_d_d31_d0 ;
|
||||
wire Iin_d_d9_d0 ;
|
||||
wire Iin_d_d4_d0 ;
|
||||
output Iout_d_d24_d1 ;
|
||||
output Iout_d_d1_d0 ;
|
||||
output Iout_d_d12_d0 ;
|
||||
wire _en ;
|
||||
output Iout_d_d3_d0 ;
|
||||
output Iout_d_d5_d0 ;
|
||||
output Iout_d_d15_d1 ;
|
||||
output Iout_d_d19_d1 ;
|
||||
output Iout_d_d31_d1 ;
|
||||
wire Iin_d_d16_d0 ;
|
||||
wire Iin_d_d21_d0 ;
|
||||
output Iout_d_d9_d1 ;
|
||||
wire I_reset_BXX0 ;
|
||||
wire Iin_d_d25_d1 ;
|
||||
output Iout_d_d28_d1 ;
|
||||
wire _reset_BX ;
|
||||
wire Iin_d_d1_d0 ;
|
||||
wire Iin_d_d7_d1 ;
|
||||
wire Iin_d_d17_d0 ;
|
||||
wire Iin_d_d29_d0 ;
|
||||
wire Iin_d_d5_d0 ;
|
||||
output Iout_d_d27_d0 ;
|
||||
output Iout_d_d24_d0 ;
|
||||
output Iout_d_d26_d0 ;
|
||||
output Iout_d_d23_d0 ;
|
||||
wire Ien_buf_out0 ;
|
||||
output Iout_d_d16_d0 ;
|
||||
output Iout_d_d26_d1 ;
|
||||
wire Iin_d_d24_d0 ;
|
||||
wire Iout_v ;
|
||||
wire Iin_d_d14_d1 ;
|
||||
wire Iin_d_d15_d0 ;
|
||||
output Iout_d_d30_d1 ;
|
||||
output Iout_d_d30_d0 ;
|
||||
wire Iin_d_d4_d1 ;
|
||||
wire Iin_d_d29_d1 ;
|
||||
output Iout_d_d27_d1 ;
|
||||
output Iout_d_d29_d0 ;
|
||||
wire Iin_d_d0_d1 ;
|
||||
wire Iin_d_d23_d1 ;
|
||||
output Iout_d_d25_d1 ;
|
||||
wire Iout_a ;
|
||||
wire Iin_d_d13_d0 ;
|
||||
output Iout_d_d3_d1 ;
|
||||
output Iout_d_d8_d0 ;
|
||||
output Iout_d_d21_d0 ;
|
||||
wire Iin_d_d1_d1 ;
|
||||
output Iout_d_d6_d1 ;
|
||||
output Iout_d_d6_d0 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X4 Iin_v_buf (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0vtree_332_4 Ivc (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .Iin_d31_d0 (Iin_d_d31_d0 ), .Iin_d31_d1 (Iin_d_d31_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
|
||||
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func7 (.y(Iout_d_d7_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func8 (.y(Iout_d_d8_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func9 (.y(Iout_d_d9_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func10 (.y(Iout_d_d10_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func11 (.y(Iout_d_d11_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func12 (.y(Iout_d_d12_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func13 (.y(Iout_d_d13_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func14 (.y(Iout_d_d14_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func15 (.y(Iout_d_d15_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func16 (.y(Iout_d_d16_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func17 (.y(Iout_d_d17_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func18 (.y(Iout_d_d18_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func19 (.y(Iout_d_d19_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func20 (.y(Iout_d_d20_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func21 (.y(Iout_d_d21_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func22 (.y(Iout_d_d22_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func23 (.y(Iout_d_d23_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func24 (.y(Iout_d_d24_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func25 (.y(Iout_d_d25_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func26 (.y(Iout_d_d26_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func27 (.y(Iout_d_d27_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func28 (.y(Iout_d_d28_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func29 (.y(Iout_d_d29_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func30 (.y(Iout_d_d30_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func31 (.y(Iout_d_d31_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d31_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func7 (.y(Iout_d_d7_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d7_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func8 (.y(Iout_d_d8_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d8_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func9 (.y(Iout_d_d9_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d9_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func10 (.y(Iout_d_d10_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d10_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func11 (.y(Iout_d_d11_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d11_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func12 (.y(Iout_d_d12_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d12_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func13 (.y(Iout_d_d13_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d13_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func14 (.y(Iout_d_d14_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d14_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func15 (.y(Iout_d_d15_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d15_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func16 (.y(Iout_d_d16_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d16_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func17 (.y(Iout_d_d17_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d17_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func18 (.y(Iout_d_d18_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d18_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func19 (.y(Iout_d_d19_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d19_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func20 (.y(Iout_d_d20_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d20_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func21 (.y(Iout_d_d21_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d21_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func22 (.y(Iout_d_d22_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d22_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func23 (.y(Iout_d_d23_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d23_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func24 (.y(Iout_d_d24_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d24_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func25 (.y(Iout_d_d25_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d25_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func26 (.y(Iout_d_d26_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d26_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func27 (.y(Iout_d_d27_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d27_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func28 (.y(Iout_d_d28_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d28_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func29 (.y(Iout_d_d29_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d29_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func30 (.y(Iout_d_d30_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d30_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func31 (.y(Iout_d_d31_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d31_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,104 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0buffer_37_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , reset_B, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d_d0_d0 ;
|
||||
input Iin_d_d0_d1 ;
|
||||
input Iin_d_d1_d0 ;
|
||||
input Iin_d_d1_d1 ;
|
||||
input Iin_d_d2_d0 ;
|
||||
input Iin_d_d2_d1 ;
|
||||
input Iin_d_d3_d0 ;
|
||||
input Iin_d_d3_d1 ;
|
||||
input Iin_d_d4_d0 ;
|
||||
input Iin_d_d4_d1 ;
|
||||
input Iin_d_d5_d0 ;
|
||||
input Iin_d_d5_d1 ;
|
||||
input Iin_d_d6_d0 ;
|
||||
input Iin_d_d6_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
input Iout_a ;
|
||||
input Iout_v ;
|
||||
input reset_B;
|
||||
|
||||
// -- signals ---
|
||||
output Iout_d_d2_d0 ;
|
||||
wire Iin_d_d6_d1 ;
|
||||
output Iout_d_d4_d1 ;
|
||||
wire I_out_a_BX0 ;
|
||||
output Iout_d_d3_d0 ;
|
||||
wire Iin_d_d4_d1 ;
|
||||
output Iout_d_d1_d0 ;
|
||||
wire Iout_v ;
|
||||
output Iout_d_d1_d1 ;
|
||||
output Iout_d_d0_d1 ;
|
||||
wire Iin_d_d6_d0 ;
|
||||
wire Iin_d_d3_d1 ;
|
||||
wire Iin_d_d4_d0 ;
|
||||
wire I_reset_BXX0 ;
|
||||
output Iin_a ;
|
||||
wire Iin_d_d1_d0 ;
|
||||
output Iout_d_d4_d0 ;
|
||||
wire Ien_buf_out0 ;
|
||||
wire Iout_a ;
|
||||
output Iout_d_d2_d1 ;
|
||||
wire Iin_d_d5_d0 ;
|
||||
output Iout_d_d5_d1 ;
|
||||
wire Iin_d_d5_d1 ;
|
||||
output Iout_d_d5_d0 ;
|
||||
wire Iin_d_d1_d1 ;
|
||||
wire _en ;
|
||||
output Iout_d_d3_d1 ;
|
||||
output Iin_v ;
|
||||
output Iout_d_d0_d0 ;
|
||||
wire Iin_d_d3_d0 ;
|
||||
wire Iin_d_d2_d1 ;
|
||||
output Iout_d_d6_d0 ;
|
||||
output Iout_d_d6_d1 ;
|
||||
wire Iin_d_d2_d0 ;
|
||||
wire _reset_BX ;
|
||||
wire _out_a_B ;
|
||||
wire reset_B;
|
||||
wire _in_v ;
|
||||
wire Iin_d_d0_d0 ;
|
||||
wire Iin_d_d0_d1 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Iout_a_B_buf (.in(_out_a_B), .Iout0 (I_out_a_BX0 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_RB_X4 Iinack_ctl (.y(Iin_a ), .c1(_en), .c2(Iin_v ), .c3(Iout_v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Ireset_bufarray (.in(_reset_BX), .Iout0 (I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X4 Iin_v_buf (.y(Iin_v ), .a(_in_v), .vdd(vdd), .vss(vss));
|
||||
INV_X1 Iout_a_inv (.y(_out_a_B), .a(Iout_a ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0vtree_37_4 Ivc (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(_in_v), .vdd(vdd), .vss(vss));
|
||||
A_1C1P_X1 Ien_ctl (.y(_en), .c1(Iin_a ), .p1(Iout_v ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_314_4 Ien_buf (.in(_en), .Iout0 (Ien_buf_out0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X1 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func0 (.y(Iout_d_d0_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func1 (.y(Iout_d_d1_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func2 (.y(Iout_d_d2_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func3 (.y(Iout_d_d3_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func4 (.y(Iout_d_d4_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func5 (.y(Iout_d_d5_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 It_buf_func6 (.y(Iout_d_d6_d1 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d1 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func0 (.y(Iout_d_d0_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d0_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func1 (.y(Iout_d_d1_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d1_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func2 (.y(Iout_d_d2_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d2_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func3 (.y(Iout_d_d3_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d3_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func4 (.y(Iout_d_d4_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d4_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func5 (.y(Iout_d_d5_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d5_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
A_2C1N_RB_X4 If_buf_func6 (.y(Iout_d_d6_d0 ), .c1(Ien_buf_out0 ), .c2(I_out_a_BX0 ), .n1(Iin_d_d6_d0 ), .pr_B(I_reset_BXX0 ), .sr_B(I_reset_BXX0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,55 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0ctree_313_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , out, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin0 ;
|
||||
input Iin1 ;
|
||||
input Iin2 ;
|
||||
input Iin3 ;
|
||||
input Iin4 ;
|
||||
input Iin5 ;
|
||||
input Iin6 ;
|
||||
input Iin7 ;
|
||||
input Iin8 ;
|
||||
input Iin9 ;
|
||||
input Iin10 ;
|
||||
input Iin11 ;
|
||||
input Iin12 ;
|
||||
output out;
|
||||
|
||||
// -- signals ---
|
||||
wire Itmp20 ;
|
||||
wire Iin6 ;
|
||||
wire Iin1 ;
|
||||
wire Iin8 ;
|
||||
wire Iin5 ;
|
||||
wire Iin12 ;
|
||||
wire Itmp15 ;
|
||||
wire out ;
|
||||
wire Itmp19 ;
|
||||
wire Itmp21 ;
|
||||
wire Iin4 ;
|
||||
wire Itmp13 ;
|
||||
wire Itmp18 ;
|
||||
wire Iin3 ;
|
||||
wire Iin7 ;
|
||||
wire Iin10 ;
|
||||
wire Iin11 ;
|
||||
wire Iin2 ;
|
||||
wire Itmp14 ;
|
||||
wire Itmp16 ;
|
||||
wire Iin0 ;
|
||||
wire Itmp17 ;
|
||||
wire Iin9 ;
|
||||
|
||||
// --- instances
|
||||
A_2C_B_X1 IC2Els0 (.y(Itmp13 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els1 (.y(Itmp14 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els2 (.y(Itmp15 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els3 (.y(Itmp16 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els4 (.y(Itmp17 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els5 (.y(Itmp19 ), .c1(Itmp13 ), .c2(Itmp14 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els6 (.y(Itmp20 ), .c1(Itmp15 ), .c2(Itmp16 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els7 (.y(Itmp21 ), .c1(Itmp17 ), .c2(Itmp18 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els0 (.y(Itmp18 ), .c1(Iin10 ), .c2(Iin11 ), .c3(Iin12 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els1 (.y(out), .c1(Itmp19 ), .c2(Itmp20 ), .c3(Itmp21 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,93 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0ctree_323_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , out, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin0 ;
|
||||
input Iin1 ;
|
||||
input Iin2 ;
|
||||
input Iin3 ;
|
||||
input Iin4 ;
|
||||
input Iin5 ;
|
||||
input Iin6 ;
|
||||
input Iin7 ;
|
||||
input Iin8 ;
|
||||
input Iin9 ;
|
||||
input Iin10 ;
|
||||
input Iin11 ;
|
||||
input Iin12 ;
|
||||
input Iin13 ;
|
||||
input Iin14 ;
|
||||
input Iin15 ;
|
||||
input Iin16 ;
|
||||
input Iin17 ;
|
||||
input Iin18 ;
|
||||
input Iin19 ;
|
||||
input Iin20 ;
|
||||
input Iin21 ;
|
||||
input Iin22 ;
|
||||
output out;
|
||||
|
||||
// -- signals ---
|
||||
wire Itmp29 ;
|
||||
wire Iin22 ;
|
||||
wire Itmp40 ;
|
||||
wire Iin19 ;
|
||||
wire Itmp27 ;
|
||||
wire Itmp26 ;
|
||||
wire Itmp36 ;
|
||||
wire Itmp25 ;
|
||||
wire Itmp31 ;
|
||||
wire Iin5 ;
|
||||
wire Iin18 ;
|
||||
wire Iin17 ;
|
||||
wire Itmp30 ;
|
||||
wire Iin21 ;
|
||||
wire Iin10 ;
|
||||
wire Iin13 ;
|
||||
wire Iin8 ;
|
||||
wire Iin6 ;
|
||||
wire Iin0 ;
|
||||
wire Iin15 ;
|
||||
wire Iin16 ;
|
||||
wire Itmp23 ;
|
||||
wire Itmp39 ;
|
||||
wire Itmp28 ;
|
||||
wire Itmp38 ;
|
||||
wire Iin11 ;
|
||||
wire Itmp32 ;
|
||||
wire Itmp37 ;
|
||||
wire out ;
|
||||
wire Iin1 ;
|
||||
wire Iin9 ;
|
||||
wire Iin4 ;
|
||||
wire Iin3 ;
|
||||
wire Iin2 ;
|
||||
wire Itmp35 ;
|
||||
wire Itmp33 ;
|
||||
wire Iin12 ;
|
||||
wire Iin20 ;
|
||||
wire Itmp34 ;
|
||||
wire Iin14 ;
|
||||
wire Itmp24 ;
|
||||
wire Iin7 ;
|
||||
|
||||
// --- instances
|
||||
A_2C_B_X1 IC2Els0 (.y(Itmp23 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els1 (.y(Itmp24 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els2 (.y(Itmp25 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els3 (.y(Itmp26 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els4 (.y(Itmp27 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els5 (.y(Itmp28 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els6 (.y(Itmp29 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els7 (.y(Itmp30 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els8 (.y(Itmp31 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els9 (.y(Itmp32 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els10 (.y(Itmp34 ), .c1(Itmp23 ), .c2(Itmp24 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els11 (.y(Itmp35 ), .c1(Itmp25 ), .c2(Itmp26 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els12 (.y(Itmp36 ), .c1(Itmp27 ), .c2(Itmp28 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els13 (.y(Itmp37 ), .c1(Itmp29 ), .c2(Itmp30 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els14 (.y(Itmp39 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els15 (.y(out), .c1(Itmp39 ), .c2(Itmp40 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els0 (.y(Itmp33 ), .c1(Iin20 ), .c2(Iin21 ), .c3(Iin22 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els1 (.y(Itmp38 ), .c1(Itmp31 ), .c2(Itmp32 ), .c3(Itmp33 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els2 (.y(Itmp40 ), .c1(Itmp36 ), .c2(Itmp37 ), .c3(Itmp38 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,117 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0ctree_329_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , out, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin0 ;
|
||||
input Iin1 ;
|
||||
input Iin2 ;
|
||||
input Iin3 ;
|
||||
input Iin4 ;
|
||||
input Iin5 ;
|
||||
input Iin6 ;
|
||||
input Iin7 ;
|
||||
input Iin8 ;
|
||||
input Iin9 ;
|
||||
input Iin10 ;
|
||||
input Iin11 ;
|
||||
input Iin12 ;
|
||||
input Iin13 ;
|
||||
input Iin14 ;
|
||||
input Iin15 ;
|
||||
input Iin16 ;
|
||||
input Iin17 ;
|
||||
input Iin18 ;
|
||||
input Iin19 ;
|
||||
input Iin20 ;
|
||||
input Iin21 ;
|
||||
input Iin22 ;
|
||||
input Iin23 ;
|
||||
input Iin24 ;
|
||||
input Iin25 ;
|
||||
input Iin26 ;
|
||||
input Iin27 ;
|
||||
input Iin28 ;
|
||||
output out;
|
||||
|
||||
// -- signals ---
|
||||
wire Iin20 ;
|
||||
wire Iin15 ;
|
||||
wire Iin3 ;
|
||||
wire Iin27 ;
|
||||
wire Itmp46 ;
|
||||
wire Iin2 ;
|
||||
wire Iin23 ;
|
||||
wire Itmp36 ;
|
||||
wire Itmp32 ;
|
||||
wire Iin13 ;
|
||||
wire Iin4 ;
|
||||
wire Itmp48 ;
|
||||
wire Iin10 ;
|
||||
wire Iin19 ;
|
||||
wire Itmp34 ;
|
||||
wire Itmp43 ;
|
||||
wire Itmp39 ;
|
||||
wire Iin8 ;
|
||||
wire out ;
|
||||
wire Itmp51 ;
|
||||
wire Itmp31 ;
|
||||
wire Iin12 ;
|
||||
wire Itmp30 ;
|
||||
wire Itmp47 ;
|
||||
wire Itmp41 ;
|
||||
wire Itmp40 ;
|
||||
wire Itmp37 ;
|
||||
wire Itmp35 ;
|
||||
wire Itmp45 ;
|
||||
wire Iin21 ;
|
||||
wire Iin16 ;
|
||||
wire Itmp52 ;
|
||||
wire Iin28 ;
|
||||
wire Iin26 ;
|
||||
wire Itmp38 ;
|
||||
wire Itmp49 ;
|
||||
wire Iin9 ;
|
||||
wire Iin7 ;
|
||||
wire Iin1 ;
|
||||
wire Itmp50 ;
|
||||
wire Iin11 ;
|
||||
wire Itmp33 ;
|
||||
wire Iin25 ;
|
||||
wire Iin18 ;
|
||||
wire Itmp44 ;
|
||||
wire Iin17 ;
|
||||
wire Iin14 ;
|
||||
wire Iin6 ;
|
||||
wire Iin5 ;
|
||||
wire Iin0 ;
|
||||
wire Itmp42 ;
|
||||
wire Iin24 ;
|
||||
wire Iin22 ;
|
||||
wire Itmp29 ;
|
||||
|
||||
// --- instances
|
||||
A_2C_B_X1 IC2Els0 (.y(Itmp29 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els1 (.y(Itmp30 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els2 (.y(Itmp31 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els3 (.y(Itmp32 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els4 (.y(Itmp33 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els5 (.y(Itmp34 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els6 (.y(Itmp35 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els7 (.y(Itmp36 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els8 (.y(Itmp37 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els9 (.y(Itmp38 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els10 (.y(Itmp39 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els11 (.y(Itmp40 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els12 (.y(Itmp41 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els13 (.y(Itmp43 ), .c1(Itmp29 ), .c2(Itmp30 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els14 (.y(Itmp44 ), .c1(Itmp31 ), .c2(Itmp32 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els15 (.y(Itmp45 ), .c1(Itmp33 ), .c2(Itmp34 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els16 (.y(Itmp46 ), .c1(Itmp35 ), .c2(Itmp36 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els17 (.y(Itmp47 ), .c1(Itmp37 ), .c2(Itmp38 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els18 (.y(Itmp48 ), .c1(Itmp39 ), .c2(Itmp40 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els19 (.y(Itmp49 ), .c1(Itmp41 ), .c2(Itmp42 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els20 (.y(Itmp50 ), .c1(Itmp43 ), .c2(Itmp44 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els21 (.y(Itmp51 ), .c1(Itmp45 ), .c2(Itmp46 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els0 (.y(Itmp42 ), .c1(Iin26 ), .c2(Iin27 ), .c3(Iin28 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els1 (.y(Itmp52 ), .c1(Itmp47 ), .c2(Itmp48 ), .c3(Itmp49 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els2 (.y(out), .c1(Itmp50 ), .c2(Itmp51 ), .c3(Itmp52 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,121 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0ctree_330_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , Iin29 , out, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin0 ;
|
||||
input Iin1 ;
|
||||
input Iin2 ;
|
||||
input Iin3 ;
|
||||
input Iin4 ;
|
||||
input Iin5 ;
|
||||
input Iin6 ;
|
||||
input Iin7 ;
|
||||
input Iin8 ;
|
||||
input Iin9 ;
|
||||
input Iin10 ;
|
||||
input Iin11 ;
|
||||
input Iin12 ;
|
||||
input Iin13 ;
|
||||
input Iin14 ;
|
||||
input Iin15 ;
|
||||
input Iin16 ;
|
||||
input Iin17 ;
|
||||
input Iin18 ;
|
||||
input Iin19 ;
|
||||
input Iin20 ;
|
||||
input Iin21 ;
|
||||
input Iin22 ;
|
||||
input Iin23 ;
|
||||
input Iin24 ;
|
||||
input Iin25 ;
|
||||
input Iin26 ;
|
||||
input Iin27 ;
|
||||
input Iin28 ;
|
||||
input Iin29 ;
|
||||
output out;
|
||||
|
||||
// -- signals ---
|
||||
wire Itmp35 ;
|
||||
wire Iin7 ;
|
||||
wire Itmp49 ;
|
||||
wire Itmp44 ;
|
||||
wire Iin3 ;
|
||||
wire Iin22 ;
|
||||
wire Iin15 ;
|
||||
wire Iin29 ;
|
||||
wire Iin1 ;
|
||||
wire Iin17 ;
|
||||
wire Iin9 ;
|
||||
wire Iin4 ;
|
||||
wire Itmp53 ;
|
||||
wire Itmp32 ;
|
||||
wire Iin14 ;
|
||||
wire Itmp46 ;
|
||||
wire Iin13 ;
|
||||
wire Iin10 ;
|
||||
wire Itmp47 ;
|
||||
wire Iin23 ;
|
||||
wire Iin8 ;
|
||||
wire Iin25 ;
|
||||
wire Iin12 ;
|
||||
wire Itmp45 ;
|
||||
wire Iin24 ;
|
||||
wire Itmp33 ;
|
||||
wire Iin26 ;
|
||||
wire Iin0 ;
|
||||
wire Iin28 ;
|
||||
wire Itmp50 ;
|
||||
wire Iin16 ;
|
||||
wire Itmp36 ;
|
||||
wire Iin11 ;
|
||||
wire Itmp34 ;
|
||||
wire Itmp31 ;
|
||||
wire Iin18 ;
|
||||
wire Itmp51 ;
|
||||
wire Itmp38 ;
|
||||
wire Itmp30 ;
|
||||
wire Itmp37 ;
|
||||
wire Iin5 ;
|
||||
wire Iin20 ;
|
||||
wire Itmp48 ;
|
||||
wire Itmp43 ;
|
||||
wire Itmp52 ;
|
||||
wire Iin27 ;
|
||||
wire Itmp42 ;
|
||||
wire Itmp41 ;
|
||||
wire Iin21 ;
|
||||
wire Iin6 ;
|
||||
wire Iin19 ;
|
||||
wire out ;
|
||||
wire Itmp54 ;
|
||||
wire Iin2 ;
|
||||
wire Itmp40 ;
|
||||
wire Itmp39 ;
|
||||
|
||||
// --- instances
|
||||
A_2C_B_X1 IC2Els0 (.y(Itmp30 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els1 (.y(Itmp31 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els2 (.y(Itmp32 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els3 (.y(Itmp33 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els4 (.y(Itmp34 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els5 (.y(Itmp35 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els6 (.y(Itmp36 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els7 (.y(Itmp37 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els8 (.y(Itmp38 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els9 (.y(Itmp39 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els10 (.y(Itmp40 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els11 (.y(Itmp41 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els12 (.y(Itmp42 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els13 (.y(Itmp43 ), .c1(Iin26 ), .c2(Iin27 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els14 (.y(Itmp44 ), .c1(Iin28 ), .c2(Iin29 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els15 (.y(Itmp45 ), .c1(Itmp30 ), .c2(Itmp31 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els16 (.y(Itmp46 ), .c1(Itmp32 ), .c2(Itmp33 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els17 (.y(Itmp47 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els18 (.y(Itmp48 ), .c1(Itmp36 ), .c2(Itmp37 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els19 (.y(Itmp49 ), .c1(Itmp38 ), .c2(Itmp39 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els20 (.y(Itmp50 ), .c1(Itmp40 ), .c2(Itmp41 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els21 (.y(Itmp52 ), .c1(Itmp45 ), .c2(Itmp46 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els22 (.y(Itmp53 ), .c1(Itmp47 ), .c2(Itmp48 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els0 (.y(Itmp51 ), .c1(Itmp42 ), .c2(Itmp43 ), .c3(Itmp44 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els1 (.y(Itmp54 ), .c1(Itmp49 ), .c2(Itmp50 ), .c3(Itmp51 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els2 (.y(out), .c1(Itmp52 ), .c2(Itmp53 ), .c3(Itmp54 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,123 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0ctree_331_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , Iin29 , Iin30 , out, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin0 ;
|
||||
input Iin1 ;
|
||||
input Iin2 ;
|
||||
input Iin3 ;
|
||||
input Iin4 ;
|
||||
input Iin5 ;
|
||||
input Iin6 ;
|
||||
input Iin7 ;
|
||||
input Iin8 ;
|
||||
input Iin9 ;
|
||||
input Iin10 ;
|
||||
input Iin11 ;
|
||||
input Iin12 ;
|
||||
input Iin13 ;
|
||||
input Iin14 ;
|
||||
input Iin15 ;
|
||||
input Iin16 ;
|
||||
input Iin17 ;
|
||||
input Iin18 ;
|
||||
input Iin19 ;
|
||||
input Iin20 ;
|
||||
input Iin21 ;
|
||||
input Iin22 ;
|
||||
input Iin23 ;
|
||||
input Iin24 ;
|
||||
input Iin25 ;
|
||||
input Iin26 ;
|
||||
input Iin27 ;
|
||||
input Iin28 ;
|
||||
input Iin29 ;
|
||||
input Iin30 ;
|
||||
output out;
|
||||
|
||||
// -- signals ---
|
||||
wire Iin22 ;
|
||||
wire Iin6 ;
|
||||
wire Itmp32 ;
|
||||
wire Iin25 ;
|
||||
wire Iin15 ;
|
||||
wire Itmp31 ;
|
||||
wire Iin28 ;
|
||||
wire Iin21 ;
|
||||
wire Iin19 ;
|
||||
wire Iin18 ;
|
||||
wire Itmp47 ;
|
||||
wire Iin12 ;
|
||||
wire Iin5 ;
|
||||
wire Iin23 ;
|
||||
wire Itmp52 ;
|
||||
wire Iin7 ;
|
||||
wire Itmp33 ;
|
||||
wire Iin11 ;
|
||||
wire Itmp45 ;
|
||||
wire Iin27 ;
|
||||
wire Itmp38 ;
|
||||
wire Iin2 ;
|
||||
wire Iin17 ;
|
||||
wire Iin16 ;
|
||||
wire out ;
|
||||
wire Iin1 ;
|
||||
wire Itmp37 ;
|
||||
wire Iin10 ;
|
||||
wire Itmp44 ;
|
||||
wire Itmp36 ;
|
||||
wire Itmp55 ;
|
||||
wire Itmp41 ;
|
||||
wire Iin9 ;
|
||||
wire Iin3 ;
|
||||
wire Iin30 ;
|
||||
wire Iin29 ;
|
||||
wire Itmp48 ;
|
||||
wire Itmp40 ;
|
||||
wire Iin4 ;
|
||||
wire Itmp50 ;
|
||||
wire Itmp46 ;
|
||||
wire Iin20 ;
|
||||
wire Iin13 ;
|
||||
wire Itmp51 ;
|
||||
wire Itmp43 ;
|
||||
wire Itmp34 ;
|
||||
wire Iin24 ;
|
||||
wire Itmp53 ;
|
||||
wire Itmp42 ;
|
||||
wire Iin14 ;
|
||||
wire Iin8 ;
|
||||
wire Itmp49 ;
|
||||
wire Iin0 ;
|
||||
wire Iin26 ;
|
||||
wire Itmp54 ;
|
||||
wire Itmp39 ;
|
||||
wire Itmp35 ;
|
||||
|
||||
// --- instances
|
||||
A_2C_B_X1 IC2Els0 (.y(Itmp31 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els1 (.y(Itmp32 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els2 (.y(Itmp33 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els3 (.y(Itmp34 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els4 (.y(Itmp35 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els5 (.y(Itmp36 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els6 (.y(Itmp37 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els7 (.y(Itmp38 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els8 (.y(Itmp39 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els9 (.y(Itmp40 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els10 (.y(Itmp41 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els11 (.y(Itmp42 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els12 (.y(Itmp43 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els13 (.y(Itmp44 ), .c1(Iin26 ), .c2(Iin27 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els14 (.y(Itmp46 ), .c1(Itmp31 ), .c2(Itmp32 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els15 (.y(Itmp47 ), .c1(Itmp33 ), .c2(Itmp34 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els16 (.y(Itmp48 ), .c1(Itmp35 ), .c2(Itmp36 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els17 (.y(Itmp49 ), .c1(Itmp37 ), .c2(Itmp38 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els18 (.y(Itmp50 ), .c1(Itmp39 ), .c2(Itmp40 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els19 (.y(Itmp51 ), .c1(Itmp41 ), .c2(Itmp42 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els20 (.y(Itmp53 ), .c1(Itmp46 ), .c2(Itmp47 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els21 (.y(Itmp54 ), .c1(Itmp48 ), .c2(Itmp49 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els0 (.y(Itmp45 ), .c1(Iin28 ), .c2(Iin29 ), .c3(Iin30 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els1 (.y(Itmp52 ), .c1(Itmp43 ), .c2(Itmp44 ), .c3(Itmp45 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els2 (.y(Itmp55 ), .c1(Itmp50 ), .c2(Itmp51 ), .c3(Itmp52 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els3 (.y(out), .c1(Itmp53 ), .c2(Itmp54 ), .c3(Itmp55 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,135 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0ctree_332_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , Iin29 , Iin30 , Iin31 , out, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin0 ;
|
||||
input Iin1 ;
|
||||
input Iin2 ;
|
||||
input Iin3 ;
|
||||
input Iin4 ;
|
||||
input Iin5 ;
|
||||
input Iin6 ;
|
||||
input Iin7 ;
|
||||
input Iin8 ;
|
||||
input Iin9 ;
|
||||
input Iin10 ;
|
||||
input Iin11 ;
|
||||
input Iin12 ;
|
||||
input Iin13 ;
|
||||
input Iin14 ;
|
||||
input Iin15 ;
|
||||
input Iin16 ;
|
||||
input Iin17 ;
|
||||
input Iin18 ;
|
||||
input Iin19 ;
|
||||
input Iin20 ;
|
||||
input Iin21 ;
|
||||
input Iin22 ;
|
||||
input Iin23 ;
|
||||
input Iin24 ;
|
||||
input Iin25 ;
|
||||
input Iin26 ;
|
||||
input Iin27 ;
|
||||
input Iin28 ;
|
||||
input Iin29 ;
|
||||
input Iin30 ;
|
||||
input Iin31 ;
|
||||
output out;
|
||||
|
||||
// -- signals ---
|
||||
wire Itmp61 ;
|
||||
wire Itmp51 ;
|
||||
wire Iin21 ;
|
||||
wire Itmp40 ;
|
||||
wire Itmp59 ;
|
||||
wire Itmp52 ;
|
||||
wire Itmp36 ;
|
||||
wire Itmp50 ;
|
||||
wire Itmp42 ;
|
||||
wire Itmp44 ;
|
||||
wire Iin19 ;
|
||||
wire Iin17 ;
|
||||
wire Iin8 ;
|
||||
wire Itmp49 ;
|
||||
wire Itmp48 ;
|
||||
wire Itmp45 ;
|
||||
wire Itmp56 ;
|
||||
wire Itmp54 ;
|
||||
wire Iin20 ;
|
||||
wire Itmp53 ;
|
||||
wire Itmp46 ;
|
||||
wire Itmp43 ;
|
||||
wire Itmp39 ;
|
||||
wire Itmp35 ;
|
||||
wire Iin15 ;
|
||||
wire Iin12 ;
|
||||
wire Iin11 ;
|
||||
wire Iin10 ;
|
||||
wire Itmp33 ;
|
||||
wire Iin27 ;
|
||||
wire Iin16 ;
|
||||
wire Iin13 ;
|
||||
wire Iin2 ;
|
||||
wire Itmp57 ;
|
||||
wire Iin7 ;
|
||||
wire Itmp58 ;
|
||||
wire Iin5 ;
|
||||
wire Iin25 ;
|
||||
wire Iin22 ;
|
||||
wire Iin31 ;
|
||||
wire Itmp34 ;
|
||||
wire Itmp38 ;
|
||||
wire Iin1 ;
|
||||
wire Itmp32 ;
|
||||
wire out ;
|
||||
wire Iin26 ;
|
||||
wire Iin18 ;
|
||||
wire Iin30 ;
|
||||
wire Itmp41 ;
|
||||
wire Itmp37 ;
|
||||
wire Iin6 ;
|
||||
wire Iin4 ;
|
||||
wire Iin24 ;
|
||||
wire Iin9 ;
|
||||
wire Iin0 ;
|
||||
wire Itmp60 ;
|
||||
wire Iin23 ;
|
||||
wire Itmp47 ;
|
||||
wire Iin3 ;
|
||||
wire Iin28 ;
|
||||
wire Itmp55 ;
|
||||
wire Iin14 ;
|
||||
wire Iin29 ;
|
||||
|
||||
// --- instances
|
||||
A_2C_B_X1 IC2Els0 (.y(Itmp32 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els1 (.y(Itmp33 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els2 (.y(Itmp34 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els3 (.y(Itmp35 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els4 (.y(Itmp36 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els5 (.y(Itmp37 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els6 (.y(Itmp38 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els7 (.y(Itmp39 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els8 (.y(Itmp40 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els9 (.y(Itmp41 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els10 (.y(Itmp42 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els11 (.y(Itmp43 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els12 (.y(Itmp44 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els13 (.y(Itmp45 ), .c1(Iin26 ), .c2(Iin27 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els14 (.y(Itmp46 ), .c1(Iin28 ), .c2(Iin29 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els15 (.y(Itmp47 ), .c1(Iin30 ), .c2(Iin31 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els16 (.y(Itmp48 ), .c1(Itmp32 ), .c2(Itmp33 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els17 (.y(Itmp49 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els18 (.y(Itmp50 ), .c1(Itmp36 ), .c2(Itmp37 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els19 (.y(Itmp51 ), .c1(Itmp38 ), .c2(Itmp39 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els20 (.y(Itmp52 ), .c1(Itmp40 ), .c2(Itmp41 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els21 (.y(Itmp53 ), .c1(Itmp42 ), .c2(Itmp43 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els22 (.y(Itmp54 ), .c1(Itmp44 ), .c2(Itmp45 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els23 (.y(Itmp55 ), .c1(Itmp46 ), .c2(Itmp47 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els24 (.y(Itmp56 ), .c1(Itmp48 ), .c2(Itmp49 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els25 (.y(Itmp57 ), .c1(Itmp50 ), .c2(Itmp51 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els26 (.y(Itmp58 ), .c1(Itmp52 ), .c2(Itmp53 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els27 (.y(Itmp59 ), .c1(Itmp54 ), .c2(Itmp55 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els28 (.y(Itmp60 ), .c1(Itmp56 ), .c2(Itmp57 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els29 (.y(Itmp61 ), .c1(Itmp58 ), .c2(Itmp59 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els30 (.y(out), .c1(Itmp60 ), .c2(Itmp61 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,23 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0ctree_34_4(Iin0 , Iin1 , Iin2 , Iin3 , out, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin0 ;
|
||||
input Iin1 ;
|
||||
input Iin2 ;
|
||||
input Iin3 ;
|
||||
output out;
|
||||
|
||||
// -- signals ---
|
||||
wire Itmp4 ;
|
||||
wire Itmp5 ;
|
||||
wire Iin0 ;
|
||||
wire Iin2 ;
|
||||
wire Iin1 ;
|
||||
wire out ;
|
||||
wire Iin3 ;
|
||||
|
||||
// --- instances
|
||||
A_2C_B_X1 IC2Els0 (.y(Itmp4 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els1 (.y(Itmp5 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els2 (.y(out), .c1(Itmp4 ), .c2(Itmp5 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,31 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0ctree_37_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , out, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin0 ;
|
||||
input Iin1 ;
|
||||
input Iin2 ;
|
||||
input Iin3 ;
|
||||
input Iin4 ;
|
||||
input Iin5 ;
|
||||
input Iin6 ;
|
||||
output out;
|
||||
|
||||
// -- signals ---
|
||||
wire Iin5 ;
|
||||
wire Iin0 ;
|
||||
wire out ;
|
||||
wire Iin1 ;
|
||||
wire Iin4 ;
|
||||
wire Iin2 ;
|
||||
wire Iin3 ;
|
||||
wire Itmp7 ;
|
||||
wire Itmp9 ;
|
||||
wire Itmp8 ;
|
||||
wire Iin6 ;
|
||||
|
||||
// --- instances
|
||||
A_2C_B_X1 IC2Els0 (.y(Itmp7 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els1 (.y(Itmp8 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els0 (.y(Itmp9 ), .c1(Iin4 ), .c2(Iin5 ), .c3(Iin6 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els1 (.y(out), .c1(Itmp7 ), .c2(Itmp8 ), .c3(Itmp9 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,41 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0ctree_39_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , out, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin0 ;
|
||||
input Iin1 ;
|
||||
input Iin2 ;
|
||||
input Iin3 ;
|
||||
input Iin4 ;
|
||||
input Iin5 ;
|
||||
input Iin6 ;
|
||||
input Iin7 ;
|
||||
input Iin8 ;
|
||||
output out;
|
||||
|
||||
// -- signals ---
|
||||
wire Iin3 ;
|
||||
wire Iin2 ;
|
||||
wire Iin6 ;
|
||||
wire Itmp10 ;
|
||||
wire Iin1 ;
|
||||
wire Itmp13 ;
|
||||
wire Iin8 ;
|
||||
wire Iin7 ;
|
||||
wire Iin4 ;
|
||||
wire Itmp12 ;
|
||||
wire Iin5 ;
|
||||
wire Itmp9 ;
|
||||
wire Itmp11 ;
|
||||
wire Iin0 ;
|
||||
wire out ;
|
||||
wire Itmp14 ;
|
||||
|
||||
// --- instances
|
||||
A_2C_B_X1 IC2Els0 (.y(Itmp9 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els1 (.y(Itmp10 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els2 (.y(Itmp11 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els3 (.y(Itmp13 ), .c1(Itmp9 ), .c2(Itmp10 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els4 (.y(Itmp14 ), .c1(Itmp11 ), .c2(Itmp12 ), .vdd(vdd), .vss(vss));
|
||||
A_2C_B_X1 IC2Els5 (.y(out), .c1(Itmp13 ), .c2(Itmp14 ), .vdd(vdd), .vss(vss));
|
||||
A_3C_B_X1 IC3Els0 (.y(Itmp12 ), .c1(Iin6 ), .c2(Iin7 ), .c3(Iin8 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
File diff suppressed because one or more lines are too long
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
File diff suppressed because one or more lines are too long
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,80 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_78_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iin_d4_d0 , Iin_d4_d1 , Iin_d5_d0 , Iin_d5_d1 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d0_d0 ;
|
||||
input Iin_d0_d1 ;
|
||||
input Iin_d1_d0 ;
|
||||
input Iin_d1_d1 ;
|
||||
input Iin_d2_d0 ;
|
||||
input Iin_d2_d1 ;
|
||||
input Iin_d3_d0 ;
|
||||
input Iin_d3_d1 ;
|
||||
input Iin_d4_d0 ;
|
||||
input Iin_d4_d1 ;
|
||||
input Iin_d5_d0 ;
|
||||
input Iin_d5_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// -- signals ---
|
||||
wire Iin_d3_d1 ;
|
||||
wire Iatree7_in2 ;
|
||||
wire Iatree5_in1 ;
|
||||
wire Iin_d5_d0 ;
|
||||
output Iout0 ;
|
||||
output Iout6 ;
|
||||
wire Iatree6_in0 ;
|
||||
wire Iin_tX5_out0 ;
|
||||
output Iout7 ;
|
||||
wire Iatree3_in2 ;
|
||||
wire Iin_d1_d0 ;
|
||||
wire Iatree7_in1 ;
|
||||
wire Iin_tX3_out0 ;
|
||||
wire Iatree7_in0 ;
|
||||
wire Iin_d0_d0 ;
|
||||
wire Iin_d2_d0 ;
|
||||
wire Iin_d1_d1 ;
|
||||
output Iout5 ;
|
||||
output Iout3 ;
|
||||
wire Iatree7_in4 ;
|
||||
output Iout2 ;
|
||||
wire Iin_d4_d0 ;
|
||||
wire Iin_tX4_out0 ;
|
||||
wire Iin_d2_d1 ;
|
||||
wire Iin_d5_d1 ;
|
||||
wire Iin_d0_d1 ;
|
||||
wire Iatree7_in5 ;
|
||||
wire Iin_d3_d0 ;
|
||||
wire Iin_d4_d1 ;
|
||||
output Iout4 ;
|
||||
output Iout1 ;
|
||||
wire Iatree7_in3 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree0 (.Iin0 (Iatree6_in0 ), .Iin1 (Iatree5_in1 ), .Iin2 (Iatree3_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree1 (.Iin0 (Iatree7_in0 ), .Iin1 (Iatree5_in1 ), .Iin2 (Iatree3_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree2 (.Iin0 (Iatree6_in0 ), .Iin1 (Iatree7_in1 ), .Iin2 (Iatree3_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout2 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree3 (.Iin0 (Iatree7_in0 ), .Iin1 (Iatree7_in1 ), .Iin2 (Iatree3_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout3 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree4 (.Iin0 (Iatree6_in0 ), .Iin1 (Iatree5_in1 ), .Iin2 (Iatree7_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout4 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree5 (.Iin0 (Iatree7_in0 ), .Iin1 (Iatree5_in1 ), .Iin2 (Iatree7_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout5 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree6 (.Iin0 (Iatree6_in0 ), .Iin1 (Iatree7_in1 ), .Iin2 (Iatree7_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout6 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree7 (.Iin0 (Iatree7_in0 ), .Iin1 (Iatree7_in1 ), .Iin2 (Iatree7_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout7 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX0 (.in(Iin_d0_d1 ), .Iout0 (Iatree7_in0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX1 (.in(Iin_d1_d1 ), .Iout0 (Iatree7_in1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX2 (.in(Iin_d2_d1 ), .Iout0 (Iatree7_in2 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX3 (.in(Iin_d3_d1 ), .Iout0 (Iin_tX3_out0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX4 (.in(Iin_d4_d1 ), .Iout0 (Iin_tX4_out0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX5 (.in(Iin_d5_d1 ), .Iout0 (Iin_tX5_out0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX0 (.in(Iin_d0_d0 ), .Iout0 (Iatree6_in0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX1 (.in(Iin_d1_d0 ), .Iout0 (Iatree5_in1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX2 (.in(Iin_d2_d0 ), .Iout0 (Iatree3_in2 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX3 (.in(Iin_d3_d0 ), .Iout0 (Iatree7_in3 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX4 (.in(Iin_d4_d0 ), .Iout0 (Iatree7_in4 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX5 (.in(Iin_d5_d0 ), .Iout0 (Iatree7_in5 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,55 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_33_76_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , en, Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d0_d0 ;
|
||||
input Iin_d0_d1 ;
|
||||
input Iin_d1_d0 ;
|
||||
input Iin_d1_d1 ;
|
||||
input Iin_d2_d0 ;
|
||||
input Iin_d2_d1 ;
|
||||
input en;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// -- signals ---
|
||||
wire Idecoder_final_refresh_d1_d0 ;
|
||||
wire Ien_ands_t2_y ;
|
||||
output Iout1 ;
|
||||
wire Ien_ands_f0_y ;
|
||||
wire Iin_d1_d0 ;
|
||||
wire Ien_ands_t0_y ;
|
||||
output Iout5 ;
|
||||
wire Idecoder_final_refresh_d2_d0 ;
|
||||
wire Iin_d2_d1 ;
|
||||
wire Iin_d0_d0 ;
|
||||
wire Iin_d0_d1 ;
|
||||
wire Idecoder_final_refresh_d0_d1 ;
|
||||
wire Idecoder_final_refresh_d0_d0 ;
|
||||
wire Idecoder_final_refresh_d1_d1 ;
|
||||
wire Ien_ands_f2_y ;
|
||||
wire Iin_d2_d0 ;
|
||||
output Iout4 ;
|
||||
wire Ien_ands_t1_y ;
|
||||
output Iout0 ;
|
||||
wire Ien_ands_f1_y ;
|
||||
wire Idecoder_final_refresh_d2_d1 ;
|
||||
wire Iin_d1_d1 ;
|
||||
wire Isb_en_out0 ;
|
||||
output Iout3 ;
|
||||
output Iout2 ;
|
||||
wire en;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4 Idecoder (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_36_4 Isb_en (.in(en), .Iout0 (Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t0 (.y(Ien_ands_t0_y ), .a(Iin_d0_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t1 (.y(Ien_ands_t1_y ), .a(Iin_d1_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t2 (.y(Ien_ands_t2_y ), .a(Iin_d2_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f0 (.y(Ien_ands_f0_y ), .a(Iin_d0_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f1 (.y(Ien_ands_f1_y ), .a(Iin_d1_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f2 (.y(Ien_ands_f2_y ), .a(Iin_d2_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,123 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iin_d4_d0 , Iin_d4_d1 , en, Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , Iout8 , Iout9 , Iout10 , Iout11 , Iout12 , Iout13 , Iout14 , Iout15 , Iout16 , Iout17 , Iout18 , Iout19 , Iout20 , Iout21 , Iout22 , Iout23 , Iout24 , Iout25 , Iout26 , Iout27 , Iout28 , Iout29 , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d0_d0 ;
|
||||
input Iin_d0_d1 ;
|
||||
input Iin_d1_d0 ;
|
||||
input Iin_d1_d1 ;
|
||||
input Iin_d2_d0 ;
|
||||
input Iin_d2_d1 ;
|
||||
input Iin_d3_d0 ;
|
||||
input Iin_d3_d1 ;
|
||||
input Iin_d4_d0 ;
|
||||
input Iin_d4_d1 ;
|
||||
input en;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// -- signals ---
|
||||
wire Iin_d2_d1 ;
|
||||
wire Ien_ands_t0_y ;
|
||||
wire Iin_d0_d0 ;
|
||||
output Iout18 ;
|
||||
output Iout2 ;
|
||||
wire Iin_d4_d1 ;
|
||||
wire Ien_ands_t1_y ;
|
||||
output Iout4 ;
|
||||
wire Iin_d4_d0 ;
|
||||
wire Idecoder_final_refresh_d0_d1 ;
|
||||
output Iout25 ;
|
||||
output Iout1 ;
|
||||
wire Iin_d3_d0 ;
|
||||
output Iout10 ;
|
||||
output Iout7 ;
|
||||
output Iout0 ;
|
||||
output Iout27 ;
|
||||
output Iout26 ;
|
||||
output Iout19 ;
|
||||
wire Idecoder_final_refresh_d1_d1 ;
|
||||
output Iout14 ;
|
||||
output Iout9 ;
|
||||
output Iout6 ;
|
||||
output Iout16 ;
|
||||
wire Iin_d0_d1 ;
|
||||
wire Ien_ands_f1_y ;
|
||||
wire Iin_d2_d0 ;
|
||||
wire Idecoder_final_refresh_d4_d0 ;
|
||||
output Iout21 ;
|
||||
output Iout12 ;
|
||||
wire Ien_ands_t3_y ;
|
||||
wire Idecoder_final_refresh_d2_d1 ;
|
||||
output Iout11 ;
|
||||
wire Ien_ands_t4_y ;
|
||||
wire Ien_ands_f3_y ;
|
||||
output Iout24 ;
|
||||
output Iout5 ;
|
||||
wire Isb_en_out0 ;
|
||||
wire Idecoder_final_refresh_d3_d0 ;
|
||||
wire Idecoder_final_refresh_d1_d0 ;
|
||||
output Iout8 ;
|
||||
wire Iin_d1_d1 ;
|
||||
output Iout20 ;
|
||||
output Iout17 ;
|
||||
output Iout3 ;
|
||||
wire Idecoder_final_refresh_d3_d1 ;
|
||||
wire Idecoder_final_refresh_d0_d0 ;
|
||||
output Iout23 ;
|
||||
output Iout22 ;
|
||||
wire en;
|
||||
wire Idecoder_final_refresh_d4_d1 ;
|
||||
wire Ien_ands_t2_y ;
|
||||
wire Ien_ands_f2_y ;
|
||||
wire Ien_ands_f0_y ;
|
||||
output Iout28 ;
|
||||
wire Ien_ands_f4_y ;
|
||||
output Iout29 ;
|
||||
output Iout13 ;
|
||||
wire Iin_d1_d0 ;
|
||||
wire Iin_d3_d1 ;
|
||||
wire Idecoder_final_refresh_d2_d0 ;
|
||||
output Iout15 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4 Idecoder (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iin_d3_d0 (Ien_ands_f3_y ), .Iin_d3_d1 (Ien_ands_t3_y ), .Iin_d4_d0 (Ien_ands_f4_y ), .Iin_d4_d1 (Ien_ands_t4_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Iout6 (Iout6 ), .Iout7 (Iout7 ), .Iout8 (Iout8 ), .Iout9 (Iout9 ), .Iout10 (Iout10 ), .Iout11 (Iout11 ), .Iout12 (Iout12 ), .Iout13 (Iout13 ), .Iout14 (Iout14 ), .Iout15 (Iout15 ), .Iout16 (Iout16 ), .Iout17 (Iout17 ), .Iout18 (Iout18 ), .Iout19 (Iout19 ), .Iout20 (Iout20 ), .Iout21 (Iout21 ), .Iout22 (Iout22 ), .Iout23 (Iout23 ), .Iout24 (Iout24 ), .Iout25 (Iout25 ), .Iout26 (Iout26 ), .Iout27 (Iout27 ), .Iout28 (Iout28 ), .Iout29 (Iout29 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .Ifinal_refresh_d3_d0 (Idecoder_final_refresh_d3_d0 ), .Ifinal_refresh_d3_d1 (Idecoder_final_refresh_d3_d1 ), .Ifinal_refresh_d4_d0 (Idecoder_final_refresh_d4_d0 ), .Ifinal_refresh_d4_d1 (Idecoder_final_refresh_d4_d1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_310_4 Isb_en (.in(en), .Iout0 (Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t0 (.y(Ien_ands_t0_y ), .a(Iin_d0_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t1 (.y(Ien_ands_t1_y ), .a(Iin_d1_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t2 (.y(Ien_ands_t2_y ), .a(Iin_d2_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t3 (.y(Ien_ands_t3_y ), .a(Iin_d3_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t4 (.y(Ien_ands_t4_y ), .a(Iin_d4_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f0 (.y(Ien_ands_f0_y ), .a(Iin_d0_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f1 (.y(Ien_ands_f1_y ), .a(Iin_d1_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f2 (.y(Ien_ands_f2_y ), .a(Iin_d2_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f3 (.y(Ien_ands_f3_y ), .a(Iin_d3_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f4 (.y(Ien_ands_f4_y ), .a(Iin_d4_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,193 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_36_760_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iin_d4_d0 , Iin_d4_d1 , Iin_d5_d0 , Iin_d5_d1 , en, Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , Iout8 , Iout9 , Iout10 , Iout11 , Iout12 , Iout13 , Iout14 , Iout15 , Iout16 , Iout17 , Iout18 , Iout19 , Iout20 , Iout21 , Iout22 , Iout23 , Iout24 , Iout25 , Iout26 , Iout27 , Iout28 , Iout29 , Iout30 , Iout31 , Iout32 , Iout33 , Iout34 , Iout35 , Iout36 , Iout37 , Iout38 , Iout39 , Iout40 , Iout41 , Iout42 , Iout43 , Iout44 , Iout45 , Iout46 , Iout47 , Iout48 , Iout49 , Iout50 , Iout51 , Iout52 , Iout53 , Iout54 , Iout55 , Iout56 , Iout57 , Iout58 , Iout59 , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d0_d0 ;
|
||||
input Iin_d0_d1 ;
|
||||
input Iin_d1_d0 ;
|
||||
input Iin_d1_d1 ;
|
||||
input Iin_d2_d0 ;
|
||||
input Iin_d2_d1 ;
|
||||
input Iin_d3_d0 ;
|
||||
input Iin_d3_d1 ;
|
||||
input Iin_d4_d0 ;
|
||||
input Iin_d4_d1 ;
|
||||
input Iin_d5_d0 ;
|
||||
input Iin_d5_d1 ;
|
||||
input en;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// -- signals ---
|
||||
wire Iin_d4_d1 ;
|
||||
wire Ien_ands_t1_y ;
|
||||
wire Ien_ands_t0_y ;
|
||||
output Iout2 ;
|
||||
wire Iin_d1_d0 ;
|
||||
wire Idecoder_final_refresh_d2_d1 ;
|
||||
output Iout56 ;
|
||||
output Iout51 ;
|
||||
output Iout40 ;
|
||||
output Iout36 ;
|
||||
output Iout22 ;
|
||||
output Iout14 ;
|
||||
output Iout59 ;
|
||||
wire Iin_d0_d1 ;
|
||||
output Iout3 ;
|
||||
wire Ien_ands_f4_y ;
|
||||
wire Ien_ands_f3_y ;
|
||||
wire Idecoder_final_refresh_d0_d1 ;
|
||||
output Iout41 ;
|
||||
output Iout26 ;
|
||||
wire en;
|
||||
output Iout50 ;
|
||||
output Iout7 ;
|
||||
wire Idecoder_final_refresh_d5_d1 ;
|
||||
output Iout47 ;
|
||||
output Iout31 ;
|
||||
output Iout25 ;
|
||||
wire Iin_d2_d1 ;
|
||||
wire Idecoder_final_refresh_d1_d1 ;
|
||||
output Iout58 ;
|
||||
wire Ien_ands_t5_y ;
|
||||
wire Iin_d5_d1 ;
|
||||
wire Idecoder_final_refresh_d0_d0 ;
|
||||
output Iout44 ;
|
||||
output Iout15 ;
|
||||
wire Ien_ands_f5_y ;
|
||||
output Iout27 ;
|
||||
output Iout57 ;
|
||||
output Iout23 ;
|
||||
wire Ien_ands_f0_y ;
|
||||
output Iout55 ;
|
||||
output Iout38 ;
|
||||
output Iout18 ;
|
||||
wire Isb_en_out0 ;
|
||||
output Iout53 ;
|
||||
output Iout21 ;
|
||||
output Iout10 ;
|
||||
wire Iin_d1_d1 ;
|
||||
output Iout1 ;
|
||||
output Iout17 ;
|
||||
wire Ien_ands_t3_y ;
|
||||
wire Iin_d3_d0 ;
|
||||
wire Idecoder_final_refresh_d5_d0 ;
|
||||
output Iout6 ;
|
||||
output Iout34 ;
|
||||
wire Idecoder_final_refresh_d4_d1 ;
|
||||
output Iout33 ;
|
||||
output Iout29 ;
|
||||
output Iout20 ;
|
||||
wire Idecoder_final_refresh_d3_d1 ;
|
||||
output Iout52 ;
|
||||
wire Ien_ands_f2_y ;
|
||||
wire Iin_d5_d0 ;
|
||||
output Iout37 ;
|
||||
wire Ien_ands_t4_y ;
|
||||
wire Idecoder_final_refresh_d4_d0 ;
|
||||
output Iout39 ;
|
||||
output Iout30 ;
|
||||
wire Iin_d2_d0 ;
|
||||
wire Iin_d0_d0 ;
|
||||
output Iout54 ;
|
||||
output Iout49 ;
|
||||
output Iout48 ;
|
||||
output Iout24 ;
|
||||
output Iout16 ;
|
||||
output Iout11 ;
|
||||
output Iout5 ;
|
||||
wire Idecoder_final_refresh_d1_d0 ;
|
||||
output Iout35 ;
|
||||
output Iout4 ;
|
||||
output Iout0 ;
|
||||
wire Ien_ands_f1_y ;
|
||||
wire Iin_d3_d1 ;
|
||||
output Iout32 ;
|
||||
output Iout8 ;
|
||||
output Iout45 ;
|
||||
output Iout42 ;
|
||||
output Iout19 ;
|
||||
output Iout9 ;
|
||||
wire Ien_ands_t2_y ;
|
||||
output Iout46 ;
|
||||
output Iout28 ;
|
||||
output Iout12 ;
|
||||
output Iout43 ;
|
||||
output Iout13 ;
|
||||
wire Iin_d4_d0 ;
|
||||
wire Idecoder_final_refresh_d3_d0 ;
|
||||
wire Idecoder_final_refresh_d2_d0 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4 Idecoder (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iin_d3_d0 (Ien_ands_f3_y ), .Iin_d3_d1 (Ien_ands_t3_y ), .Iin_d4_d0 (Ien_ands_f4_y ), .Iin_d4_d1 (Ien_ands_t4_y ), .Iin_d5_d0 (Ien_ands_f5_y ), .Iin_d5_d1 (Ien_ands_t5_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Iout6 (Iout6 ), .Iout7 (Iout7 ), .Iout8 (Iout8 ), .Iout9 (Iout9 ), .Iout10 (Iout10 ), .Iout11 (Iout11 ), .Iout12 (Iout12 ), .Iout13 (Iout13 ), .Iout14 (Iout14 ), .Iout15 (Iout15 ), .Iout16 (Iout16 ), .Iout17 (Iout17 ), .Iout18 (Iout18 ), .Iout19 (Iout19 ), .Iout20 (Iout20 ), .Iout21 (Iout21 ), .Iout22 (Iout22 ), .Iout23 (Iout23 ), .Iout24 (Iout24 ), .Iout25 (Iout25 ), .Iout26 (Iout26 ), .Iout27 (Iout27 ), .Iout28 (Iout28 ), .Iout29 (Iout29 ), .Iout30 (Iout30 ), .Iout31 (Iout31 ), .Iout32 (Iout32 ), .Iout33 (Iout33 ), .Iout34 (Iout34 ), .Iout35 (Iout35 ), .Iout36 (Iout36 ), .Iout37 (Iout37 ), .Iout38 (Iout38 ), .Iout39 (Iout39 ), .Iout40 (Iout40 ), .Iout41 (Iout41 ), .Iout42 (Iout42 ), .Iout43 (Iout43 ), .Iout44 (Iout44 ), .Iout45 (Iout45 ), .Iout46 (Iout46 ), .Iout47 (Iout47 ), .Iout48 (Iout48 ), .Iout49 (Iout49 ), .Iout50 (Iout50 ), .Iout51 (Iout51 ), .Iout52 (Iout52 ), .Iout53 (Iout53 ), .Iout54 (Iout54 ), .Iout55 (Iout55 ), .Iout56 (Iout56 ), .Iout57 (Iout57 ), .Iout58 (Iout58 ), .Iout59 (Iout59 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .Ifinal_refresh_d3_d0 (Idecoder_final_refresh_d3_d0 ), .Ifinal_refresh_d3_d1 (Idecoder_final_refresh_d3_d1 ), .Ifinal_refresh_d4_d0 (Idecoder_final_refresh_d4_d0 ), .Ifinal_refresh_d4_d1 (Idecoder_final_refresh_d4_d1 ), .Ifinal_refresh_d5_d0 (Idecoder_final_refresh_d5_d0 ), .Ifinal_refresh_d5_d1 (Idecoder_final_refresh_d5_d1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0sigbuf_312_4 Isb_en (.in(en), .Iout0 (Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t0 (.y(Ien_ands_t0_y ), .a(Iin_d0_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t1 (.y(Ien_ands_t1_y ), .a(Iin_d1_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t2 (.y(Ien_ands_t2_y ), .a(Iin_d2_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t3 (.y(Ien_ands_t3_y ), .a(Iin_d3_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t4 (.y(Ien_ands_t4_y ), .a(Iin_d4_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_t5 (.y(Ien_ands_t5_y ), .a(Iin_d5_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f0 (.y(Ien_ands_f0_y ), .a(Iin_d0_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f1 (.y(Ien_ands_f1_y ), .a(Iin_d1_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f2 (.y(Ien_ands_f2_y ), .a(Iin_d2_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f3 (.y(Ien_ands_f3_y ), .a(Iin_d3_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f4 (.y(Ien_ands_f4_y ), .a(Iin_d4_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Ien_ands_f5 (.y(Ien_ands_f5_y ), .a(Iin_d5_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
File diff suppressed because one or more lines are too long
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,56 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Ifinal_refresh_d0_d0 , Ifinal_refresh_d0_d1 , Ifinal_refresh_d1_d0 , Ifinal_refresh_d1_d1 , Ifinal_refresh_d2_d0 , Ifinal_refresh_d2_d1 , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d0_d0 ;
|
||||
input Iin_d0_d1 ;
|
||||
input Iin_d1_d0 ;
|
||||
input Iin_d1_d1 ;
|
||||
input Iin_d2_d0 ;
|
||||
input Iin_d2_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// -- signals ---
|
||||
output Ifinal_refresh_d1_d0 ;
|
||||
output Ifinal_refresh_d1_d1 ;
|
||||
wire Iin_d2_d0 ;
|
||||
wire Iin_d1_d0 ;
|
||||
output Iout0 ;
|
||||
output Iout2 ;
|
||||
wire Iin_d0_d1 ;
|
||||
output Ifinal_refresh_d2_d1 ;
|
||||
wire Iin_d2_d1 ;
|
||||
output Iout1 ;
|
||||
output Ifinal_refresh_d0_d1 ;
|
||||
output Ifinal_refresh_d2_d0 ;
|
||||
output Iout3 ;
|
||||
wire Iin_d0_d0 ;
|
||||
wire Iin_d1_d1 ;
|
||||
output Iout5 ;
|
||||
output Iout4 ;
|
||||
output Ifinal_refresh_d0_d0 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree1 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree2 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout2 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree3 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout3 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree4 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .out(Iout4 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree5 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .out(Iout5 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX0 (.y(Ifinal_refresh_d0_d1 ), .a(Iin_d0_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX1 (.y(Ifinal_refresh_d1_d1 ), .a(Iin_d1_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX2 (.y(Ifinal_refresh_d2_d1 ), .a(Iin_d2_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX0 (.y(Ifinal_refresh_d0_d0 ), .a(Iin_d0_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX1 (.y(Ifinal_refresh_d1_d0 ), .a(Iin_d1_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX2 (.y(Ifinal_refresh_d2_d0 ), .a(Iin_d2_d0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,93 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_34_715_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , Iout8 , Iout9 , Iout10 , Iout11 , Iout12 , Iout13 , Iout14 , Ifinal_refresh_d0_d0 , Ifinal_refresh_d0_d1 , Ifinal_refresh_d1_d0 , Ifinal_refresh_d1_d1 , Ifinal_refresh_d2_d0 , Ifinal_refresh_d2_d1 , Ifinal_refresh_d3_d0 , Ifinal_refresh_d3_d1 , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d0_d0 ;
|
||||
input Iin_d0_d1 ;
|
||||
input Iin_d1_d0 ;
|
||||
input Iin_d1_d1 ;
|
||||
input Iin_d2_d0 ;
|
||||
input Iin_d2_d1 ;
|
||||
input Iin_d3_d0 ;
|
||||
input Iin_d3_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// -- signals ---
|
||||
wire Iin_d2_d0 ;
|
||||
output Ifinal_refresh_d0_d0 ;
|
||||
wire Iin_d2_d1 ;
|
||||
wire Iin_d0_d1 ;
|
||||
output Iout8 ;
|
||||
output Iout13 ;
|
||||
output Ifinal_refresh_d1_d1 ;
|
||||
output Iout9 ;
|
||||
output Ifinal_refresh_d3_d1 ;
|
||||
wire Iin_d0_d0 ;
|
||||
output Iout10 ;
|
||||
output Ifinal_refresh_d0_d1 ;
|
||||
output Ifinal_refresh_d2_d0 ;
|
||||
output Iout11 ;
|
||||
output Iout6 ;
|
||||
output Iout5 ;
|
||||
output Iout4 ;
|
||||
output Iout3 ;
|
||||
wire Iin_d1_d1 ;
|
||||
output Iout12 ;
|
||||
output Iout2 ;
|
||||
output Ifinal_refresh_d3_d0 ;
|
||||
wire Iin_d3_d0 ;
|
||||
output Iout1 ;
|
||||
output Iout0 ;
|
||||
wire Iin_d3_d1 ;
|
||||
output Ifinal_refresh_d1_d0 ;
|
||||
output Ifinal_refresh_d2_d1 ;
|
||||
output Iout14 ;
|
||||
wire Iin_d1_d0 ;
|
||||
output Iout7 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree1 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree2 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout2 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree3 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout3 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree4 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout4 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree5 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout5 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree6 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout6 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree7 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout7 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree8 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout8 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree9 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout9 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree10 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout10 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree11 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout11 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree12 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout12 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree13 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout13 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree14 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout14 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX0 (.y(Ifinal_refresh_d0_d1 ), .a(Iin_d0_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX1 (.y(Ifinal_refresh_d1_d1 ), .a(Iin_d1_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX2 (.y(Ifinal_refresh_d2_d1 ), .a(Iin_d2_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX3 (.y(Ifinal_refresh_d3_d1 ), .a(Iin_d3_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX0 (.y(Ifinal_refresh_d0_d0 ), .a(Iin_d0_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX1 (.y(Ifinal_refresh_d1_d0 ), .a(Iin_d1_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX2 (.y(Ifinal_refresh_d2_d0 ), .a(Iin_d2_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX3 (.y(Ifinal_refresh_d3_d0 ), .a(Iin_d3_d0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,148 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iin_d4_d0 , Iin_d4_d1 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , Iout8 , Iout9 , Iout10 , Iout11 , Iout12 , Iout13 , Iout14 , Iout15 , Iout16 , Iout17 , Iout18 , Iout19 , Iout20 , Iout21 , Iout22 , Iout23 , Iout24 , Iout25 , Iout26 , Iout27 , Iout28 , Iout29 , Ifinal_refresh_d0_d0 , Ifinal_refresh_d0_d1 , Ifinal_refresh_d1_d0 , Ifinal_refresh_d1_d1 , Ifinal_refresh_d2_d0 , Ifinal_refresh_d2_d1 , Ifinal_refresh_d3_d0 , Ifinal_refresh_d3_d1 , Ifinal_refresh_d4_d0 , Ifinal_refresh_d4_d1 , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d0_d0 ;
|
||||
input Iin_d0_d1 ;
|
||||
input Iin_d1_d0 ;
|
||||
input Iin_d1_d1 ;
|
||||
input Iin_d2_d0 ;
|
||||
input Iin_d2_d1 ;
|
||||
input Iin_d3_d0 ;
|
||||
input Iin_d3_d1 ;
|
||||
input Iin_d4_d0 ;
|
||||
input Iin_d4_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// -- signals ---
|
||||
output Iout29 ;
|
||||
output Iout12 ;
|
||||
wire Iin_d3_d1 ;
|
||||
output Iout7 ;
|
||||
output Iout0 ;
|
||||
output Iout28 ;
|
||||
output Iout18 ;
|
||||
output Iout26 ;
|
||||
output Ifinal_refresh_d2_d0 ;
|
||||
output Iout23 ;
|
||||
output Iout6 ;
|
||||
output Iout15 ;
|
||||
output Ifinal_refresh_d3_d0 ;
|
||||
output Iout16 ;
|
||||
wire Iin_d4_d1 ;
|
||||
output Iout17 ;
|
||||
output Iout13 ;
|
||||
output Iout5 ;
|
||||
output Iout20 ;
|
||||
wire Iin_d1_d1 ;
|
||||
output Iout25 ;
|
||||
output Ifinal_refresh_d4_d0 ;
|
||||
wire Iin_d3_d0 ;
|
||||
output Iout9 ;
|
||||
output Ifinal_refresh_d1_d1 ;
|
||||
wire Iin_d4_d0 ;
|
||||
output Iout11 ;
|
||||
output Iout4 ;
|
||||
output Ifinal_refresh_d0_d1 ;
|
||||
wire Iin_d0_d1 ;
|
||||
output Iout10 ;
|
||||
wire Iin_d2_d1 ;
|
||||
output Iout27 ;
|
||||
output Iout24 ;
|
||||
output Ifinal_refresh_d2_d1 ;
|
||||
wire Iin_d0_d0 ;
|
||||
output Ifinal_refresh_d3_d1 ;
|
||||
output Iout1 ;
|
||||
wire Iin_d2_d0 ;
|
||||
output Iout21 ;
|
||||
output Iout14 ;
|
||||
output Iout8 ;
|
||||
output Ifinal_refresh_d1_d0 ;
|
||||
wire Iin_d1_d0 ;
|
||||
output Ifinal_refresh_d4_d1 ;
|
||||
output Iout3 ;
|
||||
output Iout19 ;
|
||||
output Iout2 ;
|
||||
output Ifinal_refresh_d0_d0 ;
|
||||
output Iout22 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree1 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree2 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout2 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree3 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout3 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree4 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout4 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree5 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout5 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree6 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout6 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree7 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout7 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree8 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout8 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree9 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout9 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree10 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout10 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree11 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout11 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree12 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout12 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree13 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout13 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree14 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout14 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree15 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .out(Iout15 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree16 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout16 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree17 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout17 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree18 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout18 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree19 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout19 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree20 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout20 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree21 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout21 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree22 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout22 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree23 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout23 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree24 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout24 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree25 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout25 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree26 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout26 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree27 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout27 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree28 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout28 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_35_4 Iatree29 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .out(Iout29 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX0 (.y(Ifinal_refresh_d0_d1 ), .a(Iin_d0_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX1 (.y(Ifinal_refresh_d1_d1 ), .a(Iin_d1_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX2 (.y(Ifinal_refresh_d2_d1 ), .a(Iin_d2_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX3 (.y(Ifinal_refresh_d3_d1 ), .a(Iin_d3_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX4 (.y(Ifinal_refresh_d4_d1 ), .a(Iin_d4_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX0 (.y(Ifinal_refresh_d0_d0 ), .a(Iin_d0_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX1 (.y(Ifinal_refresh_d1_d0 ), .a(Iin_d1_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX2 (.y(Ifinal_refresh_d2_d0 ), .a(Iin_d2_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX3 (.y(Ifinal_refresh_d3_d0 ), .a(Iin_d3_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX4 (.y(Ifinal_refresh_d4_d0 ), .a(Iin_d4_d0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,248 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iin_d4_d0 , Iin_d4_d1 , Iin_d5_d0 , Iin_d5_d1 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , Iout8 , Iout9 , Iout10 , Iout11 , Iout12 , Iout13 , Iout14 , Iout15 , Iout16 , Iout17 , Iout18 , Iout19 , Iout20 , Iout21 , Iout22 , Iout23 , Iout24 , Iout25 , Iout26 , Iout27 , Iout28 , Iout29 , Iout30 , Iout31 , Iout32 , Iout33 , Iout34 , Iout35 , Iout36 , Iout37 , Iout38 , Iout39 , Iout40 , Iout41 , Iout42 , Iout43 , Iout44 , Iout45 , Iout46 , Iout47 , Iout48 , Iout49 , Iout50 , Iout51 , Iout52 , Iout53 , Iout54 , Iout55 , Iout56 , Iout57 , Iout58 , Iout59 , Ifinal_refresh_d0_d0 , Ifinal_refresh_d0_d1 , Ifinal_refresh_d1_d0 , Ifinal_refresh_d1_d1 , Ifinal_refresh_d2_d0 , Ifinal_refresh_d2_d1 , Ifinal_refresh_d3_d0 , Ifinal_refresh_d3_d1 , Ifinal_refresh_d4_d0 , Ifinal_refresh_d4_d1 , Ifinal_refresh_d5_d0 , Ifinal_refresh_d5_d1 , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
input Iin_d0_d0 ;
|
||||
input Iin_d0_d1 ;
|
||||
input Iin_d1_d0 ;
|
||||
input Iin_d1_d1 ;
|
||||
input Iin_d2_d0 ;
|
||||
input Iin_d2_d1 ;
|
||||
input Iin_d3_d0 ;
|
||||
input Iin_d3_d1 ;
|
||||
input Iin_d4_d0 ;
|
||||
input Iin_d4_d1 ;
|
||||
input Iin_d5_d0 ;
|
||||
input Iin_d5_d1 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// -- signals ---
|
||||
output Iout57 ;
|
||||
output Iout30 ;
|
||||
wire Iin_d1_d1 ;
|
||||
output Iout15 ;
|
||||
output Iout2 ;
|
||||
output Iout49 ;
|
||||
output Iout40 ;
|
||||
output Iout38 ;
|
||||
output Iout43 ;
|
||||
output Iout25 ;
|
||||
output Iout19 ;
|
||||
output Iout12 ;
|
||||
output Ifinal_refresh_d5_d0 ;
|
||||
output Ifinal_refresh_d3_d0 ;
|
||||
wire Iin_d4_d1 ;
|
||||
output Iout28 ;
|
||||
output Iout3 ;
|
||||
output Ifinal_refresh_d2_d0 ;
|
||||
wire Iin_d0_d1 ;
|
||||
output Iout24 ;
|
||||
output Iout7 ;
|
||||
output Iout54 ;
|
||||
output Ifinal_refresh_d4_d0 ;
|
||||
output Iout46 ;
|
||||
output Iout41 ;
|
||||
output Iout35 ;
|
||||
output Iout23 ;
|
||||
output Ifinal_refresh_d4_d1 ;
|
||||
output Iout17 ;
|
||||
output Iout6 ;
|
||||
output Iout1 ;
|
||||
wire Iin_d4_d0 ;
|
||||
output Ifinal_refresh_d0_d0 ;
|
||||
wire Iin_d5_d0 ;
|
||||
output Iout48 ;
|
||||
output Iout33 ;
|
||||
output Iout20 ;
|
||||
output Iout10 ;
|
||||
output Ifinal_refresh_d2_d1 ;
|
||||
output Ifinal_refresh_d1_d1 ;
|
||||
wire Iin_d3_d0 ;
|
||||
output Iout52 ;
|
||||
output Ifinal_refresh_d3_d1 ;
|
||||
wire Iin_d1_d0 ;
|
||||
output Iout36 ;
|
||||
output Iout31 ;
|
||||
output Iout26 ;
|
||||
output Iout59 ;
|
||||
output Iout42 ;
|
||||
output Iout50 ;
|
||||
output Iout45 ;
|
||||
output Iout37 ;
|
||||
output Iout55 ;
|
||||
output Iout21 ;
|
||||
output Iout39 ;
|
||||
output Ifinal_refresh_d5_d1 ;
|
||||
output Iout8 ;
|
||||
output Ifinal_refresh_d1_d0 ;
|
||||
output Iout14 ;
|
||||
output Iout9 ;
|
||||
wire Iin_d3_d1 ;
|
||||
output Iout4 ;
|
||||
output Iout13 ;
|
||||
output Iout0 ;
|
||||
output Iout34 ;
|
||||
output Iout27 ;
|
||||
output Iout22 ;
|
||||
output Iout58 ;
|
||||
output Iout29 ;
|
||||
output Iout16 ;
|
||||
output Iout11 ;
|
||||
wire Iin_d2_d1 ;
|
||||
output Iout51 ;
|
||||
output Iout18 ;
|
||||
output Iout5 ;
|
||||
wire Iin_d5_d1 ;
|
||||
output Iout56 ;
|
||||
output Iout53 ;
|
||||
output Iout44 ;
|
||||
output Ifinal_refresh_d0_d1 ;
|
||||
output Iout32 ;
|
||||
wire Iin_d2_d0 ;
|
||||
wire Iin_d0_d0 ;
|
||||
output Iout47 ;
|
||||
|
||||
// --- instances
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree1 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout1 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree2 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout2 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree3 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout3 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree4 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout4 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree5 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout5 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree6 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout6 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree7 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout7 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree8 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout8 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree9 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout9 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree10 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout10 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree11 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout11 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree12 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout12 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree13 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout13 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree14 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout14 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree15 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout15 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree16 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout16 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree17 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout17 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree18 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout18 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree19 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout19 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree20 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout20 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree21 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout21 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree22 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout22 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree23 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout23 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree24 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout24 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree25 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout25 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree26 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout26 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree27 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout27 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree28 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout28 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree29 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout29 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree30 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout30 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree31 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d0 ), .out(Iout31 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree32 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout32 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree33 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout33 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree34 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout34 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree35 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout35 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree36 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout36 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree37 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout37 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree38 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout38 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree39 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout39 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree40 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout40 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree41 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout41 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree42 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout42 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree43 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout43 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree44 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout44 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree45 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout45 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree46 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout46 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree47 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d0 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout47 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree48 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout48 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree49 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout49 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree50 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout50 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree51 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout51 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree52 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout52 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree53 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout53 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree54 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout54 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree55 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout55 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree56 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout56 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree57 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout57 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree58 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout58 ), .vdd(vdd), .vss(vss));
|
||||
tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree59 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .Iin4 (Ifinal_refresh_d4_d1 ), .Iin5 (Ifinal_refresh_d5_d1 ), .out(Iout59 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX0 (.y(Ifinal_refresh_d0_d1 ), .a(Iin_d0_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX1 (.y(Ifinal_refresh_d1_d1 ), .a(Iin_d1_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX2 (.y(Ifinal_refresh_d2_d1 ), .a(Iin_d2_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX3 (.y(Ifinal_refresh_d3_d1 ), .a(Iin_d3_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX4 (.y(Ifinal_refresh_d4_d1 ), .a(Iin_d4_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_tX5 (.y(Ifinal_refresh_d5_d1 ), .a(Iin_d5_d1 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX0 (.y(Ifinal_refresh_d0_d0 ), .a(Iin_d0_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX1 (.y(Ifinal_refresh_d1_d0 ), .a(Iin_d1_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX2 (.y(Ifinal_refresh_d2_d0 ), .a(Iin_d2_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX3 (.y(Ifinal_refresh_d3_d0 ), .a(Iin_d3_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX4 (.y(Ifinal_refresh_d4_d0 ), .a(Iin_d4_d0 ), .vdd(vdd), .vss(vss));
|
||||
BUF_X12 Iin_fX5 (.y(Ifinal_refresh_d5_d0 ), .a(Iin_d5_d0 ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,15 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0delay__chain_32_4(out, in, vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
output out;
|
||||
input in;
|
||||
|
||||
// -- signals ---
|
||||
wire Idly1_a ;
|
||||
wire in;
|
||||
wire out ;
|
||||
|
||||
// --- instances
|
||||
DLY4_X1 Idly0 (.y(Idly1_a ), .a(in), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly1 (.y(out), .a(Idly1_a ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,29 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0delayprog_32_4(out, in, Is0 , Is1 , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
output out;
|
||||
input in;
|
||||
input Is0 ;
|
||||
input Is1 ;
|
||||
|
||||
// -- signals ---
|
||||
wire I_a1 ;
|
||||
wire Idly2_a ;
|
||||
wire out ;
|
||||
wire Is1 ;
|
||||
wire Idly0_y ;
|
||||
wire Idly2_y ;
|
||||
wire in;
|
||||
wire Idly1_a ;
|
||||
wire Is0 ;
|
||||
wire Idly0_a ;
|
||||
|
||||
// --- instances
|
||||
AND2_X1 Iand20 (.y(Idly0_a ), .a(in), .b(Is0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Iand21 (.y(Idly1_a ), .a(I_a1 ), .b(Is1 ), .vdd(vdd), .vss(vss));
|
||||
MUX2_X1 Imu20 (.y(I_a1 ), .a(in), .b(Idly0_y ), .s(Is0 ), .vdd(vdd), .vss(vss));
|
||||
MUX2_X1 Imu21 (.y(out), .a(I_a1 ), .b(Idly2_y ), .s(Is1 ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly0 (.y(Idly0_y ), .a(Idly0_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly1 (.y(Idly2_a ), .a(Idly1_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly2 (.y(Idly2_y ), .a(Idly2_a ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
@ -1,2 +0,0 @@
|
||||
-- Master.tag File, Rev:1.0
|
||||
verilog.v
|
||||
@ -1,65 +0,0 @@
|
||||
module tmpl_0_0dataflow__neuro_0_0delayprog_34_4(out, in, Is0 , Is1 , Is2 , Is3 , vdd, vss);
|
||||
input vdd;
|
||||
input vss;
|
||||
output out;
|
||||
input in;
|
||||
input Is0 ;
|
||||
input Is1 ;
|
||||
input Is2 ;
|
||||
input Is3 ;
|
||||
|
||||
// -- signals ---
|
||||
wire Idly3_a ;
|
||||
wire Idly2_y ;
|
||||
wire Idly5_a ;
|
||||
wire Is3 ;
|
||||
wire Idly14_y ;
|
||||
wire Idly13_a ;
|
||||
wire I_a2 ;
|
||||
wire in;
|
||||
wire Idly4_a ;
|
||||
wire I_a3 ;
|
||||
wire Idly10_a ;
|
||||
wire Idly0_y ;
|
||||
wire Idly1_a ;
|
||||
wire Idly11_a ;
|
||||
wire Idly8_a ;
|
||||
wire out ;
|
||||
wire Idly12_a ;
|
||||
wire Idly0_a ;
|
||||
wire Idly7_a ;
|
||||
wire I_a1 ;
|
||||
wire Idly14_a ;
|
||||
wire Idly6_a ;
|
||||
wire Idly2_a ;
|
||||
wire Is2 ;
|
||||
wire Is1 ;
|
||||
wire Idly9_a ;
|
||||
wire Idly6_y ;
|
||||
wire Is0 ;
|
||||
|
||||
// --- instances
|
||||
AND2_X1 Iand20 (.y(Idly0_a ), .a(in), .b(Is0 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Iand21 (.y(Idly1_a ), .a(I_a1 ), .b(Is1 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Iand22 (.y(Idly3_a ), .a(I_a2 ), .b(Is2 ), .vdd(vdd), .vss(vss));
|
||||
AND2_X1 Iand23 (.y(Idly7_a ), .a(I_a3 ), .b(Is3 ), .vdd(vdd), .vss(vss));
|
||||
MUX2_X1 Imu20 (.y(I_a1 ), .a(in), .b(Idly0_y ), .s(Is0 ), .vdd(vdd), .vss(vss));
|
||||
MUX2_X1 Imu21 (.y(I_a2 ), .a(I_a1 ), .b(Idly2_y ), .s(Is1 ), .vdd(vdd), .vss(vss));
|
||||
MUX2_X1 Imu22 (.y(I_a3 ), .a(I_a2 ), .b(Idly6_y ), .s(Is2 ), .vdd(vdd), .vss(vss));
|
||||
MUX2_X1 Imu23 (.y(out), .a(I_a3 ), .b(Idly14_y ), .s(Is3 ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly0 (.y(Idly0_y ), .a(Idly0_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly1 (.y(Idly2_a ), .a(Idly1_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly2 (.y(Idly2_y ), .a(Idly2_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly3 (.y(Idly4_a ), .a(Idly3_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly4 (.y(Idly5_a ), .a(Idly4_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly5 (.y(Idly6_a ), .a(Idly5_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly6 (.y(Idly6_y ), .a(Idly6_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly7 (.y(Idly8_a ), .a(Idly7_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly8 (.y(Idly9_a ), .a(Idly8_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly9 (.y(Idly10_a ), .a(Idly9_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly10 (.y(Idly11_a ), .a(Idly10_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly11 (.y(Idly12_a ), .a(Idly11_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly12 (.y(Idly13_a ), .a(Idly12_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly13 (.y(Idly14_a ), .a(Idly13_a ), .vdd(vdd), .vss(vss));
|
||||
DLY4_X1 Idly14 (.y(Idly14_y ), .a(Idly14_a ), .vdd(vdd), .vss(vss));
|
||||
endmodule
|
||||
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Reference in New Issue
Block a user