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Author SHA1 Message Date
Michele 04d12338b7 continued register_rw 2022-03-15 08:16:59 +01:00
Michele b8a74e1bb7 Auto stash before merge of "dev" and "origin/dev" 2022-03-14 20:43:07 +01:00
3 changed files with 79 additions and 12 deletions
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26
dataflow_neuro/registers.act
View File

@ -55,9 +55,7 @@ defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supp
bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
pint nw = 1<<lognw;
//Validation of the input
Mx1of2<1+lognw+wl> _in_temp;
(i:1+lognw+wl:_in_temp.d[i] = in.d.d[i];)
vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
// Generation of the fake clock pulse (inverted because the ff clocks are low_active)
delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
@ -175,13 +173,16 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
)
AND2_X1 ack_read_and(.a = in.d.d[lognw+wl].t,.b = output_buf.in.a,.y = _in_a_read,.vdd = supply.vdd, .vss = supply.vss);
//Reset Buffers
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
bool _reset_BX, _reset_BXX[nw],_reset_mem_BX,_reset_mem_BXX[nw*wl];
BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
sigbuf<nw*wl> reset_mem_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
sigbuf<nw> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply=supply);
//Creating the encoder
andtree<lognw> atree[nw];
AND2_X1 and_encoder[nw];
OR2_X1 or_encoder[nw];
INV_X1 inv_encoder[nw];
// Creating the different flip flop arrays
bool _out_encoder[nw];
DFFQ_R_X1 ff[nw*wl];
@ -201,11 +202,14 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
)
// WRITE: Activating the fake clock for the right word
atree[word_idx].out = _out_encoder[word_idx];
and_encoder[word_idx].a = _out_encoder[word_idx];
and_encoder[word_idx].b = _clock[word_idx];
and_encoder[word_idx].y = _clock_word_temp[word_idx];
and_encoder[word_idx].vdd = supply.vdd;
and_encoder[word_idx].vss = supply.vss;
inv_encoder[word_idx].a = _out_encoder[word_idx];
inv_encoder[word_idx].y = or_encoder[word_idx].a;
inv_encoder[word_idx].vdd = supply.vdd;
inv_encoder[word_idx].vss = supply.vss;
or_encoder[word_idx].b = _clock[word_idx];
or_encoder[word_idx].y = _clock_word_temp[word_idx];
or_encoder[word_idx].vdd = supply.vdd;
or_encoder[word_idx].vss = supply.vss;
clock_buffer[word_idx].in = _clock_word_temp[word_idx];
clock_buffer[word_idx].supply = supply;
// READ: Selecting the right word to read if read is high

48
test/unit_tests/register_wrw/run/prsim.out
View File

@ -369,6 +369,54 @@ WRONG ASSERT: "t.out.d.d[3].f" has value X and not 0.
WRONG ASSERT: "t.out.d.d[3].t" has value X and not 0.
[1] reset completed
----------------------------------------------------------
408819 t.dly_cfg[0] : 1
408819 t.dly_cfg[1] : 1
408849 t.registers.ack_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1]
408878 t.registers.clk_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1]
410286 t.registers.clk_dly.mu2[1]._s : 0 [by t.dly_cfg[1]:=1]
437146 t.registers.ack_dly.mu2[0]._s : 0 [by t.dly_cfg[0]:=1]
468382 t.registers.clk_dly.mu2[0]._y : 1 [by t.registers.clk_dly.mu2[0]._s:=0]
487766 t.registers.clk_dly._a[1] : 0 [by t.registers.clk_dly.mu2[0]._y:=1]
488451 t.registers.clk_dly.and2[1]._y : 1 [by t.registers.clk_dly._a[1]:=0]
505166 t.registers.clk_dly.dly[1].a : 0 [by t.registers.clk_dly.and2[1]._y:=1]
505293 t.registers.clk_dly.dly[1]._y : 1 [by t.registers.clk_dly.dly[1].a:=0]
505462 t.registers.clk_dly.dly[1].__y : 0 [by t.registers.clk_dly.dly[1]._y:=1]
505505 t.registers.clk_dly.dly[1].___y : 1 [by t.registers.clk_dly.dly[1].__y:=0]
505517 t.registers.clk_dly.dly[1].y : 0 [by t.registers.clk_dly.dly[1].___y:=1]
506796 t.registers.clk_dly.dly[2]._y : 1 [by t.registers.clk_dly.dly[1].y:=0]
507029 t.registers.clk_dly.dly[2].__y : 0 [by t.registers.clk_dly.dly[2]._y:=1]
507032 t.registers.clk_dly.dly[2].___y : 1 [by t.registers.clk_dly.dly[2].__y:=0]
507070 t.registers.clk_dly.dly[2].y : 0 [by t.registers.clk_dly.dly[2].___y:=1]
507071 t.registers.clk_dly.mu2[1]._y : 1 [by t.registers.clk_dly.dly[2].y:=0]
519823 t.registers._clock_temp : 0 [by t.registers.clk_dly.mu2[1]._y:=1]
519915 t.registers._clock_temp_inv : 1 [by t.registers._clock_temp:=0]
522642 t.registers.clk_X.buf1._y : 0 [by t.registers._clock_temp_inv:=1]
522644 t.registers._clock : 1 [by t.registers.clk_X.buf1._y:=0]
522645 t.registers.ack_dly.and2[0]._y : 0 [by t.registers._clock:=1]
524146 t.registers.ack_dly.dly[0].a : 1 [by t.registers.ack_dly.and2[0]._y:=0]
524148 t.registers.ack_dly.dly[0]._y : 0 [by t.registers.ack_dly.dly[0].a:=1]
524166 t.registers.ack_dly.dly[0].__y : 1 [by t.registers.ack_dly.dly[0]._y:=0]
524285 t.registers.ack_dly.dly[0].___y : 0 [by t.registers.ack_dly.dly[0].__y:=1]
530005 t.registers.ack_dly.dly[0].y : 1 [by t.registers.ack_dly.dly[0].___y:=0]
530013 t.registers.ack_dly.mu2[0]._y : 0 [by t.registers.ack_dly.dly[0].y:=1]
530067 t.registers.ack_dly._a[1] : 1 [by t.registers.ack_dly.mu2[0]._y:=0]
580605 t.registers.ack_dly.and2[1]._y : 0 [by t.registers.ack_dly._a[1]:=1]
580610 t.registers.ack_dly.dly[1].a : 1 [by t.registers.ack_dly.and2[1]._y:=0]
581677 t.registers.ack_dly.dly[1]._y : 0 [by t.registers.ack_dly.dly[1].a:=1]
581678 t.registers.ack_dly.dly[1].__y : 1 [by t.registers.ack_dly.dly[1]._y:=0]
581816 t.registers.ack_dly.dly[1].___y : 0 [by t.registers.ack_dly.dly[1].__y:=1]
581817 t.registers.ack_dly.dly[1].y : 1 [by t.registers.ack_dly.dly[1].___y:=0]
581881 t.registers.ack_dly.dly[2]._y : 0 [by t.registers.ack_dly.dly[1].y:=1]
582004 t.registers.ack_dly.dly[2].__y : 1 [by t.registers.ack_dly.dly[2]._y:=0]
582006 t.registers.ack_dly.dly[2].___y : 0 [by t.registers.ack_dly.dly[2].__y:=1]
582043 t.registers.ack_dly.dly[2].y : 1 [by t.registers.ack_dly.dly[2].___y:=0]
582186 t.registers.ack_dly.mu2[1]._y : 0 [by t.registers.ack_dly.dly[2].y:=1]
582237 t.registers._in_write.a : 1 [by t.registers.ack_dly.mu2[1]._y:=0]
582679 t.registers.read_write_demux._out2_a_B : 0 [by t.registers._in_write.a:=1]
582680 t.registers.read_write_demux.out2_a_B_buf_f.buf1._y : 1 [by t.registers.read_write_demux._out2_a_B:=0]
582689 t.registers.read_write_demux._out2_a_BX_t[0] : 0 [by t.registers.read_write_demux.out2_a_B_buf_f.buf1._y:=1]
582690 t.registers.read_write_demux.out2_a_B_buf_t.buf1._y : 1 [by t.registers.read_write_demux._out2_a_B:=0]
582715 t.registers.read_write_demux._out2_a_BX_f[0] : 0 [by t.registers.read_write_demux.out2_a_B_buf_t.buf1._y:=1]
[2] delay line set
----------------------------------------------------------
383458 t.registers.ff[0].d : 1

17
test/unit_tests/register_wrw/test.prsim
View File

@ -3,6 +3,7 @@ system "echo '[0] start test'"
system "echo '----------------------------------------------------------'"
set-qdi-channel-neutral "t.in" 5
set-qdi-channel-neutral "t.out" 4
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
@ -11,9 +12,15 @@ set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
set t.out.a 0
set t.out.v 0
cycle
#set t.registers._in_write.a 0
set Reset 0
set t.dly_cfg[0] 1
set t.dly_cfg[1] 1
cycle
assert-qdi-channel-neutral "t.in" 5
assert-qdi-channel-neutral "t.out" 4
# There shouldnt be any status X
status X
#mode run
cycle
@ -45,21 +52,29 @@ assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
assert t.registers.ff[2].q 0
assert t.registers.ff[3].q 0
assert t.registers.ff[4].q 0
assert t.registers.ff[5].q 0
assert t.registers.ff[6].q 0
assert t.registers.ff[7].q 0
system "echo '[3] first writing done'"
system "echo '----------------------------------------------------------'"
set-qdi-channel-valid "t.in" 5 16
# 16 -> 10000 -> reading mode, address 00, word 00 (word doesn't needed here)
# 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here)
cycle
assert t.registers._clock_temp_inv 1
assert-qdi-channel-valid "t.out" 4 3
set t.out.v 1
cycle
set t.out.a 1
assert t.registers._clock_temp_inv 1
cycle
assert t.in.a 1
set-qdi-channel-neutral "t.in" 5
assert t.registers._clock_temp_inv 1
cycle
assert t.registers._clock_temp_inv 1
assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
assert t.registers.ff[2].q 0