dataflow_neuro/registers.act

@@ -414,10 +414,14 @@ defproc registerA_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
 
 // BIG TODO
 // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
+
+// Input valid tree
+// Note that I may need to check the validity of other downstream stuff,
+// to be ultra careful about delays.
+// e.g. TODO add validity checking on the selector signals.
 vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
     .supply = supply);
 
-
 // Address decoder
 decoder_dualrail<NcA, M> decoder(.supply = supply);
 (i:NcA:
@@ -433,10 +437,10 @@ A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
 
 // Write bit selector
 bool _w = in.d.d[NcA+NcW].t;
-A_2C_B_X1 write_selectors[M];
+AND2_X1 write_selectors[M];
 (i:M:
-    write_selectors[i].c1 = _w;
+    write_selectors[i].a = _w;
-    write_selectors[i].c2 = decoder.out[i];
+    write_selectors[i].b = decoder.out[i];
     write_selectors[i].vdd = supply.vdd;
     write_selectors[i].vss = supply.vss;
 )
@@ -468,153 +472,6 @@ TIELO_X1 tielow_writebit_f[M];
 
 }
 
-/** 
- * Array of registers made out of A-cells
- * params:
- * NcW: number of bits in Words to be stored in buffers
- * NcA: number of bits in Address
- * M: number of registers.  M = 2^Nc_addr would be a natural choice.
- * Input packets should be 
- * [-addr-][-word-][r/w]
- */
-export template<pint NcA, NcW, M>
-defproc registerA_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
-    bool? reset_B; power supply) {
-
-// BIG TODO
-// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
-
-// Input valid tree
-vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
-    .supply = supply);
-
-
-// Address decoder
-decoder_dualrail<NcA, M> decoder(.supply = supply);
-(i:NcA:
-    decoder.in.d[i] = in.d.d[i];
-)
-
-// OrTree over acks from all registers
-ortree<M> ack_ortree(.supply = supply);
-
-bool _write_ack;
-// C element handling in ack
-A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
-    .vss = supply.vss, .vdd = supply.vdd); 
-
-// Bit to join the acks either from read or write
-bool _read_ack;
-_read_ack = out.a;
-OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack, .y = in.a,
-    .vdd = supply.vdd, .vss = supply.vss);
-
-// Write bit selector
-bool _w = in.d.d[NcA+NcW].t;
-A_2C_B_X1 write_selectors[M];
-(i:M:
-    write_selectors[i].c1 = _w;
-    write_selectors[i].c2 = decoder.out[i];
-    write_selectors[i].vdd = supply.vdd;
-    write_selectors[i].vss = supply.vss;
-)
-
-
-// Registers
-registerA<NcW> registers[M];
-TIELO_X1 tielow_writebit_f[M];
-(i:M:
-    // Connect each register to word inputs.
-    (j:NcW:
-        registers[i].in.d.d[j] = in.d.d[j + NcA];
-    )
-
-    // Connect the (selected) write bit
-    registers[i].in.d.d[NcW].t = write_selectors[i].y;
-    tielow_writebit_f[i].vdd = supply.vdd;
-    tielow_writebit_f[i].vss = supply.vss;
-    registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
-
-    // Connect to ack ortree
-    registers[i].in.a = ack_ortree.in[i];
-
-    // Connect outputs
-    data[i] = registers[i].out;
-
-    registers[i].supply = supply;
-    registers[i].reset_B = reset_B;
-)
-
-// Read bit selector
-bool _r = in.d.d[NcA+NcW].f;
-A_2C_B_X1 read_selectors[M];
-(i:M:
-    read_selectors[i].c1 = _r;
-    read_selectors[i].c2 = decoder.out[i];
-    read_selectors[i].vdd = supply.vdd;
-    read_selectors[i].vss = supply.vss;
-)
-
-// OrTrees for each output word bit on read
-ortree<M> out_ortrees_t[NcW];
-ortree<M> out_ortrees_f[NcW];
-(i:NcW:
-    out_ortrees_t[i].out = out.d.d[i+NcA].t;
-    out_ortrees_f[i].out = out.d.d[i+NcA].f;
-
-    out_ortrees_t[i].supply = supply;
-    out_ortrees_f[i].supply = supply;
-)
-
-// ANDs over each reg's data
-// and whether it is selected for read.
-AND2_X1 and_reads_t[NcW * M];
-AND2_X1 and_reads_f[NcW * M];
-pint index;
-(i:NcW:
-    (j:M:
-        index = i + j*NcW;
-
-        and_reads_t[index].a = data[j].d[i].t;
-        and_reads_t[index].b = read_selectors[j].y;
-        and_reads_f[index].a = data[j].d[i].f;
-        and_reads_f[index].b = read_selectors[j].y;
-
-        and_reads_t[index].y = out_ortrees_t[i].in[j];
-        and_reads_f[index].y = out_ortrees_f[i].in[j];
-
-        and_reads_t[index].vss = supply.vss;
-        and_reads_t[index].vdd = supply.vdd;
-        and_reads_f[index].vss = supply.vss;
-        and_reads_f[index].vdd = supply.vdd;
-    )
-
-)
-
-// C elements passing address to out on read.
-A_2C_B_X1 addr_read_t[NcA];
-A_2C_B_X1 addr_read_f[NcA];
-(i:NcA:
-    addr_read_t[i].c1 = in.d.d[i].t;
-    addr_read_f[i].c1 = in.d.d[i].f;
-
-    addr_read_t[i].c2 = _r;
-    addr_read_f[i].c2 = _r;
-
-    addr_read_t[i].y = out.d.d[i].t;
-    addr_read_f[i].y = out.d.d[i].f;
-
-    addr_read_t[i].vdd = supply.vdd;
-    addr_read_t[i].vss = supply.vss;
-    addr_read_f[i].vdd = supply.vdd;
-    addr_read_f[i].vss = supply.vss;
-
-
-)
-
-
-
-}
 
 
 

test/unit_tests/registerA_wr_array/test.act

@@ -1,55 +0,0 @@
-/*************************************************************************
- *
- *  This file is part of ACT dataflow neuro library.
- * It's the testing facility for cell_lib_std.act
- *
- *  Copyright (c) 2022 University of Groningen - Ole Richter  
- *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
- *  Copyright (c) 2022 University of Groningen - Michele Mastella
- *  Copyright (c) 2022 University of Groningen - Madison Cotteret
- *
- *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
- *
- *  You may redistribute and modify this documentation and make products
- *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
- *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
- *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
- *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
- *  for applicable conditions.
- *
- *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
- *
- *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
- *  these sources, You must maintain the Source Location visible in its
- *  documentation.
- *
- **************************************************************************
- */
-
-import "../../dataflow_neuro/registers.act";
-
-import globals;
-import std::data;
-
-open std::data;
-
-open tmpl::dataflow_neuro;
-
-defproc registerA_wr_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]; avMx1of2<8> out){
-    bool _reset_B; 
-    prs {
-        Reset => _reset_B-
-    }
-    power supply;
-    supply.vdd = Vdd;
-    supply.vss = GND;
-
-    // Make a register array with 3 bit address (-> 8 registers), 
-    // each register holding 5 bits.
-    registerA_wr_array<3,5,8> b(.in = in, .data = data, .out = out,
-        .reset_B = _reset_B, .supply = supply);
-}
-
-
-// fifo_decoder_neurons_encoder_fifo e;
-registerA_wr_array_3x5x8 b;

test/unit_tests/registerA_wr_array/test.prsim

@@ -1,199 +0,0 @@
-watchall
-
-set-qdi-channel-neutral "b.in" 9
-set b.out.a 0
-set b.out.v 0
-cycle
-
-
-mode run
-system "echo '[] Set reset 0'"
-status X
-set Reset 0
-cycle
-assert b.in.a 0
-assert b.in.v 0
-
-system "echo '[] Sending packet write 0s to reg0'"
-set-qdi-channel-valid "b.in" 9 256
-cycle
-assert b.in.a 1
-assert b.in.v 1
-assert-var-int "b.data[0]" 5 0
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert b.in.a 0
-assert b.in.v 0
-assert-var-int "b.data[0]" 5 0
-
-system "echo '[] Sending packet write 0s to reg0'"
-set-qdi-channel-valid "b.in" 9 256
-cycle
-assert b.in.a 1
-assert b.in.v 1
-assert-var-int "b.data[0]" 5 0
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert b.in.a 0
-assert b.in.v 0
-assert-var-int "b.data[0]" 5 0
-
-system "echo '[] Sending packet write 01100=12 to reg0'"
-set-qdi-channel-valid "b.in" 9 352
-cycle
-assert b.in.a 1
-assert b.in.v 1
-assert-var-int "b.data[0]" 5 12
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert b.in.a 0
-assert b.in.v 0
-assert-var-int "b.data[0]" 5 12
-
-
-system "echo '[] Sending packet write 0s to reg1'"
-set-qdi-channel-valid "b.in" 9 257
-cycle
-assert b.in.a 1
-assert b.in.v 1
-assert-var-int "b.data[1]" 5 0
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert b.in.a 0
-assert b.in.v 0
-
-system "echo '[] Sending packet write 0s to reg2'"
-set-qdi-channel-valid "b.in" 9 258
-cycle
-assert b.in.a 1
-assert b.in.v 1
-assert-var-int "b.data[2]" 5 0
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert b.in.a 0
-assert b.in.v 0
-assert-var-int "b.data[2]" 5 0
-
-system "echo '[] Sending packet write 0s to reg3'"
-set-qdi-channel-valid "b.in" 9 259
-cycle
-assert b.in.a 1
-assert b.in.v 1
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert b.in.a 0
-assert b.in.v 0
-
-system "echo '[] Sending packet write 0s to reg4'"
-set-qdi-channel-valid "b.in" 9 260
-cycle
-assert b.in.a 1
-assert b.in.v 1
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert b.in.a 0
-assert b.in.v 0
-
-system "echo '[] Sending packet write 0s to reg5'"
-set-qdi-channel-valid "b.in" 9 261
-cycle
-assert b.in.a 1
-assert b.in.v 1
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert b.in.a 0
-assert b.in.v 0
-
-system "echo '[] Sending packet write 0s to reg6'"
-set-qdi-channel-valid "b.in" 9 262
-cycle
-assert b.in.a 1
-assert b.in.v 1
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert b.in.a 0
-assert b.in.v 0
-
-system "echo '[] Sending packet write 0s to reg7'"
-set-qdi-channel-valid "b.in" 9 263
-cycle
-assert b.in.a 1
-assert b.in.v 1
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert b.in.a 0
-assert b.in.v 0
-
-assert-var-int "b.data[2]" 5 0
-assert-var-int "b.data[3]" 5 0
-assert-var-int "b.data[4]" 5 0
-assert-var-int "b.data[5]" 5 0
-assert-var-int "b.data[6]" 5 0
-assert-var-int "b.data[7]" 5 0
-
-
-system "echo '[] Reading register 0'"
-set-qdi-channel-valid "b.in" 9 0
-cycle
-assert-qdi-channel-valid "b.out" 8 96
-assert b.in.v 1
-assert b.in.a 0
-
-set b.out.a 1
-set b.out.v 1
-cycle
-assert b.in.a 1
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert-qdi-channel-neutral "b.out" 8
-set b.out.a 0
-set b.out.v 0
-cycle
-assert b.in.a 0
-assert b.in.v 0
-
-
-
-system "echo '[] Reading register 1'"
-set-qdi-channel-valid "b.in" 9 1
-cycle
-assert-qdi-channel-valid "b.out" 8 1
-assert b.in.v 1
-assert b.in.a 0
-
-set b.out.a 1
-set b.out.v 1
-cycle
-assert b.in.a 1
-
-system "echo '[] Removing input'"
-set-qdi-channel-neutral "b.in" 9
-cycle
-assert-qdi-channel-neutral "b.out" 8
-set b.out.a 0
-set b.out.v 0
-cycle
-assert b.in.a 0
-assert b.in.v 0