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Author SHA1 Message Date
Ole Richter
8cf459db1a added buffer (not tested), added license 
moved cell libs into repo
 2022-02-21 00:14:02 +01:00
291 changed files with 405 additions and 4883408 deletions
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4
Makefile
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@@ -20,8 +20,8 @@
# -----------------------------------------------------------------------------
TARGETACT=LICENSE
# tmpl because its a template based appoach no syntesis so it would be wrong in syn
TARGETACTSUBDIR=tmpl/dataflow_neuro
# template because its a template based appoach no syntesis so it would be wrong in syn
TARGETACTSUBDIR=template/dataflow
SUBDIRS=dataflow_neuro

16
README.md
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@@ -1,18 +1,10 @@
# ARCHIVED REPOSITORY
# The classical dataflow template library for mixed signal neuromoric processors
further development and new versions => https://github.com/async-ic/actlib-neurosynaptic-perifery
# A dataflow template library for mixed signal neuromoric processors
the library will be installed in `$ACT_HOME/act/template/dataflow`. This path is part of the default search path for any ACT tool.
the library will be installed in `$ACT_HOME/act/tmpl/dataflow_neuro`.
This path is part of the default search path for any ACT tool.
this library depends on stdlib (https://github.com/asyncvlsi/stdlib)
this library depends on stdlib
## Installation
Set `$ACT_HOME` to the root of your ACT installation, and then run `make install`.
## Unit tests
After installation, you can run `make runtest` to execute the unit tests
Set `$ACT_HOME` to the root of your ACT installation, and then run `make install`

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dataflow_neuro/.DS_Store vendored
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4
dataflow_neuro/Makefile
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@@ -19,10 +19,10 @@
#
# -----------------------------------------------------------------------------
TARGETACT=__all__.act cell_lib_std.act cell_lib_async.act primitives.act
TARGETACT=__all__.act stdcells.act acells.act primitives.act
SUBDIRS=
# template because its a template based appoach no syntesis so it would be wrong in syn
TARGETACTSUBDIR=tmpl/dataflow_neuro
TARGETACTSUBDIR=template/dataflow
include $(ACT_HOME)/scripts/Makefile.std

6
dataflow_neuro/__all__.act
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@@ -22,6 +22,6 @@
**************************************************************************
*/
import tmpl::dataflow_neuro::cell_lib_std;
import tmpl::dataflow_neuro::cell_lib_async;
import tmpl::dataflow_neuro::primitives;
import template::dataflow_neuro::cell_lib_std;
import template::dataflow_neuro::cell_lib_async;
import template::dataflow_neuro::primitives;

341
dataflow_neuro/cell_lib_async.act
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@@ -24,33 +24,10 @@
**************************************************************************
*/
namespace tmpl {
namespace dataflow_neuro{
export defcell KEEP (bool y; bool vdd, vss) {
bool _y;
prs{
y => _y-
// [weak=1] _y -> y-
// [weak=1] ~_y -> y+
namespace template {
namespace dataflow_neuro {
}
}
export defcell A_1C2N_RB_X1 (bool! y; bool? c1,n1,n2,pr_B, sr_B; bool vdd, vss) {
bool _y;
prs{
(~c1)|~pr_B -> _y+
c1 & n1 & n2 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
export defcell A_1C1P2N_RB_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B, vdd, vss) {
bool _y;
prs{
(~p1 & ~c1)|~pr_B -> _y+
@@ -65,23 +42,7 @@ namespace tmpl {
}
}
export defcell A_2C1P1N_RB_X1 (bool! y; bool? c1,c2,p1,n1,pr_B,sr_B; bool vdd, vss) {
bool _y;
prs{
(~p1 & ~c1 & ~c2)|~pr_B -> _y+
c1 & c2 & n1 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}
}
}
export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B; bool vdd, vss) {
export defcell A_1C1P2N_R_X1 (bool! y; bool? c1,p1,n1,n2,pr_B, sr_B, vdd, vss) {
prs{
(~p1 & ~c1)|~pr_B -> y-
c1 & n1 & n2 & sr_B -> y+
@@ -94,7 +55,7 @@ namespace tmpl {
}
export defcell A_1C1P_1N_X1 (bool! y; bool? c1, p1, n1; bool vdd, vss)
export defcell A_1C1P_1N_X1 (bool! y; bool? c1, p1, n1, vdd, vss)
{
prs{
~p1 & ~c1 -> y+
@@ -105,7 +66,7 @@ namespace tmpl {
y {-1}}
}
export defcell A_1C1P_B (bool! y; bool? c1, p1; bool vdd, vss)
export defcell A_1C1P_B (bool! y; bool? c1, p1, vdd, vss)
{
bool _y;
prs{
@@ -119,7 +80,7 @@ namespace tmpl {
}
export defcell A_1C1P_X1 (bool! y; bool? c1, p1; bool vdd, vss)
export defcell A_1C1P (bool! y; bool? c1, p1, vdd, vss)
{
prs{
~p1 & ~c1 -> y+
@@ -130,82 +91,7 @@ namespace tmpl {
y {-1}}
}
export defcell A_1C1N_X1 (bool! y; bool? c1, n1; bool vdd, vss)
{
prs{
~c1 -> y+
c1&n1-> y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-1}}
}
// export defcell A_1C1N_RB_X4 (bool! y; bool? c1, n1, pr_B, sr_B; bool vdd, vss)
// {
// bool _y;
// prs{
// ~c1 | ~pr_B-> _y+
// c1&n1&sr_B -> _y-
// _y => y-
// }
// sizing {leak_adjust <- 1;
// p_n_mode <- 1;
// y {-4}; _y{-1}}
// }
// export defcell A_1C1N_SB_X4 (bool! y; bool? c1, n1, pr, sr; bool vdd, vss)
// {
// bool _y;
// prs{
// ~c1 & ~sr-> _y+
// c1&n1 | pr -> _y-
// _y => y-
// }
// sizing {leak_adjust <- 1;
// p_n_mode <- 1;
// y {-4}; _y{-1}}
// }
export defcell A_1C2N_R_X1 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
{
prs{
~c1 | ~pr_B-> y+
c1&n1&n2&sr_B -> y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-4}}
}
export defcell A_1C2N_RB_X4 (bool! y; bool? c1, n1, n2, pr_B, sr_B; bool vdd, vss)
{
bool _y;
prs{
~c1 | ~pr_B-> _y+
c1&n1&n2&sr_B -> _y-
_y => y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-4}; _y{-1}}
}
export defcell A_1C2N_SB_X4 (bool! y; bool? c1, n1, n2, pr, sr; bool vdd, vss)
{
bool _y;
prs{
~c1 & ~sr-> _y+
c1&n1&n2 | pr -> _y-
_y => y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-4}; _y{-1}}
}
export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1; bool vdd, vss)
export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1, vdd, vss)
{
prs{
~p1 & ~p2 & ~c1 -> y+
@@ -216,7 +102,7 @@ namespace tmpl {
y {-1}}
}
export defcell A_1C2P_B_X1 (bool! y; bool? c1, p1, p2; bool vdd, vss)
export defcell A_1C2P_B_X1 (bool! y; bool? c1, p1, p2, vdd, vss)
{
bool _y;
prs{
@@ -228,9 +114,9 @@ namespace tmpl {
p_n_mode <- 1;
y {-1}; _y{-1} }
}
}
export defcell A_1C2P_X1 (bool! y; bool? c1, p1, p2; bool vdd, vss)
export defcell A_1C2P (bool! y; bool? c1, p1, p2, vdd, vss)
{
prs{
~p1 & ~p2 & ~c1 -> y+
@@ -241,7 +127,7 @@ namespace tmpl {
y {-1}}
}
export defcell A_1C3P2P2N_R_X1 (bool! y; bool? c1, p1, p2, p3, p4, p5, n1, n2, pr_B, sr_B; bool vdd, vss)
export defcell A_1C3P2P2N_R_X1 (bool! y; bool? c1, p1, p2, p3, p4, p5 n1, n2, pr_B, sr_B, vdd, vss)
{
prs{
(~p1 & ~p2 & ~p3 & ~c1)|(~p4&~p5&~c1)|~pr_B -> y+
@@ -252,12 +138,12 @@ namespace tmpl {
y {-1}}
}
export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, na1, na2, nb1, nb2, pr_B, sr_B; bool vdd, vss)
export defcell A_2C2N2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & ((na1 & na2) | (nb1 & nb2)) & sr_B -> _y-
c1 & c2 & ((n1 & n2) | (n3 & n4)) & sr_B -> _y-
_y => y-
}
sizing {
@@ -266,7 +152,7 @@ namespace tmpl {
y {-1}; _y{-1}}
}
export defcell A_2C2N2N_RB_X2 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool vdd, vss)
export defcell A_2C2N2N_RB_X2 (bool ! y; bool? c1, c2, n1, n2, n3, n4, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
@@ -308,12 +194,12 @@ namespace tmpl {
y {-1}}
}
export defcell A_2C2N_RB_X1 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss)
export defcell A_2C2N_R_B_X1 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & n1 & n2 & sr_B -> _y-
(~c1 & ~c2) | ~rp_B -> _y+
c1 & c2 & n1 & n2 & rs_B -> _y-
_y => y-
}
sizing {
@@ -322,12 +208,12 @@ namespace tmpl {
y {-1}; _y{-1}}
}
export defcell A_2C2N_RB_X2 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss)
export defcell A_2C2N_R_B_X2 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & n1 & n2 & sr_B -> _y-
(~c1 & ~c2) | ~rp_B -> _y+
c1 & c2 & n1 & n2 & rs_B -> _y-
_y => y-
}
sizing {
@@ -336,12 +222,12 @@ namespace tmpl {
y {-2}; _y{-1}}
}
export defcell A_2C2N_RB_X4 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss)
export defcell A_2C2N_R_B_X4 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & n1 & n2 & sr_B -> _y-
(~c1 & ~c2) | ~rp_B -> _y+
c1 & c2 & n1 & n2 & rs_B -> _y-
_y => y-
}
sizing {
@@ -351,11 +237,11 @@ namespace tmpl {
}
export defcell A_2C2N_R_X1 (bool ! y; bool? c1, c2, n1, n2, pr_B, sr_B; bool? vdd, vss)
export defcell A_2C2N_R_X1 (bool ! y; bool? c1, c2, n1, n2, rp_B, rs_B; bool? vdd, vss)
{
prs{
(~c1 & ~c2) | ~pr_B -> y+
c1 & c2 & n1 & n2 & sr_B -> y-
(~c1 & ~c2) | ~rp_B -> y+
c1 & c2 & n1 & n2 & rs_B -> y-
}
sizing {
leak_adjust <- 1;
@@ -391,20 +277,6 @@ namespace tmpl {
y {-1}; _y{-1}}
}
export defcell A_2C_RB_X4 (bool ! y; bool? c1, c2, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-4}; _y{-1}}
}
export defcell A_2C_R_X1 (bool ! y; bool? c1, c2, pr_B, sr_B; bool? vdd, vss)
{
prs{
@@ -416,45 +288,7 @@ namespace tmpl {
p_n_mode <- 1;
y {-1}}
}
export defcell A_2C1N_RB_X1(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & n1 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}}
}
export defcell A_2C1N_R_X1(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
{
prs{
(~c1 & ~c2) | ~pr_B -> y+
c1 & c2 & n1 & sr_B -> y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}}
}
export defcell A_2C1N_RB_X4(bool ! y; bool? c1, c2, n1, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
(~c1 & ~c2) | ~pr_B -> _y+
c1 & c2 & n1 & sr_B -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-4}; _y{-1}}
}
export defcell A_2C_X1 (bool ! y; bool? c1, c2; bool? vdd, vss)
{
prs{
@@ -467,20 +301,6 @@ namespace tmpl {
y {-1}}
}
export defcell A_3C_B_X1 (bool ! y; bool? c1, c2, c3; bool? vdd, vss)
{
bool _y;
prs{
~c1 & ~c2 & ~c3 -> _y+
c1 & c2 & c3 -> _y-
_y => y-
}
sizing {
leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1}}
}
export defcell A_3C_RB_X1 (bool ! y; bool? c1, c2, c3, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
@@ -547,7 +367,7 @@ namespace tmpl {
y {-1}}
}
export defcell A_4C_RB_X1 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
export deffcell A_4C_RB_X1 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
@@ -560,7 +380,7 @@ namespace tmpl {
y {-1}; _y{-1}}
}
export defcell A_4C_RB_X2 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
export deffcell A_4C_RB_X2 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
@@ -573,7 +393,7 @@ namespace tmpl {
y {-2}; _y{-1}}
}
export defcell A_4C_RB_X4 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
export deffcell A_4C_RB_X4 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
{
bool _y;
prs{
@@ -586,7 +406,7 @@ namespace tmpl {
y {-4}; _y{-1}}
}
export defcell A_4C_R_X1 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
export deffcell A_4C_R_X1 (bool! y; bool? c1, c2, c3, c4, pr_B, sr_B; bool? vdd, vss)
{
prs{
(~c1 & ~c2 & ~c3 & ~c4) | ~pr_B -> y+
@@ -610,110 +430,17 @@ namespace tmpl {
y {-1}; _y{-1} }
}
export defcell A_4P1N1N_X1 (bool! y; bool? na1, nb1, p1, p2, p3, p4; bool? vdd, vss)
export defcell A_4P1N1N_X1 (bool! y; bool? n1, n2, p1, p2, p3, p4; bool? vdd, vss)
{
prs{
~p1 & ~p2 & ~p3 & ~p4 -> y+
na1 | nb1 -> y-
n1 | n2 -> y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-1}}
}
//Rajit example
defproc arbiter_Rajit (bool a, b, u, v)
{
bool _u, _v;
prs {
[keeper=0] a & _v -> _u-
[keeper=0] ~a | ~_v -> _u+
[keeper=0] b & _u -> _v-
[keeper=0] ~b | ~_u -> _v+
[keeper=0] _u => u-
[keeper=0] _v => v-
}
spec {
mk_excllo(_u, _v)
}
}
defproc ARBITER (bool? a, b, c, d; bool! y1,y2; bool? vdd, vss)
{
bool _y1, _y2;
prs {
[keeper=0] a & _y2 -> _y1-
[keeper=0] ~a | ~_y2 -> _y1+
[keeper=0] b & _y1 -> _y2-
[keeper=0] ~b | ~_y1 -> _y2+
[keeper=0] _y1 | c => y1-
[keeper=0] _y2 | d => y2-
}
spec {
mk_excllo(_y1, _y2)
}
}
export
defproc A_1N_U_X4(bool? n1; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] n1 -> y-
}
}
export
defproc A_2N_U_X4(bool? n1, n2; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] n1 & n2 -> y-
}
}
export
defproc A_1P_U_X4(bool? p1; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~p1 -> y+
}
}
export
defproc A_2P_U_X4(bool? p1, p2; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~p1 & ~p2 -> y+
}
}
export
defproc A_3P_U_X4(bool? p1, p2, p3; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~p1 & ~p2 & ~p3-> y+
}
}
export
defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss) {
A_1N_U_X4 cell(.n1 = a, .y = y, .vdd = vdd, .vss = vss);
}
export
defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss) {
A_1P_U_X4 cell(.p1 = a, .y = y, .vdd = vdd, .vss = vss);
}
defproc A_2C2P_RB_X1(bool! y;bool? c1,c2,p1,p2,reset_B,vdd,vss){
bool _y;
prs{
(~p1 & ~p2 & ~c1 & ~c2)|~reset_B -> _y+
(c1 & c2 & reset_B) -> _y-
_y => y-
}
sizing {leak_adjust <- 1;
p_n_mode <- 1;
y {-1}; _y{-1} }
}
}}
xp018_cell_lib_async::A_1C1P_B_X1 cell1;

60
dataflow_neuro/cell_lib_async_test.act
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@@ -1,60 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_async.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "cell_lib_async.act";
open tmpl::dataflow_neuro;
A_1C1P2N_RB_X1 cell1;
A_1C1P2N_R_X1 cell2;
A_1C1P_1N_X1 cell3;
A_1C1P_B cell4;
A_1C1P cell5;
A_1C2P1N_X1 cell6;
A_1C2P_B_X1 cell7;
A_1C2P cell8;
A_1C3P2P2N_R_X1 cell9;
A_2C2N2N_RB_X1 cell10;
A_2C2N2N_RB_X2 cell11;
A_2C2N2N_RB_X4 cell12;
A_2C2N2N_R_X1 cell13;
A_2C2N_R_B_X2 cell14;
A_2C2N_R_B_X4 cell15;
A_2C2N_R_X1 cell16;
A_2C_B_X1 cell17;
A_2C_RB_X1 cell18;
A_2C_R_X1 cell19;
A_2C_X1 cell20;
A_3C_RB_X1 cell21;
A_3C_RB_X2 cell22;
A_3C_RB_X4 cell23;
A_3C_R_X1 cell24;
A_3C_X1 cell25;
A_4C_RB_X1 cell26;
A_4C_RB_X2 cell27;
A_4C_RB_X4 cell28;
A_4C_R_X1 cell29;
A_4P1N1N_B_X1 cell30;
A_4P1N1N_X1 cell31;

650
dataflow_neuro/cell_lib_std.act
View File

@@ -24,416 +24,256 @@
**************************************************************************
*/
namespace tmpl {
namespace dataflow_neuro {
namespace dataflow {
export defproc TIELO_X1(bool! y; bool vdd, vss)
{
y = vss;
}
export defproc TIELO_X1(bool! y; bool? vdd, vss)
{
y = vss;
}
export defproc TIEHI_X1(bool! y; bool vdd, vss)
{
y = vdd;
}
export defproc TIEHI_X1(bool! y; bool? vdd, vss)
{
y = vdd;
}
/*-- inverters --*/
/*-- inverters --*/
defproc inv (bool! y; bool? a, vdd, vss)
{
prs {
a => y-
}
}
template<pint nf>
defproc szinv <: inv()
{
[nf = 0 -> sizing { y {-1} }
[] else -> sizing { y {-2*nf,svt,nf} }
]
}
export defcell INV_X1<: szinv<0>() { }
export defcell INV_X2<: szinv<1>() { }
export defcell INV_X4<: szinv<2>() { }
export defcell INV_X8<: szinv<4>() { }
/*-- signal buffers --*/
defproc buf (bool! y; bool? a, vdd, vss)
{
bool _y;
prs {
a => _y-
_y => y-
}
}
export defcell BUF_X1<: buf()
{
sizing { _y {-1}; y {-1} }
}
export defcell BUF_X2<: buf()
{
sizing { _y {-1}; y {-2} }
}
export defcell BUF_X3<: buf()
{
sizing { _y {-1.5}; y {-3} }
}
export defcell BUF_X4<: buf()
{
sizing { _y {-1.5}; y {-4,2} }
}
export defcell BUF_X6<: buf()
{
sizing { _y {-3}; y {-6,2} }
}
export defcell BUF_X8<: buf()
{
sizing { _y {-4,2}; y {-8,4} }
}
export defcell BUF_X12<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
export defcell BUF_X16<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
export defcell BUF_X24<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
export defcell BUF_X32<: buf()
{
sizing { _y {-6,2}; y {-12,4} }
}
/*-- delay cells --*/
// TODO properly
// export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
// {
// bool _y, __y, ___y;
// prs {
// a => _y-
// _y => __y-
// __y => ___y-
// ___y => y-
// }
// }
export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
{
BUF_X1 bufchain[16];
(i:0..14: bufchain[i].y = bufchain[i+1].a;)
bufchain[0].a = a;
bufchain[15].y = y;
}
/*-- simple gates --*/
export defcell NOR2_X1(bool! y; bool? a, b, vdd, vss)
{
prs {
a | b => y-
}
sizing { y {-1} }
}
export defcell NOR3_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a | b | c => y-
}
sizing { y {-1} }
}
export defcell NOR4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
prs {
a | b | c | d => y-
}
sizing { y {-1} }
}
export defcell OR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a | b => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell OR2_X2(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a | b => _y-
_y => y-
}
sizing { _y{-1}; y{-2} }
}
export defcell OR3_X1(bool! y; bool? a, b, c, vdd, vss)
{
bool _y;
prs {
a | b | c => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell OR4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
bool _y;
prs {
a | b | c | d => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell NAND2_X1(bool! y; bool? a, b, vdd, vss)
{
prs {
a & b => y-
}
sizing { y{-1} }
}
export defcell NAND3_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a & b & c => y-
}
sizing { y{-1} }
}
export defcell NAND4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
prs {
a & b & c & d => y-
}
sizing { y{-1} }
}
export defcell AND2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a & b => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell AND2_X2(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a & b => _y-
_y => y-
}
sizing { _y{-1}; y{-2} }
}
export defcell AND3_X1(bool! y; bool? a, b, c, vdd, vss)
{
bool _y;
prs {
a & b & c => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell AND4_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
bool _y;
prs {
a & b & c & d => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell XOR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _a, _b;
prs {
a => _a-
b => _b-
[keeper=0] ~b & ~_a | ~_b & ~a -> y+
_b & _a | b & a -> y-
}
sizing { _a{-1}; _b{-1}; y{-1} }
}
export defcell XNOR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _a, _b;
prs {
a => _a-
b => _b-
[keeper=0] ~b & ~a | ~_b & ~_a -> y+
b & _a | _b & a -> y-
}
sizing { _a{-1}; _b{-1}; y{-1} }
}
export defcell MUX2_X1(bool! y; bool? a, b, s, vdd, vss)
{
// y = !( S ? b : a )
// Actually looks more like
// if s = 0 -> use A
// Adjusted to fit the XFAB Muxes
bool _s;
bool _y;
prs {
s => _s-
[keeper=0] ~a & ~s | ~b & ~_s -> _y+
a & _s | b & s -> _y-
_y => y-
}
sizing { _s{-1}; y{-1}; _y{-1}}
}
export defcell MUX4_X1(bool! y; bool? a, b, c, d, s0, s1, vdd, vss)
{
// y = !( S ? a : b )
bool _s0;
bool _s1;
bool _yab;
bool _ycd;
prs {
s0 => _s0-
s1 => _s1-
[keeper=0] a & _s0 | b & s0 -> _yab-
~a & ~s0 | ~b & ~_s0 -> _yab+
[keeper=0] c & _s0 | d & s0 -> _ycd-
~c & ~s0 | ~d & ~_s0 -> _ycd+
[keeper=0]_yab & _s1 | _ycd & s1 -> y-
~_yab & ~s1 | ~_ycd & ~_s1 -> y+
}
sizing {_s0{-1}; _s1{-1}; y{-1}; _yab{-1}; _ycd{-1}}
}
export defcell OAI21_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
(a | b) & c => y-
}
sizing { y{-1} }
}
export defcell AOI21_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a & b | c => y-
}
sizing { y{-1} }
}
export defcell OAI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
// y = !((a|b) & (c|d))
prs {
(a | b) & (c | d) => y-
}
sizing { y{-1} }
}
export defcell AOI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
prs {
a & b | c & d => y-
}
sizing { y{-1} }
}
/*--- buffered transmission gates ---*/
export defcell TBUF1_X1 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-1}; y{-1} }
}
export defcell TBUF_X2 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-2}; y{-2,2} }
}
export defcell TBUF_X4 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-4}; y{-4,4} }
}
export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q,q_B; bool? vdd,vss)
{
bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;
prs {
// Creating delayed versions of the clock
clk_B => _clk_B-
_clk_B => __clk_B-
(~d & ~_clk_B)|(~reset_B)|(~__clk_B&~_mqi) -> _mqib+
((d & __clk_B)|(_mqi & _clk_B))&reset_B -> _mqib-
_mqib => _mqi-
(~_mqi &~__clk_B)|(~reset_B)|(~_sqi&~_clk_B) -> _sqib+
((_mqi &_clk_B)|(_sqi&__clk_B))&reset_B -> _sqib-
_sqib => _sqi-
_sqib => q-
q => q_B-
}
}
defproc inv (bool! y; bool? a, vdd, vss)
{
prs {
a => y-
}
}
template<pint nf>
defproc szinv <: inv()
{
[nf = 0 -> sizing { y {-1} }
[] else -> sizing { y {-2*nf,svt,nf} }
]
}
export defcell INV_X1<: szinv<0>() { }
export defcell INV_X2<: szinv<1>() { }
export defcell INV_X4<: szinv<2>() { }
export defcell INV_X8<: szinv<4>() { }
/*-- clock delay buffers --*/
template<pint N>
defproc dbuf (bool! y; bool? a, vdd, vss)
{
{N > 0 : "Delay buffer needs at least one stage!"};
bool sig[2*N+1];
sig[0] = a;
sig[2*N] = y;
prs {
(i:2*N: ~sig[i] <80;2> -> sig[i+1]+
sig[i] <40;2> -> sig[i+1]-
)
}
}
export defproc CLKBUF1 <: dbuf<2>() { }
export defproc CLKBUF2 <: dbuf<3>() { }
export defproc CLKBUF3 <: dbuf<4>() { }
/*-- signal buffers --*/
defproc buf (bool! y; bool? a, vdd, vss)
{
bool _y;
prs {
a => _y-
_y => y-
}
}
export defcell BUF_X2<: buf()
{
sizing { _y {-1}; y {-2} }
}
export defcell BUF_X4<: buf()
{
sizing { _y {-1.5}; y {-4,2} }
}
/*-- simple gates --*/
export defcell NOR2_X1(bool! y; bool? a, b, vdd, vss)
{
prs {
a | b => y-
}
sizing { y {-1} }
}
export defcell NOR3_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a | b | c => y-
}
sizing { y {-1} }
}
export defcell OR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a | b => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell OR2_X2(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a | b => _y-
_y => y-
}
sizing { _y{-1}; y{-2} }
}
export defcell NAND2_X1(bool! y; bool? a, b, vdd, vss)
{
prs {
a & b => y-
}
sizing { y{-1} }
}
export defcell NAND3_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a & b & c => y-
}
sizing { y{-1} }
}
export defcell AND2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a & b => _y-
_y => y-
}
sizing { _y{-1}; y{-1} }
}
export defcell AND2_X2(bool! y; bool? a, b, vdd, vss)
{
bool _y;
prs {
a & b => _y-
_y => y-
}
sizing { _y{-1}; y{-2} }
}
export defcell XOR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _a, _b;
prs {
a => _a-
b => _b-
[keeper=0] ~b & ~_a | ~_b & ~a -> y+
_b & _a | b & a -> y-
}
sizing { _a{-1}; _b{-1}; y{-1} }
}
export defcell XNOR2_X1(bool! y; bool? a, b, vdd, vss)
{
bool _a, _b;
prs {
a => _a-
b => _b-
[keeper=0] ~b & ~a | ~_b & ~_a -> y+
b & _a | _b & a -> y-
}
sizing { _a{-1}; _b{-1}; y{-1} }
}
export defcell MUX2_X1(bool! y; bool? a, b, S, vdd, vss)
{
// y = !( S ? a : b )
bool _S;
prs {
S => _S-
[keeper=0] ~a & ~_S | ~b & ~S -> y+
a & S | b & _S -> y-
}
sizing { _S{-1}; y{-1} }
}
export defcell OAI21_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
(a | b) & c => y-
}
sizing { y{-1} }
}
export defcell AOI21_X1(bool! y; bool? a, b, c, vdd, vss)
{
prs {
a & b | c => y-
}
sizing { y{-1} }
}
export defcell OAI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
// y = !((a|b) & (c|d))
prs {
(a | b) & (c | d) => y-
}
sizing { y{-1} }
}
export defcell AOI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
{
prs {
a & b | c & d => y-
}
sizing { y{-1} }
}
/*--- buffered transmission gates ---*/
export defcell TBUF1_X1 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-1}; y{-1} }
}
export defcell TBUF_X2 (bool! y; bool? a, en, vdd, vss)
{
bool _en;
prs {
en => _en-
~a & ~_en -> y+
a & en -> y-
}
sizing { _en{-2}; y{-2,2} }
}

58
dataflow_neuro/cell_lib_std_test.act
View File

@@ -1,58 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Alex Madison
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "cell_lib_std.act";
open std_cell_template::dataflow_neuro;
TIELO_X1 cell1;
TIEHI_X1 cell2;
INV_X1 cell4;
INV_X2 cell5;
INV_X4 cell6;
INV_X8 cell7;
CLKBUF1 cell8;
CLKBUF2 cell9;
CLKBUF3 cell10;
NOR2_X1 cell11;
NOR3_X1 cell12;
OR2_X1 cell13;
OR2_X2 cell14;
NAND2_X1 cell15;
NAND3_X1 cell16;
AND2_X1 cell17;
AND2_X2 cell18;
XOR2_X1 cell19;
XNOR2_X1 cell20;
MUX2_X1 cell25;
OAI21_X1 cell26;
AOI21_X1 cell27;
OAI22_X1 cell28;
AOI22_X1 cell29;
TBUF1_X1 cell30;
TBUF_X2 cell31;

510
dataflow_neuro/chips.act
View File

@@ -1,510 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/interfaces.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
REG_NCA, REG_NCW, REG_M>
defproc texel_core (avMx1of2<N_IN> in, out;
Mx1of2<REG_NCW> reg_data[REG_M];
// Dummy synapses and neurons in the handshake blocks
// should be removed pre-innovus, else they are floating.
// a1of1 synapses[N_SYN_X * N_SYN_Y];
// a1of1 neurons[N_NRN_X * N_NRN_Y];
// Synapse decoder stuff
// The analogue core and connects to these to replace the above synapses.
bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
bool? dec_ackB[N_SYN_X];
a1of1 syn_pu[N_SYN_X];
// Neuron encoder stuff
a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
// Monitors and flags to/from core, and selected mon out.
bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
power supply;
bool? reset_B, reset_reg_B){
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
pint index = 0; // Just useful
// Onwards
fifo<N_IN,N_BUFFERS> fifo_in(.in = in, .reset_B = _reset_BX, .supply = supply);
demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
// Register
fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
.supply = supply, .reset_B = reset_reg_B);
fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);
// Spike Decoder
pint NC_SYN;
NC_SYN = NC_SYN_X + NC_SYN_Y;
slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
.hs_en = register.data[0].d[0].t, // Defaults to handshake disable
.ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
.out_req_x = dec_req_x, .out_req_y = dec_req_y,
.to_pu = syn_pu,
.in_ackB_decoder = dec_ackB,
.supply = supply, .reset_B = _reset_BX);
INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG];
(i:N_SYN_DLY_CFG:
dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
dly_cfg_inverters[i].vdd = supply.vdd;
dly_cfg_inverters[i].vss = supply.vss;
decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
)
// Synapse handshake circuits, to be removed for innovus
// decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
// .synapses = synapses,
// .in_req_x = dec_req_x, .in_req_y = dec_req_y,
// .to_pu = syn_pu,
// .out_ackB_decoder = dec_ackB,
// .supply = supply);
// Neurons + encoder
pint NC_NRN;
NC_NRN = NC_NRN_X + NC_NRN_Y;
encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
.inx = enc_inx, .iny = enc_iny,
.reset_B = _reset_BX, .supply = supply,
.to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
.reset_B = _reset_BX, .supply = supply);
// Neuron handshake circuits, to be removed for innovus
// nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
// .outx = enc_inx, .outy = enc_iny,
// .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
// .supply = supply, .reset_B = _reset_BX);
// Merge
append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
append<N_IN-2, 2, 2> append_reg(.in = fifo_reg2mrg.out, .supply = supply);
merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out,
.supply = supply, .reset_B = _reset_BX);
// Output
fifo<N_IN, N_BUFFERS> fifo_out(.in = merge_enc8reg.out, .out = out,
.reset_B = _reset_BX, .supply = supply);
// Neuron/synapse monitor targeters
pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
nrn_mon_dec_x.en = register.data[1].d[0].t;
(i:NC_NRN_MON_X:
nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
)
sigbuf_boolarray<N_NRN_MON_X, 13> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
nrn_mon_dec_y.en = register.data[1].d[0].t;
(i:NC_NRN_MON_Y:
nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
)
sigbuf_boolarray<N_NRN_MON_Y, 48> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
.supply = supply);
syn_mon_dec_x.en = register.data[1].d[1].t;
(i:NC_SYN_MON_X:
syn_mon_dec_x.in.d[i] = register.data[3].d[i];
)
sigbuf_boolarray<N_SYN_MON_X, 13> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
syn_mon_dec_y.en = register.data[1].d[1].t;
(i:NC_SYN_MON_Y:
syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
)
sigbuf_boolarray<N_SYN_MON_Y, 48> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
// Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
// Stops the possibility of dev_mon being high while some other sig is high.
// Otherwise boom.
bool DEV_DEBUG;
pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
.supply = supply);
DEV_DEBUG = sb_DEV_DEBUG.out[0];
[NSMX4 >= 1 ->
AND2_X1 ands_devmon[NSMX4];
(i:NSMX4:
ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
ands_devmon[i].b = DEV_DEBUG;
ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
ands_devmon[i].vdd = supply.vdd;
ands_devmon[i].vss = supply.vss;
)
// Wire up the non-ANDed lines.
(i:N_SYN_MON_X:
[~(i%4 = 1) ->
syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
]
)
]
// Create TBUFs for each synapse column,
// ctrl wired to mon line (first in each 4).
TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
(j:N_MON_AMZO_PER_SYN:
(i:N_SYN_X:
index = i*N_MON_AMZO_PER_SYN + j;
syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
)
)
// Create TBUFs for each neuron column,
// ctrl wired to mon line (first in each 4).
TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply);
(j:N_MON_AMZO_PER_NRN:
(i:N_NRN_X:
index = i*N_MON_AMZO_PER_NRN + j;
nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index];
nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
)
)
// Create NON buffered signals from register to nrns.
(i:N_FLAGS_PER_NRN:
nrn_flags_EFO[i] = register.data[5].d[i].t;
)
// Create NON buffered signals from register to synapses.
// Includes safety on the first 3 flags with dev mon.
(i:3..N_FLAGS_PER_SYN-1:
syn_flags_EFO[i] = register.data[4].d[i].t;
)
AND2_X1 syn_flags_dev_safety[3];
BUF_X4 syn_flags_dev_safety_sb[3];
(i:0..2:
syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
syn_flags_dev_safety_sb[i].a = syn_flags_dev_safety[i].y;
syn_flags_dev_safety_sb[i].y = syn_flags_EFO[i];
syn_flags_dev_safety[i].vdd = supply.vdd;
syn_flags_dev_safety[i].vss = supply.vss;
syn_flags_dev_safety_sb[i].vdd = supply.vdd;
syn_flags_dev_safety_sb[i].vss = supply.vss;
)
}
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M>
defproc texel_singlecore (bd<N_IN> in, out;
Mx1of2<REG_NCW> reg_data[REG_M];
// a1of1 synapses[N_SYN_X * N_SYN_Y];
// a1of1 neurons[N_NRN_X * N_NRN_Y];
bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B){
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
pint index = 0; // Just useful
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = _reset_BX, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
// Loopback
fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
.supply = supply);
fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
// Onwards to core
fifo<N_IN,N_BUFFERS> fifo_fork2core(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
texel_core<N_IN,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core(.in = fifo_fork2core.out,
.reg_data = reg_data,
// .synapses = synapses,
// .neurons = neurons,
.nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
.syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
.syn_mon_AMZI = syn_mon_AMZI, .nrn_mon_AMZI = nrn_mon_AMZI,
.syn_mon_AMZO = syn_mon_AMZO, .nrn_mon_AMZO = nrn_mon_AMZO,
.syn_flags_EFO = syn_flags_EFO, .nrn_flags_EFO = nrn_flags_EFO,
.reset_B = _reset_BX,
.supply = supply
);
// qdi2bd
fifo<N_IN, N_BUFFERS> fifo_core2mrg(.in = core.out,
.reset_B = _reset_BX, .supply = supply);
// merge core output and loopback
merge<N_IN> merge_drop8core(.in1 = fifo_core2mrg.out, .in2 = fifo_drop2mrg.out,
.supply = supply, .reset_B = _reset_BX);
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = merge_drop8core.out, .out = out, .dly_cfg = bd_dly_cfg,
.reset_B = _reset_BX, .supply = supply);
}
export template<pint N_IN, // Size of input data from outside world
N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M>
defproc texel_dualcore (bd<N_IN> in, out;
Mx1of2<REG_NCW> c1_reg_data[REG_M];
// a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
bool? c1_dec_ackB[N_SYN_X];
a1of1 c1_syn_pu[N_SYN_X];
a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
Mx1of2<REG_NCW> c2_reg_data[REG_M];
// a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
// a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
bool? c2_dec_ackB[N_SYN_X];
a1of1 c2_syn_pu[N_SYN_X];
a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B, reset_reg_B){
// Reset buffers
bool _reset_BX;
BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = _reset_BX, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
// Loopback
fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
.supply = supply);
fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
// Onwards to core demux
fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
// Cores
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core1(.in = fifo_dmx2core1.out,
.reg_data = c1_reg_data,
// .synapses = c1_synapses,
// .neurons = c1_neurons,
.dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
.dec_ackB = c1_dec_ackB,
.syn_pu = c1_syn_pu,
.enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
.nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
.nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
.syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
.syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
.syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
.syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
.supply = supply
);
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
core2(.in = fifo_dmx2core2.out,
.reg_data = c2_reg_data,
// .synapses = c2_synapses,
// .neurons = c2_neurons,
.dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
.dec_ackB = c2_dec_ackB,
.syn_pu = c2_syn_pu,
.enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
.nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
.nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
.syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
.syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
.syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
.syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
.supply = supply
);
fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
// Merge cores
append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
.supply = supply, .reset_B = _reset_BX);
// Merge cores and loopback
merge<N_IN> merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out,
.reset_B = _reset_BX, .supply = supply);
// qdi2bd
fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
.reset_B = _reset_BX, .supply = supply);
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
.reset_B = _reset_BX, .supply = supply);
}
}
}

1169
dataflow_neuro/coders.act
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File diff suppressed because it is too large Load Diff

174
dataflow_neuro/interfaces.act
View File

@@ -1,174 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import std::channel;
open std::channel;
// import std::func;
open std;
import std::data;
open std::data;
namespace tmpl {
namespace dataflow_neuro {
/**
* Bundled data (non dual rail, with req)
* 2
* quasi delay insensitive channel (dual rail).
* Basically a buffer with a bitwise conversion in front of it.
*/
export template<pint N, N_dly_cfg, N_dly_cfg2>
defproc bd2qdi(bd<N> in; avMx1of2<N> out; bool? dly_cfg[N_dly_cfg], dly_cfg2[N_dly_cfg2];
power supply; bool? reset_B) {
// Delay on req_in
bool _req;
delayprog<N_dly_cfg> dly(.in = in.r, .out = _req, .s = dly_cfg, .supply = supply);
// sig buff the reset signal
bool _reset_BX, _reset_BXX[N*2];
BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
// sig buff the req
bool _reqX, _reqXX[N*2];
BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
// For reasons of pure spice, the control circuitry
// requires a req signal that FALLS SLOWER than the req going to the function block.
// Thus need another delay prog.
bool _req_slowfall;
delayprog<N_dly_cfg2> dly2(.in = _reqX, .s = dly_cfg2, .supply = supply);
OR2_X1 req_dly_or(.a = _reqX, .b = dly2.out, .y = _req_slowfall,
.vss = supply.vss, .vdd = supply.vdd);
// bd2qdi conversion
// Each line goes to a t pin, its not to an f.
bool _inB[N];
INV_X1 input_invs[N];
(i:N:
input_invs[i].a = in.d[i];
input_invs[i].y = _inB[i];
input_invs[i].vss = supply.vss;
input_invs[i].vdd = supply.vdd;
)
// BUFFER
// Basically the buffer_s but with the validity tree ripped out
// and just connected to in_req instead.
// And probably need a delay on the in_ack to ensure en has time to disable
// before the inputs go to another state.
// Actually apparently no: there is a fixed, huge delay, already incurred
// by communicating with pads-> uC -> windows 95 and back again.
// Since the input is never invalid, also need a mechanism
// for the output to become invalid, when an out_ack is received.
//control
bool _en;
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_req_slowfall,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_B;
A_2C2N_RB_X4 f_buf_func[N];
A_2C2N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=en_buf.out[i];
t_buf_func[i].c1=en_buf.out[i+N];
f_buf_func[i].c2=out_a_B_buf.out[i];
t_buf_func[i].c2=out_a_B_buf.out[i+N];
f_buf_func[i].n1=_inB[i];
t_buf_func[i].n1=in.d[i];
f_buf_func[i].n2=_reqXX[i];
t_buf_func[i].n2=_reqXX[i+N];
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i+N];
f_buf_func[i].sr_B = _reset_BXX[i+N];
)
}
/**
* quasi delay insensitive channel (dual rail).
* 2
* Bundled data (non dual rail, with req)
*/
export template<pint N, N_dly_cfg>
defproc qdi2bd(avMx1of2<N> in; bd<N> out; bool? dly_cfg[N_dly_cfg]; power supply; bool? reset_B) {
// Buffer
buffer<N> buf(.in = in, .supply = supply, .reset_B = reset_B);
buf.out.a = out.a;
// Vtree
vtree<N> out_vtree(.supply = supply);
(i:N:
out_vtree.in.d[i].t = buf.out.d.d[i].t;
out_vtree.in.d[i].f = buf.out.d.d[i].f;
)
buf.out.v = out_vtree.out;
// Delay
delayprog<N_dly_cfg> dly(.in = out_vtree.out, .out = out.r, .s = dly_cfg, .supply = supply);
out_vtree.out = dly.in;
// Wire output data bits to buffer True lines
(i:N:
buf.out.d.d[i].t = out.d[i];
)
}
}
}

821
dataflow_neuro/primitives.act
View File

@@ -2,11 +2,7 @@
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* Copyright (c) 2022 University of Groningen - Ole Richter
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
@@ -25,18 +21,12 @@
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import template::dataflow_neuro::cell_lib_std;
import template::dataflow_neuro::cell_lib_async;
import std::channel;
open std::channel;
// import std::func;
namespace tmpl {
namespace template {
namespace dataflow_neuro {
// @ole talk to rajit, we use valid the wrong way arround according to stdlib
@@ -78,8 +68,8 @@ namespace tmpl {
[(&i:M: d.d[i].t | d.d[i].f)];
self := 0;
(;i:M: [ d.d[i].t -> self := self | (1 << i)
[] else -> skip
]
[] else -> skip
]
)
}
@@ -109,799 +99,46 @@ namespace tmpl {
*
*/
export template<pint N>
defproc buffer (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
defproc buffer (avMx1of2<N> in; avMx1of2<N> out; rsp reset; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[N*2];
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
bool _en,_en_X,_preset_X,_sreset_X;
A_3C_RB_X4 inack_ctl(c1=en_X,c2=in.v,c3=out.v,y=in.a,pr_B=_preset_X,sr_B=_sreset_X,vdd=supply.vdd,vss=supply.vss);
A_1C1P_X1 en_ctl(c1=in.a,p1=out.v,y=_en,vdd=supply.vdd,vss=supply.vss);
sigbuf en_buf<N*2>(a=_en, y=_en_X, power=supply);
sigbuf preset_buf<N*2>(a=reset.p,y=preset_X, power=supply);
sigbuf sreset_buf<N*2>(a=reset.s,y=sreset_X, power=supply);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
ctree vc<N>(in=in.d,y=_in_v, power=supply);
sigbuf in_v_buf<12>(a=_in_v, y=in.v);
//function
bool _out_a_BX[N*2],_out_a_B;
bool _out_a_BX, _out_a_B;
A_2C1N_RB_X4 f_buf_func[N];
A_2C1N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out_a_B_buf(.in=_out_a_B,.out=_out_a_BX, .supply = supply);
INV_X1 out_a_inv(a=out.a,y=_out_a_B);
sigbuf out_a_B_buf<N*2>(a=_out_a_B,y=_out_a_BX);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=en_buf.out[i];
t_buf_func[i].c1=en_buf.out[i+N];
f_buf_func[i].c2=_out_a_BX[i];
t_buf_func[i].c2=_out_a_BX[i+N];
f_buf_func[i].c1=_en_X;
t_buf_func[i].c1=_en_X;
f_buf_func[i].c2=_out_a_BX;
t_buf_func[i].c2=_out_a_BX;
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].pr_B=_preset_X;
t_buf_func[i].pr_B=_preset_X;
f_buf_func[i].sr_B=_sreset_X;
t_buf_func[i].sr_B=_sreset_X;
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i+N];
f_buf_func[i].sr_B = _reset_BXX[i+N];
)
}
// A template creating a FIFO of M buffers with N bits each
export template<pint N;pint M>
defproc fifo(avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply)
{
buffer<N> fifo_element[M];
bool _reset_BXX[M];
fifo_element[0].in = in ;
fifo_element[0].supply = supply;
fifo_element[0].reset_B = _reset_BXX[0];
(i:1..M-1:
fifo_element[i].in = fifo_element[i-1].out;
fifo_element[i].supply = supply;
fifo_element[i].reset_B = _reset_BXX[i];
)
fifo_element[M-1].out = out;
// reset buffers
bool _reset_BX;
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<M> reset_bufarray(.in=_reset_BX, .out=_reset_BXX,.supply = supply);
}
/**
* Buffer_S template.
* S maybe stands for special.
* Like a buffer, except that the output function block does not load the data in
* until the input data is valid.
* Not entirely sure what the point of it is,
* Ole says is useful for funky timing scenarios.
*/
export template<pint N>
defproc buffer_s (avMx1of2<N> in; avMx1of2<N> out; bool? reset_B; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[N];
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
//validity
bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf4(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> in_v_bufN(.in = in.v, .supply = supply);
//function
bool _out_a_B;
A_2C2N_RB_X4 f_buf_func[N];
A_2C2N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply);
INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
// check if you can also do single var to array connect a=b[N]
// and remove them from the loop
(i:N:
f_buf_func[i].y=out.d.d[i].f;
t_buf_func[i].y=out.d.d[i].t;
f_buf_func[i].c1=en_buf.out[i];
t_buf_func[i].c1=en_buf.out[i+N];
f_buf_func[i].c2=out_a_B_buf.out[i];
t_buf_func[i].c2=out_a_B_buf.out[i+N];
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].n2=in_v_bufN.out[i];
t_buf_func[i].n2=in_v_bufN.out[i+N];
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
t_buf_func[i].pr_B = _reset_BXX[i];
t_buf_func[i].sr_B = _reset_BXX[i];
f_buf_func[i].pr_B = _reset_BXX[i];
f_buf_func[i].sr_B = _reset_BXX[i];
)
}
export template<pint N>
defproc demux (avMx1of2<N> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; avMx1of2<1> cond; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[2*N], _out_v, _in_c_v_;
OR2_X1 out_or(.a=out1.v, .b=out2.v, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3=_out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
cond.a = in.a; // THIS SHOULD BE IMPROVED UPON IN FUTURE VERSIONS
cond.v = _in_c_v_;
A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
bool _in_v, _c_f_buf[N], _c_t_buf[N], _c_v;
sigbuf<N> c_buf_t(.in=cond.d.d[0].t, .out=_c_t_buf, .supply=supply);
sigbuf<N> c_buf_f(.in=cond.d.d[0].f, .out=_c_f_buf, .supply=supply);
OR2_X1 c_f_c_t_or(.a=cond.d.d[0].t, .b=cond.d.d[0].f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss);
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
A_2C_B_X1 c_el(.c1=_c_v, .c2=_in_v, .y=_in_c_v_,.vdd=supply.vdd,.vss=supply.vss);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function
//func buffer out1
bool _out1_a_B;
A_2C2N_RB_X4 out1_f_buf_func[N];
A_2C2N_RB_X4 out1_t_buf_func[N];
sigbuf<N*4> out_en_buf(.in=_en, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
(i:N:
out1_f_buf_func[i].y=out1.d.d[i].f;
out1_t_buf_func[i].y=out1.d.d[i].t;
out1_f_buf_func[i].c1=out_en_buf.out[i];
out1_t_buf_func[i].c1=out_en_buf.out[i+N];
out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
out1_f_buf_func[i].n1=in.d.d[i].f;
out1_t_buf_func[i].n1=in.d.d[i].t;
out1_f_buf_func[i].vdd=supply.vdd;
out1_t_buf_func[i].vdd=supply.vdd;
out1_f_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].pr_B = _reset_BXX[i];
out1_t_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].pr_B = _reset_BXX[i];
out1_f_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].n2=_c_f_buf[i];
out1_t_buf_func[i].n2=_c_f_buf[i];
)
//func buffer out2
bool _out2_a_B;
A_2C2N_RB_X4 out2_f_buf_func[N];
A_2C2N_RB_X4 out2_t_buf_func[N];
// sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
(i:N:
out2_f_buf_func[i].y=out2.d.d[i].f;
out2_t_buf_func[i].y=out2.d.d[i].t;
out2_f_buf_func[i].c1=out_en_buf.out[i+2*N];
out2_t_buf_func[i].c1=out_en_buf.out[i+3*N];
out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
out2_f_buf_func[i].n1=in.d.d[i].f;
out2_t_buf_func[i].n1=in.d.d[i].t;
out2_f_buf_func[i].vdd=supply.vdd;
out2_t_buf_func[i].vdd=supply.vdd;
out2_f_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].pr_B = _reset_BXX[i+N];
out2_t_buf_func[i].sr_B = _reset_BXX[i+N];
out2_f_buf_func[i].pr_B = _reset_BXX[i+N];
out2_f_buf_func[i].sr_B = _reset_BXX[i+N];
out2_f_buf_func[i].n2=_c_t_buf[i];
out2_t_buf_func[i].n2=_c_t_buf[i];
)
}
export template<pint N>
defproc fork (avMx1of2<N> in; avMx1of2<N> out1; avMx1of2<N> out2 ; bool? reset_B; power supply) {
// control
bool _en, _reset_BX,_reset_BXX[N*2];
A_4C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out1.v,.c4=out2.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C2P_X1 en_ctl(.c1=in.a,.p1=out1.v,.p2=out2.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
//reset_buffers
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function
//func buffer out1
bool _out1_a_B;
A_2C1N_RB_X4 out1_f_buf_func[N];
A_2C1N_RB_X4 out1_t_buf_func[N];
sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B);
sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B);
(i:N:
out1_f_buf_func[i].y=out1.d.d[i].f;
out1_t_buf_func[i].y=out1.d.d[i].t;
out1_f_buf_func[i].c1=out1_en_buf.out[i];
out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
out1_f_buf_func[i].n1=in.d.d[i].f;
out1_t_buf_func[i].n1=in.d.d[i].t;
out1_f_buf_func[i].vdd=supply.vdd;
out1_t_buf_func[i].vdd=supply.vdd;
out1_f_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].pr_B = _reset_BXX[i];
out1_t_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].pr_B = _reset_BXX[i];
out1_f_buf_func[i].sr_B = _reset_BXX[i];
)
//func buffer out2
bool _out2_a_B;
A_2C1N_RB_X4 out2_f_buf_func[N];
A_2C1N_RB_X4 out2_t_buf_func[N];
sigbuf<N*2> out2_en_buf(.in=_en, .supply=supply);
INV_X1 out2_a_inv(.a=out2.a,.y=_out2_a_B);
sigbuf<N*2> out2_a_B_buf(.in=_out2_a_B);
(i:N:
out2_f_buf_func[i].y=out2.d.d[i].f;
out2_t_buf_func[i].y=out2.d.d[i].t;
out2_f_buf_func[i].c1=out2_en_buf.out[i];
out2_t_buf_func[i].c1=out2_en_buf.out[i+N];
out2_f_buf_func[i].c2=out2_a_B_buf.out[i];
out2_t_buf_func[i].c2=out2_a_B_buf.out[i+N];
out2_f_buf_func[i].n1=in.d.d[i].f;
out2_t_buf_func[i].n1=in.d.d[i].t;
out2_f_buf_func[i].vdd=supply.vdd;
out2_t_buf_func[i].vdd=supply.vdd;
out2_f_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].vss=supply.vss;
out2_t_buf_func[i].pr_B = _reset_BXX[i];
out2_t_buf_func[i].sr_B = _reset_BXX[i];
out2_f_buf_func[i].pr_B = _reset_BXX[i];
out2_f_buf_func[i].sr_B = _reset_BXX[i];
)
}
// Demux
export template<pint N; pbool CONDITION_SIGN>
defproc demux_td (avMx1of2<N> in; avMx1of2<N> out1; a1of1 token; bool? reset_B; avMx1of2<1> cond; power supply) {
//control
bool _en, _reset_BX,_reset_BXX[N], _out_v, _in_c_v_, _reset_BXt;
OR2_X1 out_or(.a=out1.v, .b=token.r, .y=_out_v,.vdd=supply.vdd,.vss=supply.vss);
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_in_c_v_,.c3= _out_v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=_out_v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_token(.a=_reset_BX, .y=_reset_BXt,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
//validity
bool _in_v, _c_tk_buf, _c_d_buf[N], _c_v, cond_inv_t, cond_inv_f;
cond.a = in.a;
cond.v = _c_v;
OR2_X1 c_f_c_t_or(.a=cond.d.d[0].t, .b=cond.d.d[0].f, .y=_c_v,.vdd=supply.vdd,.vss=supply.vss);
//orientation of condition
[ CONDITION_SIGN ->
BUF_X1 c_buf_tk(.a=cond.d.d[0].t, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d(.in=cond.d.d[0].f, .out=_c_d_buf, .supply=supply);
[] else ->
INV_X1 invout_t(.a = cond.d.d[0].t,.y=cond_inv_t,.vdd = supply.vdd,.vss=supply.vss);
INV_X1 invout_f(.a = cond.d.d[0].f,.y=cond_inv_f,.vdd = supply.vdd,.vss=supply.vss);
BUF_X1 c_buf_tk_inv(.a=cond_inv_t, .y=_c_tk_buf, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N> c_buf_d_inv(.in=cond_inv_f, .out=_c_d_buf, .supply=supply);
]
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
A_2C_B_X1 c_el(.c1=_c_v, .c2=_in_v, .y=_in_c_v_,.vdd=supply.vdd,.vss=supply.vss);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function
//func buffer out1
bool _out1_a_B;
A_2C2N_RB_X4 out1_f_buf_func[N];
A_2C2N_RB_X4 out1_t_buf_func[N];
sigbuf<N*2> out1_en_buf(.in=_en, .supply=supply);
INV_X1 out1_a_inv(.a=out1.a,.y=_out1_a_B, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> out1_a_B_buf(.in=_out1_a_B, .supply=supply);
(i:N:
out1_f_buf_func[i].y=out1.d.d[i].f;
out1_t_buf_func[i].y=out1.d.d[i].t;
out1_f_buf_func[i].c1=out1_en_buf.out[i];
out1_t_buf_func[i].c1=out1_en_buf.out[i+N];
out1_f_buf_func[i].c2=out1_a_B_buf.out[i];
out1_t_buf_func[i].c2=out1_a_B_buf.out[i+N];
out1_f_buf_func[i].n1=in.d.d[i].f;
out1_t_buf_func[i].n1=in.d.d[i].t;
out1_f_buf_func[i].vdd=supply.vdd;
out1_t_buf_func[i].vdd=supply.vdd;
out1_f_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].vss=supply.vss;
out1_t_buf_func[i].pr_B = _reset_BXX[i];
out1_t_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].pr_B = _reset_BXX[i];
out1_f_buf_func[i].sr_B = _reset_BXX[i];
out1_f_buf_func[i].n2=_c_d_buf[i];
out1_t_buf_func[i].n2=_c_d_buf[i];
)
//token out
bool token_a_out;
A_2C2N_RB_X4 token_buf;
INV_X1 outt_a_inv(.a=token.a,.y=token_a_out, .vss = supply.vss, .vdd = supply.vdd);
token_buf.y = token.r;
token_buf.c1 = _en;
token_buf.c2 = token_a_out;
token_buf.n1 = _c_tk_buf;
token_buf.n2 = _in_v;
token_buf.vdd = supply.vdd;
token_buf.vss = supply.vss;
token_buf.pr_B = _reset_BXt;
token_buf.sr_B = _reset_BXt;
}
/**
* Drops a packet if condition is met, otherwise passes it on.
* This is a very lazy implementation, where the cond MUST NOT CHANGE DURING OPERATION.
* Means that this should be used in a very small set of circumstances.
*
* params:
* N: size of packet
* CONDITION_DROP: value of cond when packets are dropped.
*/
export template<pint N; pbool CONDITION_DROP>
defproc dropper_static (avMx1of2<N> in; avMx1of2<N> out; bool? cond; power supply) {
bool _drop, _dropB;
INV_X1 inv(.a = cond, .vss = supply.vss, .vdd = supply.vdd);
[~CONDITION_DROP ->
_dropB = cond;
_drop = inv.y;
[] CONDITION_DROP ->
_drop = cond;
_dropB = inv.y;
]
bool _in_vX;
vtree<N> vt(.in = in.d, .supply = supply);
BUF_X4 in_v_buf(.a = vt.out, .y = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
AND2_X1 and2(.a = _drop, .b = _in_vX, .vss = supply.vss, .vdd = supply.vdd);
OR2_X1 or2(.a = out.a, .b = and2.y, .vss = supply.vss, .vdd = supply.vdd);
A_2C_B_X1 ack_Cel(.c1 = or2.y, .c2 = _in_vX, .y = in.a);
// _in_vX = in.v;
// Sigbufs
sigbuf<N*2> sb_dropB(.in = _dropB, .supply = supply);
sigbuf<N*2+1> sb_in_v(.in = _in_vX, .supply = supply);
sb_in_v.out[2*N] = in.v;
AND3_X1 and_t[N];
AND3_X1 and_f[N];
(i:N:
and_t[i].a = in.d.d[i].t;
and_f[i].a = in.d.d[i].f;
and_t[i].y = out.d.d[i].t;
and_f[i].y = out.d.d[i].f;
and_t[i].b = sb_dropB.out[i];
and_f[i].b = sb_dropB.out[i+N];
and_t[i].c = sb_in_v.out[i];
and_f[i].c = sb_in_v.out[i+N];
and_t[i].vss = supply.vss;
and_t[i].vdd = supply.vdd;
)
}
export
defproc arbiter_handshake(a1of1 in1; a1of1 in2; a1of1 out; power supply)
{
bool _y1_arb,_y2_arb;
A_2C_B_X1 ack_cell1(.c1 = out.a,.c2 = _y1_arb,.y = in1.a,.vdd = supply.vdd, .vss = supply.vss);
A_2C_B_X1 ack_cell2(.c1 = out.a,.c2 = _y2_arb,.y = in2.a,.vdd = supply.vdd, .vss = supply.vss);
OR2_X1 or_cell(.a = _y1_arb, .b = _y2_arb, .y = out.r,.vdd = supply.vdd, .vss = supply.vss);
ARBITER arbiter(.a = in1.r, .b = in2.r, .c = in2.a, .d = in1.a, .y1 = _y1_arb, .y2 = _y2_arb, .vdd = supply.vdd, .vss = supply.vss);
}
//The buffer_t_valid doesn't work
// export
// defproc buffer_t_valid(a1of1 in; a1of1 out; bool? reset_B; power supply)
// {
// //control
// bool _en, _reset_BX;
// A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.c3=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
// //function
// bool _out_a_B;
// INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
// A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
// //reset buffers
// BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
// }
export template<pint N>
defproc merge (avMx1of2<N> in1; avMx1of2<N> in2; avMx1of2<N> out ; bool? reset_B; power supply) {
//out acknowledge sigbuffer and inverter
bool _out_a_B,_out_a_BX[2*N];
INV_X1 out_a_inverter(.a = out.a, .y = _out_a_B);
sigbuf<2*N> out_a_buffer(.in = _out_a_B,.out = _out_a_BX,.supply=supply);
//control
bool _in1_a_B,_in2_a_B,_en,_en_X[2*N], _reset_BX,_reset_BXX[2*N];
bool _in1_arb,_in2_arb,_in1_arb_X[2*N],_in2_arb_X[2*N];
A_4C_RB_X4 in1ack_ctl(.c1=_in1_arb,.c2=_en,.c3=in1.v,.c4=out.v,.y=in1.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_4C_RB_X4 in2ack_ctl(.c1=_in2_arb,.c2=_en,.c3=in2.v,.c4=out.v,.y=in2.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_4P1N1N_X1 en_ctl(.p1 = in1.a,.p2=in2.a,.p3=out.a,.p4 = out.v, .na1 = in1.a,.nb1 = in2.a,.y = _en,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<2*N> en_buffer(.in = _en,.out = _en_X,.supply=supply);
INV_X1 in1ack_ctl_inv(.a=in1.a,.y=_in1_a_B,.vdd=supply.vdd,.vss=supply.vss);
INV_X1 in2ack_ctl_inv(.a=in2.a,.y=_in2_a_B,.vdd=supply.vdd,.vss=supply.vss);
//reset_buffers
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
//validity
a1of1 _in1_temp,_in2_temp,_out_temp;
bool _in1_arb_temp,_in2_arb_temp;
vtree<N> vc1(.in=in1.d,.out=in1.v,.supply=supply);
vtree<N> vc2(.in=in2.d,.out=in2.v,.supply=supply);
arbiter_handshake validity_arb(.in1 = _in1_temp,.in2 = _in2_temp,.out =_out_temp, .supply = supply);
_in1_temp.r = in1.v;
_in2_temp.r = in2.v;
_in1_temp.a = _in1_arb_temp;
_in2_temp.a = _in2_arb_temp;
_out_temp.r = _out_temp.a;
AND2_X1 AND_arb1(.a = _in2_a_B,.b = _in1_arb_temp, .y = _in1_arb);
AND2_X1 AND_arb2(.a = _in1_a_B,.b = _in2_arb_temp, .y = _in2_arb);
sigbuf<2*N> arb2function1(.in = _in1_arb,.out = _in1_arb_X,.supply=supply);
sigbuf<2*N> arb2function2(.in = _in2_arb,.out = _in2_arb_X,.supply=supply);
//function
A_2C2N2N_RB_X1 merge_func_t[N];
A_2C2N2N_RB_X1 merge_func_f[N];
(i:N:
merge_func_t[i].c1 = _en_X[i];
merge_func_t[i].c2 = _out_a_BX[i];
merge_func_t[i].na1 = _in1_arb_X[i];
merge_func_t[i].na2 = in1.d.d[i].t;
merge_func_t[i].nb1 = _in2_arb_X[i];
merge_func_t[i].nb2 = in2.d.d[i].t;
merge_func_t[i].y = out.d.d[i].t;
merge_func_t[i].vdd=supply.vdd;
merge_func_t[i].vss=supply.vss;
merge_func_t[i].pr_B = _reset_BXX[i];
merge_func_t[i].sr_B = _reset_BXX[i];
merge_func_f[i].c1 = _en_X[i+N];
merge_func_f[i].c2 = _out_a_BX[i+N];
merge_func_f[i].na1 = _in1_arb_X[i+N];
merge_func_f[i].na2 = in1.d.d[i].f;
merge_func_f[i].nb1 = _in2_arb_X[i+N];
merge_func_f[i].nb2 = in2.d.d[i].f;
merge_func_f[i].y = out.d.d[i].f;
merge_func_f[i].vdd=supply.vdd;
merge_func_f[i].vss=supply.vss;
merge_func_f[i].pr_B = _reset_BXX[i+N];
merge_func_f[i].sr_B = _reset_BXX[i+N];
)
}
export
defproc buffer_t(a1of1 in; a1of1 out; bool? reset_B; power supply)
{
//control
bool _en, _reset_BX;
A_2C1N_RB_X4 inack_ctl(.c1=_en,.c2=in.r,.n1=out.r,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.r,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_B;
INV_X1 inv_outa(.a = out.a,.y=_out_a_B,.vdd = supply.vdd,.vss=supply.vss);
A_2C1N_RB_X4 buf_func(.c1 = _en,.c2 = _out_a_B, .n1 = in.r,.y = out.r, .pr_B = _reset_BX, .sr_B = _reset_BX,.vdd = supply.vdd,.vss=supply.vss);
//reset buffers
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
}
// A template creating a FIFO of N buffers tokens
export template<pint N>
defproc fifo_t(a1of1 in; a1of1 out; bool? reset_B; power supply)
{
buffer_t fifo_element[N];
bool _reset_BXX[N];
fifo_element[0].in.r = in.r;
fifo_element[0].in.a = in.a;
fifo_element[0].supply = supply;
fifo_element[0].reset_B = _reset_BXX[0];
(i:1..N-1:
fifo_element[i].in.r = fifo_element[i-1].out.r;
fifo_element[i].in.a = fifo_element[i-1].out.a;
fifo_element[i].supply = supply;
fifo_element[i].reset_B = _reset_BXX[i];
)
fifo_element[N-1].out.r = out.r;
fifo_element[N-1].out.a = out.a;
// reset buffers
bool _reset_BX;
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply = supply);
}
// Programmable delay line.
// N is the number of layers,
// the longest layer having 2**N DLY elements
// Circuit for creating delays, there are N delay layers.
// The block has the parameters:
// N -> the number is the number of layers with the longest being 2**N elements
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data
// out -> output data
// s -> bit word with size N that sets delay configuration. int(s) = number of delays
export template<pint N>
defproc delayprog (bool! out; bool? in, s[N]; power supply)
{
{ N >= 0 : "What?" };
{ N < 10 : "Delay prog size is given in 2**N. Given N is ridiculous." };
AND2_X1 and2[N];
MUX2_X1 mu2[N];
DLY4_X1 dly[(1<<N) -1];
bool _a[N+1]; // Holds the input to each row
_a[0] = in;
pint i_delay;
i_delay = 0; // Index of the last connected delay element
(i:0..N-1:
// For each row
and2[i].a = _a[i];
and2[i].b = s[i];
// Delays
dly[i_delay].a = and2[i].y;
i_delay = i_delay + 1;
(j:1..(1<<i)-1:
dly[i_delay].a = dly[i_delay-1].y;
i_delay = i_delay +1;
)
// Mux
mu2[i].a = _a[i];
mu2[i].s = s[i];
dly[i_delay-1].y = mu2[i].b;
_a[i+1] = mu2[i].y;
)
out = mu2[N-1].y;
// Connect everything to vdd/gnd
(i:N:and2[i].vdd = supply.vdd;)
(i:N:mu2[i].vdd = supply.vdd;)
(i:((1<<N)-1):dly[i].vdd = supply.vdd;)
(i:N:and2[i].vss = supply.vss;)
(i:N:mu2[i].vss = supply.vss;)
(i:((1<<N)-1):dly[i].vss = supply.vss;)
}
// Non programmable delays
// N is number of delays to have in series (not log!!).
// Is useful for testing purposes.
// But should probably remove before running innovus etc.
export template<pint N>
defproc delay_chain (bool out; bool in; power supply) {
{ N >= 0 : "What?" };
[N >= 1 ->
DLY4_X1 dly[N];
dly[0].vdd = supply.vdd;
dly[0].vss = supply.vss;
dly[0].a = in;
(i:1..N-1:
dly[i].vdd = supply.vdd;
dly[i].vss = supply.vss;
dly[i].a = dly[i-1].y;
)
dly[N-1].vdd = supply.vdd;
dly[N-1].vss = supply.vss;
dly[N-1].y = out;
[] N = 0 ->
in = out;
]
}
/**
* Appends a hard-coded word "VAL" to an input.
* Works by piping through all sigs, but adding
* some extra sigs when the input is valid.
* N is size of channel to pipe through.
* NVAL is size of word to be put on output.
* VAL is word to be put on output.
* Output looks like
* 0..............N........N+NVAL-1
* --input_data----LSB....MSB
*
*/
export template<pint N, NVAL, VAL>
defproc append (avMx1of2<N> in; avMx1of2<N+NVAL> out; power supply)
{
{ N >= 0 : "What?" };
{ NVAL >= 0 : "What?" };
{ VAL < 1<<NVAL : "VAL too big!" };
// valid tree
vtree<N> in_val(.supply = supply);
(i:N:
in_val.in.d[i].t = in.d.d[i].t;
in_val.in.d[i].f = in.d.d[i].f;
)
// wire through most signals
(i:N:
in.d.d[i].t = out.d.d[i].t;
in.d.d[i].f = out.d.d[i].f;
)
in.a = out.a;
in.v = out.v;
// appender
pint bitval;
sigbuf<NVAL> sb(.in = in_val.out, .supply = supply);
TIELO_X1 tielows[NVAL];
(i:NVAL:tielows[i].vss = supply.vss; tielows[i].vdd = supply.vdd;)
(i:0..NVAL-1:
bitval = (VAL & ( 1 << i )) >> i;
[ bitval = 1 ->
out.d.d[i+N].t = sb.out[i];
out.d.d[i+N].f = tielows[i].y;
[] bitval = 0 ->
out.d.d[i+N].f = sb.out[i];
out.d.d[i+N].t = tielows[i].y;
[] bitval >= 2 -> {false : "fuck"};
]
)
}
/**
* Drops bits. Slices lines. Crop in. Enhance.
* Useful if say, have an 8 bit packet coming in, but
* receiver only needs 3 of them.
* KEEPS all bits between the two bounds.
* e.g. drop_lines(8, 0, 3) would keep lines [0,1,2]
**/
export template<pint N, N0, N1>
defproc slice_data(avMx1of2<N> in; avMx1of2<std::min(N1,N)-std::max(N0,0)> out; power supply) {
// {N0 >= 0 : "N0 can be minimum 0!"};
// {N1 <= N : "N1 can be maximum N"};
pint _N1, _N0;
_N1 = std::min(N1,N);
_N0 = std::max(N0,0);
// BUF_X1 ack_buf(.a = out.a, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
vtree<N> in_vt(.in = in.d, .out = in.v, .supply = supply);
(i:_N1-_N0:
in.d.d[i + _N0] = out.d.d[i];
)
// in.a = out.a;
A_2C_B_X1 Cel(.c1 = out.a, .c2 =in.v, .y = in.a, .vss = supply.vss, .vdd = supply.vdd);
}
export template<pint N; pint CONDITION_BIT>
defproc demux_bit (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
{
demux<N> demux(.reset_B = reset_B, .out1=out1, .out2=out2);
in.d.d[CONDITION_BIT].f = demux.cond.d.d[0].f;
in.d.d[CONDITION_BIT].t = demux.cond.d.d[0].t;
A_2C_B_X1 val_Cel(.c1 = demux.in.v, .c2 = demux.cond.v, .y = in.v,
.vdd = supply.vdd, .vss = supply.vss);
// Not actually needed bc the current version of demux
// Something like below should be added once the handshakes are properly decoupled.
// wires the data and cond ack lines together anyway.
// A_2C_B_X1 ack_Cel(.c1 = demux.in.a, .c2 = demux.cond.a, .y = in.a,
// .vdd = supply.vdd, .vss = supply.vss);
// in.v = demux.in.v;
in.a = demux.in.a;
(i:0..CONDITION_BIT-1:
in.d.d[i].f = demux.in.d.d[i].f;
in.d.d[i].t = demux.in.d.d[i].t;)
(i:CONDITION_BIT+1..N:
in.d.d[i].f = demux.in.d.d[i-1].f;
in.d.d[i].t = demux.in.d.d[i-1].t;)
}
export template<pint N>
defproc demux_bit_msb (avMx1of2<N+1> in; avMx1of2<N> out1; avMx1of2<N> out2; bool? reset_B; power supply)
{
demux_bit<N,N> demux(.in = in, .out1 = out1, .out2 = out2, .reset_B = reset_B, .out1=out1, .out2=out2);
}
/**
* Create M sigbufs to buffer an M bool array to N strength.
* Done lazily.
**/
export template<pint M, N>
defproc sigbuf_boolarray(bool? in[M]; bool! out[M]; power supply) {
sigbuf<N> sb[M];
(i:M:
sb[i].in = in[i];
sb[i].out[0] = out[i];
sb[i].supply = supply;
)
}
}}
}
}

410
dataflow_neuro/registers.act
View File

@@ -1,410 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
/**
* Buffer for use in an A-cell register.
* Basically the same as a normal buffer, except that when out.v goes high,
* in.a goes high too.
* Also, in.a does not wait for out.v to go low to go to low.
* Means have a buffer that completes its Right handshake as soon as out data is valid.
*/
export template<pint N>
defproc buffer_register(avMx1of2<N> in; Mx1of2<N> out; bool? out_v, flush,
reset_B; power supply) {
//control
bool _en, _reset_BX[N];
bool _in_aB;
bool _reset;
bool _resetX[N];
// Reset sigs
INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply);
sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB,
.pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss);
INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss);
// Flush sigs
bool _flushB, _flushBX[N*2];
INV_X1 flush_inv(.a = flush, .y = _flushB);
sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply);
_en = _in_aB;
//validity
bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B;
A_1C2N_SB_X4 f_buf_func[N];
A_1C2N_RB_X4 t_buf_func[N];
sigbuf<N*2> en_buf(.in=_en, .supply=supply);
(i:N:
f_buf_func[i].y=out.d[i].f;
t_buf_func[i].y=out.d[i].t;
f_buf_func[i].c1=_flushBX[i];
t_buf_func[i].c1=_flushBX[i+N];
f_buf_func[i].n2=en_buf.out[i];
t_buf_func[i].n2=en_buf.out[i+N];
f_buf_func[i].n1=in.d.d[i].f;
t_buf_func[i].n1=in.d.d[i].t;
f_buf_func[i].vdd=supply.vdd;
t_buf_func[i].vdd=supply.vdd;
f_buf_func[i].vss=supply.vss;
t_buf_func[i].vss=supply.vss;
f_buf_func[i].pr = _resetX[i];
f_buf_func[i].sr = _resetX[i];
t_buf_func[i].pr_B = _reset_BX[i];
t_buf_func[i].sr_B = _reset_BX[i];
)
}
/**
* A single register made out of A cells.
* MSB is whether to read or write.
* Currently only handles writing.
*/
export template<pint N>
defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out;
bool? reset_B; power supply) {
bool _en2;
bool _w;
bool _out_v, _out_vB;
bool _flush, _flushB;
_w = in.d.d[N].t;
// Buffer
buffer_register<N> buf(.out = out, .out_v = _out_v, .flush = _flush,
.supply = supply, .reset_B = reset_B);
buf.in.v = in.v;
// In ack stuff
INV_X1 in_ack_inv(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
// To stop in ack going low before en2 has been reset.
A_1C1N_X1 in_ack_safety(.c1 = in_ack_inv.y, .n1 = _en2, .y = in.a,
.vdd = supply.vdd, .vss = supply.vss);
// Out valid tree
vtree<N> out_valid(.in = buf.out, .out = _out_v, .supply = supply);
INV_X2 out_val_inv(.a = _out_v, .y = _out_vB, .vdd = supply.vdd, .vss=supply.vss);
// Control
A_1C1P2N_RB_X1 A_flush(.c1 = _en2, .n1 = _out_v, .n2 = _w, .p1 = _flushB, .y = _flush,
.vdd = supply.vdd, .vss = supply.vss, .sr_B = reset_B, .pr_B = reset_B);
INV_X2 flush_inv(.a = _flush, .y = _flushB, .vdd = supply.vdd, .vss = supply.vss);
A_1C2N_R_X1 A_en2(.c1 = _w, .n1 = _en2, .n2 = _out_vB, .y = _en2,
.pr_B = reset_B, .sr_B = reset_B);
// Pass to let data into the buffer
NOR2_X1 pass(.a = _en2, .b = _flush, .vss = supply.vss, .vdd = supply.vdd);
sigbuf<N*2> passX(.in = pass.y, .supply = supply);
AND2_X1 gandalf_t[N];
AND2_X1 gandalf_f[N];
(i:0..N-1:
gandalf_t[i].a = in.d.d[i].t;
gandalf_f[i].a = in.d.d[i].f;
gandalf_t[i].b = passX.out[i];
gandalf_f[i].b = passX.out[i+N];
gandalf_t[i].y = buf.in.d.d[i].t;
gandalf_f[i].y = buf.in.d.d[i].f;
gandalf_t[i].vdd = supply.vdd;
gandalf_f[i].vdd = supply.vdd;
gandalf_t[i].vss = supply.vss;
gandalf_f[i].vss = supply.vss;
)
}
/**
* Array of registers made out of A-cells
* params:
* NcW: number of bits in Words to be stored in buffers
* NcA: number of bits in Address
* M: number of registers. M = 2^Nc_addr would be a natural choice.
* Input packets should be
* [-addr-][-word-][r/w]
*/
// UNUSED
// UNUSED
// UNUSED
// UNUSED
// export template<pint NcA, NcW, M>
// defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
// bool? reset_B; power supply) {
// // BIG TODO
// // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
// vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
// .supply = supply);
// // Address decoder
// decoder_dualrail<NcA, M> decoder(.supply = supply);
// (i:NcA:
// decoder.in.d[i] = in.d.d[i];
// )
// // OrTree over acks from all registers
// ortree<M> ack_ortree(.supply = supply);
// // C element handling in ack
// A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
// .vss = supply.vss, .vdd = supply.vdd);
// // Write bit selector
// bool _w = in.d.d[NcA+NcW].t;
// A_2C_B_X1 write_selectors[M];
// (i:M:
// write_selectors[i].c1 = _w;
// write_selectors[i].c2 = decoder.out[i];
// write_selectors[i].vdd = supply.vdd;
// write_selectors[i].vss = supply.vss;
// )
// // Registers
// register_acells<NcW> registers[M];
// TIELO_X1 tielow_writebit_f[M];
// (i:M:
// // Connect each register to word inputs.
// (j:NcW:
// registers[i].in.d.d[j] = in.d.d[j + NcA];
// )
// // Connect the (selected) write bit
// registers[i].in.d.d[NcW].t = write_selectors[i].y;
// tielow_writebit_f[i].vdd = supply.vdd;
// tielow_writebit_f[i].vss = supply.vss;
// registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
// // Connect to ack ortree
// registers[i].in.a = ack_ortree.in[i];
// // Connect outputs
// data[i] = registers[i].out;
// registers[i].supply = supply;
// registers[i].reset_B = reset_B;
// )
// }
/**
* Array of registers made out of A-cells
* params:
* NcW: number of bits in Words to be stored in buffers
* NcA: number of bits in Address
* M: number of registers. M = 2^Nc_addr would be a natural choice.
* Input packets should be
* [-addr-][-word-][r/w]
*/
export template<pint NcA, NcW, M>
defproc register_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
bool? reset_B; power supply) {
// Input valid tree
vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
.supply = supply);
// Address decoder
decoder_dualrail<NcA, M> decoder(.supply = supply);
(i:NcA:
decoder.in.d[i] = in.d.d[i];
)
// OrTree over acks from all registers
ortree<M> ack_ortree(.supply = supply);
bool _write_ack;
// C element handling in ack
A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
.vss = supply.vss, .vdd = supply.vdd);
// Bit to join the acks either from read or write
bool _read_ack;
_read_ack = out.a;
OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack,
.vdd = supply.vdd, .vss = supply.vss);
A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
// Write bit selector
bool _w = in.d.d[NcA+NcW].t;
bool _wX[M];
sigbuf<M> _w_sb(.in = _w, .out = _wX, .supply = supply);
A_2C_B_X1 write_selectors[M];
(i:M:
write_selectors[i].c1 = _wX[i];
write_selectors[i].c2 = decoder.out[i];
write_selectors[i].vdd = supply.vdd;
write_selectors[i].vss = supply.vss;
)
// Registers
register_acells<NcW> registers[M];
TIELO_X1 tielow_writebit_f[M];
(i:M:
// Connect each register to word inputs.
(j:NcW:
registers[i].in.d.d[j] = in.d.d[j + NcA];
)
// Connect the (selected) write bit
registers[i].in.d.d[NcW].t = write_selectors[i].y;
tielow_writebit_f[i].vdd = supply.vdd;
tielow_writebit_f[i].vss = supply.vss;
registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
// Connect to ack ortree
registers[i].in.a = ack_ortree.in[i];
// Connect outputs
data[i] = registers[i].out;
registers[i].supply = supply;
registers[i].reset_B = reset_B;
)
// Read bit selector
bool _r = in.d.d[NcA+NcW].f;
bool _rX[M+NcA];
sigbuf<M+NcA> _r_sb(.in = _r, .out = _rX, .supply = supply);
A_2C_B_X1 read_selectors[M];
sigbuf_boolarray<M, NcW*2> read_selectorsX(.supply = supply);
(i:M:
read_selectors[i].c1 = _rX[i];
read_selectors[i].c2 = decoder.out[i];
read_selectors[i].vdd = supply.vdd;
read_selectors[i].vss = supply.vss;
read_selectorsX.in[i] = read_selectors[i].y;
)
// OrTrees for each output word bit on read
ortree<M> out_ortrees_t[NcW];
ortree<M> out_ortrees_f[NcW];
(i:NcW:
out_ortrees_t[i].out = out.d.d[i+NcA].t;
out_ortrees_f[i].out = out.d.d[i+NcA].f;
out_ortrees_t[i].supply = supply;
out_ortrees_f[i].supply = supply;
)
// ANDs over each reg's data
// and whether it is selected for read.
AND2_X1 and_reads_t[NcW * M];
AND2_X1 and_reads_f[NcW * M];
pint index;
(i:NcW:
(j:M:
index = i + j*NcW;
and_reads_t[index].a = data[j].d[i].t;
and_reads_t[index].b = read_selectorsX.out[j];
and_reads_f[index].a = data[j].d[i].f;
and_reads_f[index].b = read_selectorsX.out[j];
and_reads_t[index].y = out_ortrees_t[i].in[j];
and_reads_f[index].y = out_ortrees_f[i].in[j];
and_reads_t[index].vss = supply.vss;
and_reads_t[index].vdd = supply.vdd;
and_reads_f[index].vss = supply.vss;
and_reads_f[index].vdd = supply.vdd;
)
)
// C elements passing address to out on read.
A_2C_B_X1 addr_read_t[NcA];
A_2C_B_X1 addr_read_f[NcA];
(i:NcA:
addr_read_t[i].c1 = in.d.d[i].t;
addr_read_f[i].c1 = in.d.d[i].f;
addr_read_t[i].c2 = _rX[M+i];
addr_read_f[i].c2 = _rX[M+i];
addr_read_t[i].y = out.d.d[i].t;
addr_read_f[i].y = out.d.d[i].f;
addr_read_t[i].vdd = supply.vdd;
addr_read_t[i].vss = supply.vss;
addr_read_f[i].vdd = supply.vdd;
addr_read_f[i].vss = supply.vss;
)
}
}}

481
dataflow_neuro/treegates.act
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@@ -1,481 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Madison Cotteret
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2021 Rajit Manohar
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
/*
* Build an OR-gate tree (NOR/NAND/optional INV)
*/
export deftype power (bool?! vdd, vss) { }
export template<pint N>
defproc ortree (bool? in[N]; bool! out; power supply)
{
bool tout;
{ N > 0 : "What?" };
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
pint lenTree2Count, lenTree3Count;
lenTree2Count = 0;
lenTree3Count = 0;
/* Pre"calculate" the number of C cells required, look below if confused */
*[ i != end ->
j = 0;
*[ i < end ->
j = j + 1;
[ i+1 >= end ->
i = end;
lenTree2Count = lenTree2Count +1;
[] i+2 >= end ->
i = end;
lenTree3Count = lenTree3Count +1;
[] else ->
i = i + 2;
lenTree2Count = lenTree2Count +1;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
/* array that holds ALL the nodes in the completion tree */
bool tmp[end+1];
(k:N:tmp[k] = in[k];)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
OR2_X1 or2s[lenTree2Count];
]
[lenTree3Count > 0 ->
OR3_X1 or3s[lenTree3Count];
]
(h:lenTree2Count:or2s[h].vdd = supply.vdd;)
(h:lenTree3Count:or3s[h].vdd = supply.vdd;)
(h:lenTree2Count:or2s[h].vss = supply.vss;)
(h:lenTree3Count:or3s[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
end = N-1;
j = 0;
pint tree2Index = 0;
pint tree3Index = 0;
/* Invariant: i <= end */
*[ i != end ->
/*
* Invariant: tmp[i..end] has the current signals that need to be
* combined together, and "isinv" specifies if they are the inverted
* sense or not
*/
j = 0;
*[ i < end ->
/*-- there are still signals that need to be combined --*/
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
or2s[tree2Index].a = tmp[i];
or2s[tree2Index].b = tmp[i+1];
or2s[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
or3s[tree3Index].a = tmp[i];
or3s[tree3Index].b = tmp[i+1];
or3s[tree3Index].c = tmp[i+2];
or3s[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
or2s[tree2Index].a = tmp[i];
or2s[tree2Index].b = tmp[i+1];
or2s[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
out = tmp[end];
]
}
export template<pint N>
defproc andtree (bool? in[N]; bool! out; power supply)
{
bool tout;
{ N > 0 : "What?" };
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
pint lenTree2Count, lenTree3Count;
lenTree2Count = 0;
lenTree3Count = 0;
/* Pre"calculate" the number of C cells required, look below if confused */
*[ i != end ->
j = 0;
*[ i < end ->
j = j + 1;
[ i+1 >= end ->
i = end;
lenTree2Count = lenTree2Count +1;
[] i+2 >= end ->
i = end;
lenTree3Count = lenTree3Count +1;
[] else ->
i = i + 2;
lenTree2Count = lenTree2Count +1;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
/* array that holds ALL the nodes in the completion tree */
bool tmp[end+1];
(k:N:tmp[k] = in[k];)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
AND2_X1 and2s[lenTree2Count];
]
[lenTree3Count > 0 ->
AND3_X1 and3s[lenTree3Count];
]
(h:lenTree2Count:and2s[h].vdd = supply.vdd;)
(h:lenTree3Count:and3s[h].vdd = supply.vdd;)
(h:lenTree2Count:and2s[h].vss = supply.vss;)
(h:lenTree3Count:and3s[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
end = N-1;
j = 0;
pint tree2Index = 0;
pint tree3Index = 0;
/* Invariant: i <= end */
*[ i != end ->
/*
* Invariant: tmp[i..end] has the current signals that need to be
* combined together, and "isinv" specifies if they are the inverted
* sense or not
*/
j = 0;
*[ i < end ->
/*-- there are still signals that need to be combined --*/
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
and2s[tree2Index].a = tmp[i];
and2s[tree2Index].b = tmp[i+1];
and2s[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
and3s[tree3Index].a = tmp[i];
and3s[tree3Index].b = tmp[i+1];
and3s[tree3Index].c = tmp[i+2];
and3s[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
and2s[tree2Index].a = tmp[i];
and2s[tree2Index].b = tmp[i+1];
and2s[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
out = tmp[end];
]
}
/*
* Build a completion tree using a combination of 2-input and 3-input
* C-elements
*/
export template<pint N>
defproc ctree (bool? in[N]; bool! out; power supply)
{
bool tout;
{ N > 0 : "What?" };
bool meaningless_var;
[N = 1 -> BUF_X1 b(.vss=supply.vss, .vdd = supply.vdd, .a = in[0], .y = out);
[] N > 1 ->
pint i, end, j;
i = 0;
end = N-1;
pint lenTree2Count, lenTree3Count;
lenTree2Count = 0;
lenTree3Count = 0;
/* Pre"calculate" the number of C cells required, look below if confused */
*[ i != end ->
j = 0;
*[ i < end ->
j = j + 1;
[ i+1 >= end ->
i = end;
lenTree2Count = lenTree2Count +1;
[] i+2 >= end ->
i = end;
lenTree3Count = lenTree3Count +1;
[] else ->
i = i + 2;
lenTree2Count = lenTree2Count +1;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
]
/* array that holds ALL the nodes in the completion tree */
bool tmp[end+1];
// Connecting the first nodes to the input
(l:N:
tmp[l] = in[l];
)
/* array to hold the actual C-elments, either A2C or A3C */
[lenTree2Count > 0 ->
A_2C_B_X1 C2Els[lenTree2Count];
]
[lenTree3Count > 0 ->
A_3C_B_X1 C3Els[lenTree3Count];
]
(h:lenTree2Count:C2Els[h].vdd = supply.vdd;)
(h:lenTree3Count:C3Els[h].vdd = supply.vdd;)
(h:lenTree2Count:C2Els[h].vss = supply.vss;)
(h:lenTree3Count:C3Els[h].vss = supply.vss;)
/* Reset the variables we just stole lol */
i = 0;
end = N-1;
j = 0;
pint tree2Index = 0;
pint tree3Index = 0;
/* Invariant: i <= end */
*[ i != end ->
/*
* Invariant: tmp[i..end] has the current signals that need to be
* combined together, and "isinv" specifies if they are the inverted
* sense or not
*/
j = 0;
*[ i < end ->
/*-- there are still signals that need to be combined --*/
j = j + 1;
[ i+1 >= end ->
/*-- last piece: use either a 2 input C-element --*/
C2Els[tree2Index].c1 = tmp[i];
C2Els[tree2Index].c2 = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = end;
[] i+2 >= end ->
/*-- last piece: use either a 3 input C-element --*/
C3Els[tree3Index].c1 = tmp[i];
C3Els[tree3Index].c2 = tmp[i+1];
C3Els[tree3Index].c3 = tmp[i+2];
C3Els[tree3Index].y = tmp[end+j];
tree3Index = tree3Index +1;
i = end;
[] else ->
/*-- more to come; so use a two input C-element --*/
C2Els[tree2Index].c1 = tmp[i];
C2Els[tree2Index].c2 = tmp[i+1];
C2Els[tree2Index].y = tmp[end+j];
tree2Index = tree2Index +1;
i = i + 2;
]
]
/*-- update range that has to be combined --*/
i = end+1;
end = end+j;
j = 0;
]
out = tmp[end];
]
}
export template<pint N>
defproc vtree (std::data::Mx1of2?<N> in; bool! out; power supply)
{
// OR layer for making OR between true and false of in (they are then sent to Ctree)
OR2_X1 OR2_tf[N];
ctree<N> ct;
(l:N:
OR2_tf[l].a = in.d[l].t;
OR2_tf[l].b = in.d[l].f;
OR2_tf[l].y = ct.in[l];
OR2_tf[l].vdd = supply.vdd;
OR2_tf[l].vss = supply.vss;
)
ct.supply = supply;
out = ct.out;
}
export template<pint N>
defproc sigbuf (bool? in; bool! out[N]; power supply)
{
{ N >= 0 : "sigbuf: parameter error" };
{ N <= 128 : "sigbuf: parameter error, N too big" };
/* -- just use in sized driver here -- */
[ N <= 4 ->
BUF_X1 buf1 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 5 & N <= 7 ->
BUF_X2 buf2 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 8 & N <= 10 ->
BUF_X3 buf3 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 11 & N <= 14 ->
BUF_X4 buf4 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 15 & N <= 18 ->
BUF_X6 buf6 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 19 & N <= 29 ->
BUF_X8 buf8 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 30 & N <= 48->
BUF_X12 buf12 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 49 & N <= 64 ->
BUF_X16 buf16 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 65 & N <= 96 ->
BUF_X24 buf24 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
[] N >= 97 & N <=128 ->
BUF_X32 buf32 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
// [] N >= 129 & N <=192 ->
// BUF_X48 buf48 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
// [] N >= 193 & N <= 256->
// BUF_X64 buf64 (.a = in, .y = out[0], .vdd = supply.vdd, .vss = supply.vss);
]
(i:1..N-1:out[i]=out[0];)
}
//Sigbuf in which there is only 1 output. Made for outputs that cannot have multiple wires.
export template<pint N>
defproc sigbuf_1output (bool? in; bool! out; power supply)
{
{ N >= 0 : "sigbuf: parameter error" };
{ N <= 43 : "sigbuf: parameter error, N too big" };
/* -- just use in sized driver here -- */
[ N <= 4 ->
BUF_X1 buf1 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 5 & N <= 7 ->
BUF_X2 buf2 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 8 & N <= 10 ->
BUF_X3 buf3 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 11 & N <= 14 ->
BUF_X4 buf4 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 15 & N <= 18 ->
BUF_X6 buf6 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 19 & N <= 29 ->
BUF_X8 buf8 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
[] N >= 30 & N <= 42 ->
BUF_X12 buf12 (.a = in, .y = out, .vdd = supply.vdd, .vss = supply.vss);
]
}
}}

280
test/prsim_plot.py
View File

@@ -1,280 +0,0 @@
#!/usr/bin/env python3
import sys
import glob
import re
import matplotlib.pyplot as plt
import numpy as np
def main(argv):
# Load file
assert len(argv) >= 2, "No arguments given. -h for help"
if argv[1] == "-h":
print("""Specify the path to prsim.out either by giving the full path,
or the folder name like 'buf_15'.
Use -include='regex' to specify signals to include (or -in).
Use -exclude='regex' to specify signals to exclude (or -ex).""")
return
file_path = argv[1]
if not ".out" in file_path:
file_path = f"./unit_tests/{file_path}/run/prsim.out"
assert len(glob.glob(file_path)) >= 1, "prsim.out file not found!"
print(f"Loading {file_path}")
f = open(file_path,'r').read()
# Start regexxing
entries = re.findall(r"\t *(\d+) ([^:]+) : (\d)( \[by.+\])?[\n\r]", f)
assert len(entries) >= 1, "Could not find signal info in prsim.out!"
# Check if user gave a colour specification
# default is Michele's atm
colour_undefined = (100,100,100)
colour_high = (98, 187, 93)
colour_low = (233, 115, 115)
for arg in argv:
r = re.findall(r'-c=[\"\']?(.+)[\"\']?', arg)
if len(r) >= 1:
if r[0] == "ole":
colour_undefined = (233, 115, 115)
colour_high = (98, 187, 93)
colour_low = (90, 111, 199)
elif r[0] == "og":
colour_undefined = (255,0,0)
colour_high = (252, 186, 3)
colour_low = (20, 184, 186)
elif r[0] == "michele":
colour_undefined = (100,100,100)
colour_high = (98, 187, 93)
colour_low = (233, 115, 115)
else:
raise Exception("Unknown colour given. I cba to code up general colours atm.")
# Check if start time given
t0 = None
for arg in argv:
r = re.findall(r'-t0=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by start time t0 = {r[0]}")
t0 = int[r[0]]
entries = [e for e in entries if int(e[0]) >= int(r[0])]
# Check if end time given
t1 = None
for arg in argv:
r = re.findall(r'-t1=(\d+)', arg)
if len(r) >= 1:
print(f"Filtering by end time t1 = {r[0]}")
t1 = int[r[0]]
entries = [e for e in entries if int(e[0]) <= int(r[0])]
# Check if user gave an include filter
include_given = False
include_re = None
for arg in argv:
r = re.findall(r'(-include|-in)=(.+)', arg)
if len(r) >= 1:
include_given = True
include_re = r[0][1]
# Check if user gave an exclude filter
exclude_given = False
exclude_re = None
for arg in argv:
r = re.findall(r'(-exclude|-ex)=(.+)', arg)
if len(r) >= 1:
exclude_given = True
exclude_re = r[0][1]
# Check if user gave "keep all times" flag
# This is so you can look at certain signals only
# without them all bunching up.
include_all_times = False
for arg in argv:
r = re.findall(r'(-alltimes?)', arg)
if len(r) >= 1:
include_all_times = True
# Check if user gave "nowarn" flag
plot_warn = True
for arg in argv:
r = re.findall(r'(-nowarn?)', arg)
if len(r) >= 1:
plot_warn = False
# Get list of all times (before filtering)
unique_times = np.unique([int(e[0]) for e in entries])
# assert not (exclude_given and include_given), "Can't give include and exclude re simultaneously."
if include_given: print(f"Including signals that match regex {include_re}")
if exclude_given: print(f"Excluding signals that match regex {exclude_re}")
if include_given:
entries = [e for e in entries if not re.search(include_re, e[1]) == None]
if exclude_given:
entries = [e for e in entries if re.search(exclude_re, e[1]) == None]
assert len(entries) >= 1, "No valid entries in prsim.out!"
num_times = unique_times.shape[0]
# Get list of all times (after filtering)
times = np.array([int(e[0]) for e in entries])
if not include_all_times: unique_times = np.unique(times)
num_times = unique_times.shape[0]
# Get list of all sigs
sigs = np.array([e[1] for e in entries])
unique_sigs = np.unique(sigs)
num_sigs = unique_sigs.shape[0]
print(f"Plotting signals:")
print(unique_sigs)
# Some functions to order everything nicely
# Should probably put these outside but whatever.
def time_to_index(time):
'''
Since times are random, need to convert them to an index.
'''
if not (int(time) in unique_times): return None
out = np.argwhere(unique_times == int(time))
return out[0][0]
def sig_to_index(sig):
'''
Handles signal name ordering.
Assume ordered like unique_sigs for now
'''
if not (sig in unique_sigs): return None
out = np.argwhere(unique_sigs == sig)
return out[0][0]
# Create matrix of signals over time and populate
signals_matrix = np.zeros((num_sigs, num_times), dtype = int)
for sig in unique_sigs:
entries_filtered = [e for e in entries if e[1] == sig]
# make sure sorted
entries_filtered = sorted(entries_filtered, key = lambda e: int(e[0]))
for e in entries_filtered:
val = int(e[2])
val = 2*val -1
signals_matrix[sig_to_index(sig),time_to_index(e[0]):] = val
# Plot
# Generate figure
# weird sizing is to try to keep "pixel" sizes approx const
fig = plt.figure(figsize = (num_times/3+0.2,num_sigs/3+0.2), dpi = 100)
image = np.zeros((num_sigs, num_times, 3), dtype = int)
image[signals_matrix == 0] = colour_undefined
image[signals_matrix == 1] = colour_high
image[signals_matrix == -1] = colour_low
plt.imshow(image)
ax = fig.gca()
ax.set_xlabel("Time")
# ax.set_ylabel("Signal")
ax.set_yticks([])
# Plot signal names
sig_repeat_period = 20
for sig in unique_sigs:
ax.text(-1, sig_to_index(sig), sig, ha = "right", va = "center", size = 10)
ax.text(num_times, sig_to_index(sig), sig, ha = "left", va = "center", size = 10)
for i in range(num_sigs-1):
ax.axhline(i+0.5, c = "white", lw = 2)
for i in range(num_times-1):
ax.axvline(i+0.5, c = "white", lw = 2)
ax.axis("off")
# Draw arrows
for e in entries:
# check if has a causal signal
by = re.findall(r"\[by (.+):=(\d)",e[3])
if len(by) == 0: continue
sig = e[1]
time = e[0]
t_index = time_to_index(time)
by_sig = by[0][0]
by_val = int(by[0][1])
t0,t1 = (t_index, t_index)
# The sig that caused the change might have been excluded from plotting
s0 = sig_to_index(sig)
if by_sig in unique_sigs:
s1 = sig_to_index(by_sig)
else:
s1 = s0
if by_val == 1:
plt.arrow(t0, s1, 0, s0-s1 + 0.2*np.sign(s0-s1), head_width = 0.5, width = 0.2,
ec = "none", lw = 0, fc = "black", length_includes_head = True)
else:
plt.arrow(t0, s1, 0, s0-s1 + 0.2*np.sign(s0-s1), head_width = 0, width = 0.2,
ec = "none", lw = 0, fc = "black", length_includes_head = True)
plt.scatter((t0),(s0), c = "black", s = 40)
# Write times on x axis
for time in unique_times:
ax.text(time_to_index(time), num_sigs, time, ha = "center", va = "top", size = 10, rotation = 90)
# Find and plot wrong Assert statements
asserts = re.findall(r"\t *(\d+) .*\n(WRONG ASSERT|WARNING):\t?(.+)", f)
if len(asserts): print("Warnings found!")
for a in asserts:
print(a)
time = int(a[0])
if not time in unique_times:
try:
time = unique_times[np.argwhere((unique_times-time) < 0)[-1]]
except:
print(f"Couldn't find an appropriate time for warning {a}")
continue
index = time_to_index(time)
if plot_warn:
ax.axvline(index+0.5, c = "red", lw = 2)
ax.text(index+0.5, -1, a[2], rotation = 90, ha = "center", va = "bottom", c = "red")
# Find echoed statements of the form "[digits] text"
echoes = re.findall(r"\t *(\d+) [^\t]*\n(\[\d*\].+)", f)
for a in echoes:
time = int(a[0])
if not time in unique_times:
try:
time = unique_times[np.argwhere((unique_times-time) < 0)[-1]]
except:
print(f"Couldn't find an appropriate time for echo {a}")
continue
index = time_to_index(time)
c = "xkcd:bright purple"
ax.axvline(index+0.5, c = c, lw = 2)
ax.text(index+0.5, -1, a[1], rotation = 90, ha = "center", va = "bottom", c = c)
output_type = ".pdf"
for arg in argv:
if arg == "-png": output_type = ".png"
file_out_path = file_path.replace(".out",output_type)
plt.savefig(file_out_path, bbox_inches = "tight")
if __name__ == "__main__":
# print(sys.argv[0:])
main(sys.argv)
# main(sys.argv[1:])

159
test/repeat_unit.sh
View File

@@ -1,94 +1,85 @@
#!/bin/sh
# repeatedly run prsim on one unit_test's PRs
fail=0
faildirs=""
proc=""
bold=$(tput bold)
normal=$(tput sgr0)
und=$(tput smul)
i=${unit}
proc="$i<>"
faildirs=""
failed=0
iteration=0
numberofruns=100
#
# run_test name [option]
#
run_test () {
echo "Testing ${bold}$1 ${normal} for $2 random delay runs"
# clear run directory
if [ -d $1/run ]; then
rm -rf $1/run
fi
mkdir $1/run
cp init.prs $1/run/test.prs
if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
echo "random_seed $2" > $1/run/prsim.in
cat init_qdi.prsim $1/test.prsim >> $1/run/prsim.in
cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
echo "${bold}*** simulation failed seed: $2 ***${normal}"
faildirs="${faildirs} ${1}-sim($2)"
failed=1
echo
fi
else
echo "${bold}*** circuit construction failed ***${normal}"
faildirs="${faildirs} ${1}-ckt"
failed=1
echo
fi
}
if [ ! $(command -v aflat) ]; then #&& ! command -v prsim ]; then
echo "${bold}Error:${bold} aflat & prsim necessary for tests."
exit 1
fi
if [ ! -d "unit_tests" ];
then
echo "${bold}Error:${bold} no unit_tests directory."
exit 1
fi
echo ""
echo "${bold}******************************************"
echo "* ${i} repetitions , show warnings=${warning}*"
echo "******************************************${normal}"
cd "unit_tests"
echo "${bold}... checking aflat${normal}"
# run all test except single one is specified
if [ ! -z $3 ]; then
iteration=$3
fi
if [ ! -z $2 ]; then
numberofruns=$2
fi
if [ -z $1 ]; then
for i in *
do
if [ -d $i -a -f $i/test.act ]; then
while [ $iteration -lt $numberofruns ]
do
run_test $iteration
iteration=$iteration+1
done
fi
done
else
while [ $iteration -lt $numberofruns ]
do
run_test $1 $iteration
iteration=$((iteration+1))
done
# check aflat
if ($ACT_HOME/bin/aflat "$i/test_final.act" > "$i/test.prs");
then
echo "${bold}... aflat complete, checking in prsim${normal}"
# run prsim on prs
(($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test.prsim") > "$i/prsim.out");
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found")
then
echo "FAILED in first prsim"
else
# show warnings setting
if [ "${warning}" = "1" ];
then
echo "${bold}Exit on prsim warnings turned ON${normal}"
else
echo "${bold}Exit on prsim warnings turned OFF${normal}"
fi
echo ""
# begin prsim test loop
has_failed=0
iter=0
echo "${bold}using random_seed${normal}"
echo "\nusing random_seed" >> "$i/prsim.out"
while [ has_failed=0 ]
do
# write prsim test file with random seed appended to top of file
(echo "random_seed $iter \nrandom" > "$i/test_rand.prsim");
(cat "$i/test.prsim" >> "$i/test_rand.prsim");
(echo "\nTEST $iter\n" >> "$i/prsim.out");
# validate prsim output
if (($ACT_HOME/bin/prsim "$i/test.prs" < "$i/test_rand.prsim") >> "$i/prsim.out");
then
if [ "${warning}" = "1" ];
then
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found" -e "WARNING:");
then
echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
has_failed=1
exit 0
else
echo "==> passed test #${iter}"
iter=$(($iter + 1))
fi
else
if (cat "$i/prsim.out" | grep -e "WRONG ASSERT" -e "FATAL" -e "not found");
then
echo "${bold}==> test #${iter} ${und}FAILED in prsim${normal}"
has_failed=1
exit 0
else
echo "==> passed test #${iter}"
iter=$(($iter + 1))
fi
fi
else
has_failed=1
exit 0
fi
done
(cd ".."; pwd);
exit 1
fi
else
echo "FAILED in aflat conversion"
fi
if [ $failed -eq 1 ]; then
echo ""
echo "${bold}*********************************"
echo "* FAILED DIRECTORIES:${normal}$faildirs ${bold}*"
echo "*********************************${normal}"
fi
exit $failed

6
test/run.sh
View File

@@ -22,8 +22,7 @@ run_test () {
mkdir $1/run
cp init.prs $1/run/test.prs
if aflat -ref=1 $1/test.act >> $1/run/test.prs; then
cat init_qdi.prsim $1/test.prsim > $1/run/prsim.in
cat $1/run/prsim.in | prsim -r $1/run/test.prs > $1/run/prsim.out
cat init_qdi.prsim $1/test.prsim | prsim -r $1/run/test.prs > $1/run/prsim.out
if egrep '(WRONG|WARNING|Node)' $1/run/prsim.out >/dev/null; then
echo "${bold}*** simulation failed ***${normal}"
faildirs="${faildirs} ${1}-sim"
@@ -38,7 +37,8 @@ run_test () {
fi
}
if [ ! $(command -v aflat) ]; then #&& ! command -v prsim ]; then
if [ ! ( command -v aflat && command -v prsim ) ];
then
echo "${bold}Error:${bold} aflat & prsim necessary for tests."
exit 1
fi

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118
test/unit_tests/andtree_15/run/prsim.out
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@@ -1,118 +0,0 @@
t.in[0] t.at.tmp[22] t.in[5] t.in[2] t.at.tmp[15] t.in[3] t.at.tmp[23] t.at.C2Els[0]._y t.in[7] t.in[6] t.at.C2Els[3]._y t.in[4] t.at.C3Els[0]._y t.in[12] t.out t.at.tmp[21] t.at.C2Els[6]._y t.in[11] t.at.tmp[17] t.in[14] t.in[1] t.in[10] t.in[9] t.at.C2Els[5]._y t.at.tmp[19] t.at.tmp[20] t.at.tmp[24] t.in[13] t.at.tmp[16] t.at.C2Els[4]._y t.in[8] t.at.tmp[18] t.at.C2Els[2]._y t.at.C3Els[2]._y t.at.C2Els[1]._y t.at.C2Els[7]._y t.at.C3Els[1]._y
0
1
0 t.in[0] : 0
0 t.in[14] : 0
0 t.in[2] : 0
0 t.in[6] : 0
0 t.in[13] : 0
0 t.in[5] : 0
0 t.in[12] : 0
0 t.in[11] : 0
0 t.in[1] : 0
0 t.in[4] : 0
0 t.in[10] : 0
0 t.in[9] : 0
0 t.in[3] : 0
0 t.in[8] : 0
0 t.in[7] : 0
1 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
2 t.at.C2Els[3]._y : 1 [by t.in[6]:=0]
114 t.at.C2Els[4]._y : 1 [by t.in[9]:=0]
153 t.at.tmp[19] : 0 [by t.at.C2Els[4]._y:=1]
168 t.at.C3Els[1]._y : 1 [by t.at.tmp[19]:=0]
659 t.at.tmp[24] : 0 [by t.at.C3Els[1]._y:=1]
672 t.at.C3Els[2]._y : 1 [by t.at.tmp[24]:=0]
712 t.out : 0 [by t.at.C3Els[2]._y:=1]
1137 t.at.C2Els[5]._y : 1 [by t.in[11]:=0]
1552 t.at.tmp[20] : 0 [by t.at.C2Els[5]._y:=1]
1728 t.at.tmp[18] : 0 [by t.at.C2Els[3]._y:=1]
1748 t.at.C2Els[7]._y : 1 [by t.at.tmp[18]:=0]
4753 t.at.C2Els[2]._y : 1 [by t.in[5]:=0]
4800 t.at.tmp[17] : 0 [by t.at.C2Els[2]._y:=1]
7092 t.at.C3Els[0]._y : 1 [by t.in[14]:=0]
7108 t.at.tmp[21] : 0 [by t.at.C3Els[0]._y:=1]
7809 t.at.tmp[23] : 0 [by t.at.C2Els[7]._y:=1]
10467 t.at.C2Els[1]._y : 1 [by t.in[2]:=0]
54565 t.at.tmp[16] : 0 [by t.at.C2Els[1]._y:=1]
65367 t.at.tmp[15] : 0 [by t.at.C2Els[0]._y:=1]
68289 t.at.C2Els[6]._y : 1 [by t.at.tmp[16]:=0]
68293 t.at.tmp[22] : 0 [by t.at.C2Els[6]._y:=1]
[] setting some bits high
68293 t.in[0] : 1
68293 t.in[11] : 1
68293 t.in[10] : 1
68293 t.in[9] : 1
68293 t.in[2] : 1
68293 t.in[8] : 1
68293 t.in[7] : 1
68293 t.in[6] : 1
68293 t.in[5] : 1
68293 t.in[1] : 1
68293 t.in[4] : 1
68293 t.in[3] : 1
68308 t.at.C2Els[4]._y : 0 [by t.in[8]:=1]
68348 t.at.C2Els[2]._y : 0 [by t.in[4]:=1]
77422 t.at.C2Els[5]._y : 0 [by t.in[10]:=1]
82197 t.at.tmp[17] : 1 [by t.at.C2Els[2]._y:=0]
98088 t.at.tmp[19] : 1 [by t.at.C2Els[4]._y:=0]
102234 t.at.tmp[20] : 1 [by t.at.C2Els[5]._y:=0]
105224 t.at.C2Els[0]._y : 0 [by t.in[1]:=1]
111541 t.at.C2Els[3]._y : 0 [by t.in[6]:=1]
111963 t.at.tmp[18] : 1 [by t.at.C2Els[3]._y:=0]
119567 t.at.tmp[15] : 1 [by t.at.C2Els[0]._y:=0]
119946 t.at.C2Els[1]._y : 0 [by t.in[3]:=1]
119947 t.at.tmp[16] : 1 [by t.at.C2Els[1]._y:=0]
119948 t.at.C2Els[6]._y : 0 [by t.at.tmp[16]:=1]
140153 t.at.tmp[22] : 1 [by t.at.C2Els[6]._y:=0]
160677 t.at.C2Els[7]._y : 0 [by t.at.tmp[18]:=1]
160959 t.at.tmp[23] : 1 [by t.at.C2Els[7]._y:=0]
[] setting all bits high
160959 t.in[12] : 1
160959 t.in[14] : 1
160959 t.in[13] : 1
161727 t.at.C3Els[0]._y : 0 [by t.in[13]:=1]
161730 t.at.tmp[21] : 1 [by t.at.C3Els[0]._y:=0]
184171 t.at.C3Els[1]._y : 0 [by t.at.tmp[21]:=1]
184722 t.at.tmp[24] : 1 [by t.at.C3Els[1]._y:=0]
185793 t.at.C3Els[2]._y : 0 [by t.at.tmp[24]:=1]
186747 t.out : 1 [by t.at.C3Els[2]._y:=0]
[] setting some low
186747 t.in[10] : 0
187828 t.at.C2Els[5]._y : 1 [by t.in[10]:=0]
242298 t.at.tmp[20] : 0 [by t.at.C2Els[5]._y:=1]
243280 t.at.C3Els[1]._y : 1 [by t.at.tmp[20]:=0]
243298 t.at.tmp[24] : 0 [by t.at.C3Els[1]._y:=1]
247311 t.at.C3Els[2]._y : 1 [by t.at.tmp[24]:=0]
251314 t.out : 0 [by t.at.C3Els[2]._y:=1]
[] setting all low
251314 t.in[0] : 0
251314 t.in[14] : 0
251314 t.in[2] : 0
251314 t.in[6] : 0
251314 t.in[5] : 0
251314 t.in[13] : 0
251314 t.in[12] : 0
251314 t.in[1] : 0
251314 t.in[4] : 0
251314 t.in[11] : 0
251314 t.in[9] : 0
251314 t.in[3] : 0
251314 t.in[8] : 0
251314 t.in[7] : 0
251517 t.at.C2Els[2]._y : 1 [by t.in[5]:=0]
251656 t.at.tmp[17] : 0 [by t.at.C2Els[2]._y:=1]
251816 t.at.C2Els[3]._y : 1 [by t.in[6]:=0]
251885 t.at.tmp[18] : 0 [by t.at.C2Els[3]._y:=1]
253168 t.at.C2Els[4]._y : 1 [by t.in[9]:=0]
253179 t.at.tmp[19] : 0 [by t.at.C2Els[4]._y:=1]
256074 t.at.C2Els[1]._y : 1 [by t.in[2]:=0]
272898 t.at.C3Els[0]._y : 1 [by t.in[14]:=0]
273102 t.at.tmp[21] : 0 [by t.at.C3Els[0]._y:=1]
288002 t.at.C2Els[7]._y : 1 [by t.at.tmp[17]:=0]
288017 t.at.tmp[23] : 0 [by t.at.C2Els[7]._y:=1]
296215 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
296216 t.at.tmp[15] : 0 [by t.at.C2Els[0]._y:=1]
296253 t.at.C2Els[6]._y : 1 [by t.at.tmp[15]:=0]
296992 t.at.tmp[22] : 0 [by t.at.C2Els[6]._y:=1]
307860 t.at.tmp[16] : 0 [by t.at.C2Els[1]._y:=1]

BIN
test/unit_tests/andtree_15/run/prsim.pdf
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139
test/unit_tests/andtree_15/run/test.prs
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@@ -1,139 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
"t.at.C2Els[2].a"&"t.at.C2Els[2].b"->"t.at.C2Els[2]._y"-
~("t.at.C2Els[2].a"&"t.at.C2Els[2].b")->"t.at.C2Els[2]._y"+
"t.at.C2Els[2]._y"->"t.at.C2Els[2].y"-
~("t.at.C2Els[2]._y")->"t.at.C2Els[2].y"+
"t.at.C2Els[3].a"&"t.at.C2Els[3].b"->"t.at.C2Els[3]._y"-
~("t.at.C2Els[3].a"&"t.at.C2Els[3].b")->"t.at.C2Els[3]._y"+
"t.at.C2Els[3]._y"->"t.at.C2Els[3].y"-
~("t.at.C2Els[3]._y")->"t.at.C2Els[3].y"+
"t.at.C2Els[4].a"&"t.at.C2Els[4].b"->"t.at.C2Els[4]._y"-
~("t.at.C2Els[4].a"&"t.at.C2Els[4].b")->"t.at.C2Els[4]._y"+
"t.at.C2Els[4]._y"->"t.at.C2Els[4].y"-
~("t.at.C2Els[4]._y")->"t.at.C2Els[4].y"+
"t.at.C2Els[5].a"&"t.at.C2Els[5].b"->"t.at.C2Els[5]._y"-
~("t.at.C2Els[5].a"&"t.at.C2Els[5].b")->"t.at.C2Els[5]._y"+
"t.at.C2Els[5]._y"->"t.at.C2Els[5].y"-
~("t.at.C2Els[5]._y")->"t.at.C2Els[5].y"+
"t.at.C2Els[6].a"&"t.at.C2Els[6].b"->"t.at.C2Els[6]._y"-
~("t.at.C2Els[6].a"&"t.at.C2Els[6].b")->"t.at.C2Els[6]._y"+
"t.at.C2Els[6]._y"->"t.at.C2Els[6].y"-
~("t.at.C2Els[6]._y")->"t.at.C2Els[6].y"+
"t.at.C2Els[7].a"&"t.at.C2Els[7].b"->"t.at.C2Els[7]._y"-
~("t.at.C2Els[7].a"&"t.at.C2Els[7].b")->"t.at.C2Els[7]._y"+
"t.at.C2Els[7]._y"->"t.at.C2Els[7].y"-
~("t.at.C2Els[7]._y")->"t.at.C2Els[7].y"+
"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
"t.at.C3Els[1].a"&"t.at.C3Els[1].b"&"t.at.C3Els[1].c"->"t.at.C3Els[1]._y"-
~("t.at.C3Els[1].a"&"t.at.C3Els[1].b"&"t.at.C3Els[1].c")->"t.at.C3Els[1]._y"+
"t.at.C3Els[1]._y"->"t.at.C3Els[1].y"-
~("t.at.C3Els[1]._y")->"t.at.C3Els[1].y"+
"t.at.C3Els[2].a"&"t.at.C3Els[2].b"&"t.at.C3Els[2].c"->"t.at.C3Els[2]._y"-
~("t.at.C3Els[2].a"&"t.at.C3Els[2].b"&"t.at.C3Els[2].c")->"t.at.C3Els[2]._y"+
"t.at.C3Els[2]._y"->"t.at.C3Els[2].y"-
~("t.at.C3Els[2]._y")->"t.at.C3Els[2].y"+
= "t.at.tmp[15]" "t.at.C2Els[6].a"
= "t.at.tmp[15]" "t.at.C2Els[0].y"
= "t.at.tmp[16]" "t.at.C2Els[6].b"
= "t.at.tmp[16]" "t.at.C2Els[1].y"
= "t.at.tmp[17]" "t.at.C2Els[7].a"
= "t.at.tmp[17]" "t.at.C2Els[2].y"
= "t.at.tmp[18]" "t.at.C2Els[7].b"
= "t.at.tmp[18]" "t.at.C2Els[3].y"
= "t.at.tmp[19]" "t.at.C3Els[1].a"
= "t.at.tmp[19]" "t.at.C2Els[4].y"
= "t.at.tmp[20]" "t.at.C3Els[1].b"
= "t.at.tmp[20]" "t.at.C2Els[5].y"
= "t.at.tmp[21]" "t.at.C3Els[1].c"
= "t.at.tmp[21]" "t.at.C3Els[0].y"
= "t.at.tmp[22]" "t.at.C3Els[2].a"
= "t.at.tmp[22]" "t.at.C2Els[6].y"
= "t.at.tmp[23]" "t.at.C3Els[2].b"
= "t.at.tmp[23]" "t.at.C2Els[7].y"
= "t.at.tmp[24]" "t.at.C3Els[2].c"
= "t.at.tmp[24]" "t.at.C3Els[1].y"
= "t.at.supply.vdd" "t.at.C3Els[2].vdd"
= "t.at.supply.vdd" "t.at.C3Els[1].vdd"
= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
= "t.at.supply.vdd" "t.at.C2Els[7].vdd"
= "t.at.supply.vdd" "t.at.C2Els[6].vdd"
= "t.at.supply.vdd" "t.at.C2Els[5].vdd"
= "t.at.supply.vdd" "t.at.C2Els[4].vdd"
= "t.at.supply.vdd" "t.at.C2Els[3].vdd"
= "t.at.supply.vdd" "t.at.C2Els[2].vdd"
= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
= "t.at.supply.vss" "t.at.C3Els[2].vss"
= "t.at.supply.vss" "t.at.C3Els[1].vss"
= "t.at.supply.vss" "t.at.C3Els[0].vss"
= "t.at.supply.vss" "t.at.C2Els[7].vss"
= "t.at.supply.vss" "t.at.C2Els[6].vss"
= "t.at.supply.vss" "t.at.C2Els[5].vss"
= "t.at.supply.vss" "t.at.C2Els[4].vss"
= "t.at.supply.vss" "t.at.C2Els[3].vss"
= "t.at.supply.vss" "t.at.C2Els[2].vss"
= "t.at.supply.vss" "t.at.C2Els[1].vss"
= "t.at.supply.vss" "t.at.C2Els[0].vss"
= "t.at.in[0]" "t.at.C2Els[0].a"
= "t.at.in[0]" "t.at.tmp[0]"
= "t.at.in[1]" "t.at.C2Els[0].b"
= "t.at.in[1]" "t.at.tmp[1]"
= "t.at.in[2]" "t.at.C2Els[1].a"
= "t.at.in[2]" "t.at.tmp[2]"
= "t.at.in[3]" "t.at.C2Els[1].b"
= "t.at.in[3]" "t.at.tmp[3]"
= "t.at.in[4]" "t.at.C2Els[2].a"
= "t.at.in[4]" "t.at.tmp[4]"
= "t.at.in[5]" "t.at.C2Els[2].b"
= "t.at.in[5]" "t.at.tmp[5]"
= "t.at.in[6]" "t.at.C2Els[3].a"
= "t.at.in[6]" "t.at.tmp[6]"
= "t.at.in[7]" "t.at.C2Els[3].b"
= "t.at.in[7]" "t.at.tmp[7]"
= "t.at.in[8]" "t.at.C2Els[4].a"
= "t.at.in[8]" "t.at.tmp[8]"
= "t.at.in[9]" "t.at.C2Els[4].b"
= "t.at.in[9]" "t.at.tmp[9]"
= "t.at.in[10]" "t.at.C2Els[5].a"
= "t.at.in[10]" "t.at.tmp[10]"
= "t.at.in[11]" "t.at.C2Els[5].b"
= "t.at.in[11]" "t.at.tmp[11]"
= "t.at.in[12]" "t.at.C3Els[0].a"
= "t.at.in[12]" "t.at.tmp[12]"
= "t.at.in[13]" "t.at.C3Els[0].b"
= "t.at.in[13]" "t.at.tmp[13]"
= "t.at.in[14]" "t.at.C3Els[0].c"
= "t.at.in[14]" "t.at.tmp[14]"
= "t.at.out" "t.at.C3Els[2].y"
= "t.at.out" "t.at.tmp[25]"
= "Vdd" "t.at.supply.vdd"
= "GND" "t.at.supply.vss"
= "t.out" "t.at.out"
= "t.in[0]" "t.at.in[0]"
= "t.in[1]" "t.at.in[1]"
= "t.in[2]" "t.at.in[2]"
= "t.in[3]" "t.at.in[3]"
= "t.in[4]" "t.at.in[4]"
= "t.in[5]" "t.at.in[5]"
= "t.in[6]" "t.at.in[6]"
= "t.in[7]" "t.at.in[7]"
= "t.in[8]" "t.at.in[8]"
= "t.in[9]" "t.at.in[9]"
= "t.in[10]" "t.at.in[10]"
= "t.in[11]" "t.at.in[11]"
= "t.in[12]" "t.at.in[12]"
= "t.in[13]" "t.at.in[13]"
= "t.in[14]" "t.at.in[14]"

41
test/unit_tests/andtree_15/test.act
View File

@@ -1,41 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc andtree_15 (bool? in[15]; bool! out){
andtree<15> at(.in=in, .out=out);
at.supply.vss = GND;
at.supply.vdd = Vdd;
}
andtree_15 t;

110
test/unit_tests/andtree_15/test.prsim
View File

@@ -1,110 +0,0 @@
watchall
system "echo '0'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
set t.in[5] 0
set t.in[6] 0
set t.in[7] 0
set t.in[8] 0
set t.in[9] 0
set t.in[10] 0
set t.in[11] 0
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
system "echo '1'"
cycle
mode run
assert t.out 0
system "echo '[] setting some bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 1
set t.in[11] 1
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
cycle
assert t.out 0
system "echo '[] setting all bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 1
set t.in[11] 1
set t.in[12] 1
set t.in[13] 1
set t.in[14] 1
cycle
assert t.out 1
system "echo '[] setting some low'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
set t.in[3] 1
set t.in[4] 1
set t.in[5] 1
set t.in[6] 1
set t.in[7] 1
set t.in[8] 1
set t.in[9] 1
set t.in[10] 0
set t.in[11] 1
set t.in[12] 1
set t.in[13] 1
set t.in[14] 1
cycle
assert t.out 0
system "echo '[] setting all low'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
set t.in[5] 0
set t.in[6] 0
set t.in[7] 0
set t.in[8] 0
set t.in[9] 0
set t.in[10] 0
set t.in[11] 0
set t.in[12] 0
set t.in[13] 0
set t.in[14] 0
cycle
assert t.out 0

40
test/unit_tests/andtree_5/run/prsim.out
View File

@@ -1,40 +0,0 @@
t.in[0] t.in[2] t.at.tmp[5] t.in[3] t.at.C2Els[0]._y t.in[4] t.at.C3Els[0]._y t.at.tmp[6] t.in[1] t.out t.at.C2Els[1]._y
0
1
0 t.in[0] : 0
0 t.in[4] : 0
0 t.in[2] : 0
0 t.in[1] : 0
0 t.in[3] : 0
1 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
7092 t.at.C3Els[0]._y : 1 [by t.in[4]:=0]
7094 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]
10468 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
11847 t.at.C2Els[1]._y : 1 [by t.at.tmp[6]:=0]
12984 t.out : 0 [by t.at.C2Els[1]._y:=1]
[] setting some bits high
12984 t.in[0] : 1
12984 t.in[2] : 1
12984 t.in[1] : 1
13098 t.at.C2Els[0]._y : 0 [by t.in[1]:=1]
78464 t.at.tmp[5] : 1 [by t.at.C2Els[0]._y:=0]
[] setting all bits high
78464 t.in[3] : 1
78464 t.in[4] : 1
80190 t.at.C3Els[0]._y : 0 [by t.in[4]:=1]
80229 t.at.tmp[6] : 1 [by t.at.C3Els[0]._y:=0]
80244 t.at.C2Els[1]._y : 0 [by t.at.tmp[6]:=1]
80735 t.out : 1 [by t.at.C2Els[1]._y:=0]
[] setting some low
80735 t.in[0] : 0
80735 t.in[1] : 0
80748 t.at.C2Els[0]._y : 1 [by t.in[0]:=0]
80788 t.at.tmp[5] : 0 [by t.at.C2Els[0]._y:=1]
81203 t.at.C2Els[1]._y : 1 [by t.at.tmp[5]:=0]
81223 t.out : 0 [by t.at.C2Els[1]._y:=1]
[] setting all low
81223 t.in[2] : 0
81223 t.in[4] : 0
81223 t.in[3] : 0
87284 t.at.C3Els[0]._y : 1 [by t.in[2]:=0]
87331 t.at.tmp[6] : 0 [by t.at.C3Els[0]._y:=1]

BIN
test/unit_tests/andtree_5/run/prsim.pdf
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45
test/unit_tests/andtree_5/run/test.prs
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@@ -1,45 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"t.at.C2Els[0].a"&"t.at.C2Els[0].b"->"t.at.C2Els[0]._y"-
~("t.at.C2Els[0].a"&"t.at.C2Els[0].b")->"t.at.C2Els[0]._y"+
"t.at.C2Els[0]._y"->"t.at.C2Els[0].y"-
~("t.at.C2Els[0]._y")->"t.at.C2Els[0].y"+
"t.at.C2Els[1].a"&"t.at.C2Els[1].b"->"t.at.C2Els[1]._y"-
~("t.at.C2Els[1].a"&"t.at.C2Els[1].b")->"t.at.C2Els[1]._y"+
"t.at.C2Els[1]._y"->"t.at.C2Els[1].y"-
~("t.at.C2Els[1]._y")->"t.at.C2Els[1].y"+
"t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c"->"t.at.C3Els[0]._y"-
~("t.at.C3Els[0].a"&"t.at.C3Els[0].b"&"t.at.C3Els[0].c")->"t.at.C3Els[0]._y"+
"t.at.C3Els[0]._y"->"t.at.C3Els[0].y"-
~("t.at.C3Els[0]._y")->"t.at.C3Els[0].y"+
= "t.at.tmp[5]" "t.at.C2Els[1].a"
= "t.at.tmp[5]" "t.at.C2Els[0].y"
= "t.at.tmp[6]" "t.at.C2Els[1].b"
= "t.at.tmp[6]" "t.at.C3Els[0].y"
= "t.at.supply.vdd" "t.at.C3Els[0].vdd"
= "t.at.supply.vdd" "t.at.C2Els[1].vdd"
= "t.at.supply.vdd" "t.at.C2Els[0].vdd"
= "t.at.supply.vss" "t.at.C3Els[0].vss"
= "t.at.supply.vss" "t.at.C2Els[1].vss"
= "t.at.supply.vss" "t.at.C2Els[0].vss"
= "t.at.in[0]" "t.at.C2Els[0].a"
= "t.at.in[0]" "t.at.tmp[0]"
= "t.at.in[1]" "t.at.C2Els[0].b"
= "t.at.in[1]" "t.at.tmp[1]"
= "t.at.in[2]" "t.at.C3Els[0].a"
= "t.at.in[2]" "t.at.tmp[2]"
= "t.at.in[3]" "t.at.C3Els[0].b"
= "t.at.in[3]" "t.at.tmp[3]"
= "t.at.in[4]" "t.at.C3Els[0].c"
= "t.at.in[4]" "t.at.tmp[4]"
= "t.at.out" "t.at.C2Els[1].y"
= "t.at.out" "t.at.tmp[7]"
= "Vdd" "t.at.supply.vdd"
= "GND" "t.at.supply.vss"
= "t.out" "t.at.out"
= "t.in[0]" "t.at.in[0]"
= "t.in[1]" "t.at.in[1]"
= "t.in[2]" "t.at.in[2]"
= "t.in[3]" "t.at.in[3]"
= "t.in[4]" "t.at.in[4]"

41
test/unit_tests/andtree_5/test.act
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@@ -1,41 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc andtree_5 (bool? in[5]; bool! out){
andtree<5> at(.in=in, .out=out);
at.supply.vss = GND;
at.supply.vdd = Vdd;
}
andtree_5 t;

50
test/unit_tests/andtree_5/test.prsim
View File

@@ -1,50 +0,0 @@
watchall
system "echo '0'"
set t.in[0] 0
set t.in[1] 0
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
system "echo '1'"
cycle
mode run
assert t.out 0
system "echo '[] setting some bits high'"
set t.in[0] 1
set t.in[1] 1
set t.in[2] 1
cycle
assert t.out 0
system "echo '[] setting all bits high'"
set t.in[3] 1
set t.in[4] 1
cycle
assert t.out 1
system "echo '[] setting some low'"
set t.in[0] 0
set t.in[1] 0
cycle
assert t.out 0
system "echo '[] setting all low'"
set t.in[2] 0
set t.in[3] 0
set t.in[4] 0
cycle
assert t.out 0

1878
test/unit_tests/append_5_3_2/run/prsim.out
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test/unit_tests/append_5_3_2/run/prsim.pdf
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6163
test/unit_tests/append_5_3_2/run/test.prs
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53
test/unit_tests/append_5_3_2/test.act
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@@ -1,53 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc append_5_3_2(avMx1of2<5> in; avMx1of2<8> out)
{
bool _reset_B;
prs {
Reset => _reset_B-
}
fifo<5,4> fifo_pre(.in = in, .reset_B = _reset_B);
append<5,3,3> app(.in = fifo_pre.out);
fifo<5+3,4> fifo_post(.in = app.out, .out = out, .reset_B = _reset_B);
app.supply.vdd = Vdd;
app.supply.vss = GND;
fifo_pre.supply.vdd = Vdd;
fifo_pre.supply.vss = GND;
fifo_post.supply.vdd = Vdd;
fifo_post.supply.vss = GND;
}
append_5_3_2 b;

78
test/unit_tests/append_5_3_2/test.prsim
View File

@@ -1,78 +0,0 @@
watchall
set b.out.a 0
set b.out.v 0
set Reset 0
set-qdi-channel-neutral "b.in" 5
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
status X
assert-qdi-channel-neutral "b.out" 8
assert b.in.a 0
assert b.in.v 0
system "echo '[] sending in a 31'"
set-qdi-channel-valid "b.in" 5 31
cycle
assert-qdi-channel-valid "b.out" 8 127
assert b.in.a 1
assert b.in.v 1
system "echo '[] removing input'"
set-qdi-channel-neutral "b.in" 5
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] sending in a 0'"
set-qdi-channel-valid "b.in" 5 0
cycle
# assert-qdi-channel-valid "b.out" 8 96
assert b.in.a 1
assert b.in.v 1
system "echo '[] removing input'"
set-qdi-channel-neutral "b.in" 5
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] receiving out ack/val'"
set b.out.a 1
set b.out.v 1
cycle
assert-qdi-channel-neutral "b.out" 8
system "echo '[] removing out ack/val'"
set b.out.a 0
set b.out.v 0
cycle
assert-qdi-channel-valid "b.out" 8 96
system "echo '[] receiving out ack/val'"
set b.out.a 1
set b.out.v 1
cycle
assert-qdi-channel-neutral "b.out" 8
system "echo '[] removing out ack/val'"
set b.out.a 0
set b.out.v 0
cycle
assert-qdi-channel-neutral "b.out" 8

39
test/unit_tests/arbiter/run/prsim.out
View File

@@ -1,39 +0,0 @@
a._v a.a a.u a.v a._u a.b
reset done
0 a.a : 0
0 a.b : 0
1 a._u : 1 [by a.a:=0]
7092 a._v : 1 [by a.b:=0]
7094 a.v : 0 [by a._v:=1]
10468 a.u : 0 [by a._u:=1]
step 1.1 finished
10468 a.a : 1
10468 a.b : 1
15221 a._u : 0 [by a.a:=1]
15335 a.u : 1 [by a._u:=0]
step 1.2 finished
15335 a.a : 0
15335 a.b : 0
80701 a._u : 1 [by a.a:=0]
82427 a.u : 0 [by a._u:=1]
step 2.1 finished
82427 a.a : 1
82427 a.b : 1
82466 a._u : 0 [by a.a:=1]
82957 a.u : 1 [by a._u:=0]
step 2.2 finished
82957 a.a : 0
82957 a.b : 0
82970 a._u : 1 [by a.a:=0]
83010 a.u : 0 [by a._u:=1]
step 3.1 finished
83010 a.b : 1
83425 a._v : 0 [by a.b:=1]
83445 a.v : 1 [by a._v:=0]
step 3.2 finished

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3
test/unit_tests/arbiter/run/test.prs
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@@ -1,3 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"

18
test/unit_tests/arbiter/test.act
View File

@@ -1,18 +0,0 @@
defproc arbiter (bool a, b, u, v)
{
bool _u, _v;
prs {
[keeper=0] a & _v -> _u-
[keeper=0] ~a | ~_v -> _u+
[keeper=0] b & _u -> _v-
[keeper=0] ~b | ~_u -> _v+
[keeper=0] _u => u-
[keeper=0] _v => v-
}
spec {
mk_excllo(_u, _v)
}
}
arbiter a;

39
test/unit_tests/arbiter/test.prsim
View File

@@ -1,39 +0,0 @@
watchall
cycle
system "echo 'reset done'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 1.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 1.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 2.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 2.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 3.1 finished'"
set a.a 0
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 3.2 finished'"

39
test/unit_tests/arbiter_2/run/prsim.out
View File

@@ -1,39 +0,0 @@
a._v a.a a.u a.v a._u a.b
reset done
0 a.a : 0
0 a.b : 0
1 a._u : 1 [by a.a:=0]
7092 a._v : 1 [by a.b:=0]
7094 a.v : 0 [by a._v:=1]
10468 a.u : 0 [by a._u:=1]
step 1.1 finished
10468 a.a : 1
10468 a.b : 1
15221 a._u : 0 [by a.a:=1]
15335 a.u : 1 [by a._u:=0]
step 1.2 finished
15335 a.a : 0
15335 a.b : 0
80701 a._u : 1 [by a.a:=0]
82427 a.u : 0 [by a._u:=1]
step 2.1 finished
82427 a.a : 1
82427 a.b : 1
82466 a._u : 0 [by a.a:=1]
82957 a.u : 1 [by a._u:=0]
step 2.2 finished
82957 a.a : 0
82957 a.b : 0
82970 a._u : 1 [by a.a:=0]
83010 a.u : 0 [by a._u:=1]
step 3.1 finished
83010 a.b : 1
83425 a._v : 0 [by a.b:=1]
83445 a.v : 1 [by a._v:=0]
step 3.2 finished

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12
test/unit_tests/arbiter_2/run/test.prs
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@@ -1,12 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"a.a"&"a._v"->"a._u"-
~"a.a"|~"a._v"->"a._u"+
"a.b"&"a._u"->"a._v"-
~"a.b"|~"a._u"->"a._v"+
"a._u"->"a.u"-
~("a._u")->"a.u"+
"a._v"->"a.v"-
~("a._v")->"a.v"+
mk_excllo("a._u","a._v")

18
test/unit_tests/arbiter_2/test.act
View File

@@ -1,18 +0,0 @@
defproc arbiter (bool a, b, u, v)
{
bool _u, _v;
prs {
[keeper=0] a & _v -> _u-
[keeper=0] ~a | ~_v -> _u+
[keeper=0] b & _u -> _v-
[keeper=0] ~b | ~_u -> _v+
[keeper=0] _u => u-
[keeper=0] _v => v-
}
spec {
mk_excllo(_u, _v)
}
}
arbiter a;

39
test/unit_tests/arbiter_2/test.prsim
View File

@@ -1,39 +0,0 @@
watchall
cycle
system "echo 'reset done'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 1.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 1.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 2.1 finished'"
set a.a 1
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 2.2 finished'"
set a.a 0
set a.b 0
advance 1000000
status X
mode run
system "echo 'step 3.1 finished'"
set a.a 0
set a.b 1
advance 1000000
status X
mode run
system "echo 'step 3.2 finished'"

357
test/unit_tests/arbiter_handshake_adv/run/prsim.out
View File

@@ -1,357 +0,0 @@
t.fifo_in1.fifo_element[2].in.r t.fifo_in1.fifo_element[1]._en t.in1.r t.in2.r t.fifo_in2.fifo_element[3].in.r t.out.r t._out1.r t.fifo_in2.fifo_element[3].inack_ctl._y t._out1.a t.arb._y1_arb t.fifo_in2.fifo_element[1].in.a t.fifo_in1.fifo_element[2].in.a t.fifo_in1.fifo_element[3]._out_a_B t.fifo_in1.fifo_element[1].in.r t.in2.a t.fifo_in2.fifo_element[3].in.a t._out2.a t.fifo_in2.fifo_element[1].in.r t.fifo_in1.fifo_element[3]._en t.fifo_in1.fifo_element[0].buf_func._y t.fifo_in2.fifo_element[0].inack_ctl._y t.fifo_in1.fifo_element[3].in.r t.fifo_in2.fifo_element[2].in.a t.fifo_in2.fifo_element[1]._out_a_B t.fifo_in2.fifo_element[3]._out_a_B t.fifo_in2.fifo_element[2].inack_ctl._y t.fifo_in2.fifo_element[0]._en t.fifo_in1.fifo_element[2]._en t._out2.r t.fifo_in1.fifo_element[1].in.a t.in1.a t.arb.ack_cell1._y t.fifo_in1.fifo_element[2].buf_func._y t.fifo_in1.fifo_element[0]._en t.fifo_in2.fifo_element[0]._out_a_B t.fifo_in1.fifo_element[2].inack_ctl._y t.fifo_in2.fifo_element[2]._out_a_B t.fifo_in1.fifo_element[1]._out_a_B t.fifo_in2.fifo_element[3]._en t.fifo_in2.fifo_element[1].buf_func._y t.fifo_in1.fifo_element[0].inack_ctl._y t.arb.or_cell._y t.arb.arbiter._y1 t.arb._y2_arb t.fifo_in1.fifo_element[1].inack_ctl._y t.fifo_in1.fifo_element[0]._out_a_B t.fifo_in2.fifo_element[1]._en t.fifo_in2.fifo_element[2]._en t.fifo_in2.fifo_element[0].buf_func._y t.fifo_in2.fifo_element[3].buf_func._y t.fifo_in1.fifo_element[2]._out_a_B t.fifo_in1.fifo_element[3].in.a t.fifo_in2.fifo_element[2].buf_func._y t.arb.arbiter._y2 t.fifo_in1.fifo_element[3].inack_ctl._y t.fifo_in2.fifo_element[2].in.r t.fifo_in1.fifo_element[1].buf_func._y t.fifo_in2.fifo_element[1].inack_ctl._y t.out.a t.fifo_in1.fifo_element[3].buf_func._y t.arb.ack_cell2._y
[0] code starts
77100 t.in1.r : 0
77100 Reset : 0
77100 t.out.a : 0
77100 t.in2.r : 0
114031 t.fifo_in1.reset_buf._y : 1 [by Reset:=0]
114086 t.fifo_in1._reset_BX : 0 [by t.fifo_in1.reset_buf._y:=1]
120348 t.fifo_in2.reset_buf._y : 1 [by Reset:=0]
150128 t.fifo_in2._reset_BX : 0 [by t.fifo_in2.reset_buf._y:=1]
163977 t.fifo_in2.reset_bufarray.buf1._y : 1 [by t.fifo_in2._reset_BX:=0]
165739 t.fifo_in1.reset_bufarray.buf1._y : 1 [by t.fifo_in1._reset_BX:=0]
180082 t.fifo_in1._reset_BXX[0] : 0 [by t.fifo_in1.reset_bufarray.buf1._y:=1]
180083 t.fifo_in1.fifo_element[0].reset_buf._y : 1 [by t.fifo_in1._reset_BXX[0]:=0]
180083 t.fifo_in1.fifo_element[3].reset_buf._y : 1 [by t.fifo_in1._reset_BXX[0]:=0]
180365 t.fifo_in1.fifo_element[3]._reset_BX : 0 [by t.fifo_in1.fifo_element[3].reset_buf._y:=1]
180368 t.fifo_in1.fifo_element[3].inack_ctl._y : 1 [by t.fifo_in1.fifo_element[3]._reset_BX:=0]
180504 t.fifo_in1.fifo_element[2].reset_buf._y : 1 [by t.fifo_in1._reset_BXX[0]:=0]
181055 t.fifo_in1.fifo_element[2]._reset_BX : 0 [by t.fifo_in1.fifo_element[2].reset_buf._y:=1]
181133 t.fifo_in1.fifo_element[3].buf_func._y : 1 [by t.fifo_in1.fifo_element[3]._reset_BX:=0]
182009 t.fifo_in1.fifo_element[2].inack_ctl._y : 1 [by t.fifo_in1.fifo_element[2]._reset_BX:=0]
182126 t.fifo_in1.fifo_element[2].buf_func._y : 1 [by t.fifo_in1.fifo_element[2]._reset_BX:=0]
182214 t._out1.r : 0 [by t.fifo_in1.fifo_element[3].buf_func._y:=1]
182232 t.arb.arbiter._y1 : 1 [by t._out1.r:=0]
183108 t.fifo_in1.fifo_element[3].in.r : 0 [by t.fifo_in1.fifo_element[2].buf_func._y:=1]
186245 t.arb._y1_arb : 0 [by t.arb.arbiter._y1:=1]
188789 t.fifo_in2._reset_BXX[0] : 0 [by t.fifo_in2.reset_bufarray.buf1._y:=1]
189291 t.fifo_in2.fifo_element[3].reset_buf._y : 1 [by t.fifo_in2._reset_BXX[0]:=0]
189494 t.fifo_in2.fifo_element[3]._reset_BX : 0 [by t.fifo_in2.fifo_element[3].reset_buf._y:=1]
189633 t.fifo_in2.fifo_element[3].inack_ctl._y : 1 [by t.fifo_in2.fifo_element[3]._reset_BX:=0]
190248 t.arb.ack_cell1._y : 1 [by t.arb._y1_arb:=0]
190317 t._out1.a : 0 [by t.arb.ack_cell1._y:=1]
190328 t.fifo_in1.fifo_element[3]._out_a_B : 1 [by t._out1.a:=0]
191348 t.fifo_in2.fifo_element[3].buf_func._y : 1 [by t.fifo_in2.fifo_element[3]._reset_BX:=0]
193549 t.fifo_in2.fifo_element[0].reset_buf._y : 1 [by t.fifo_in2._reset_BXX[0]:=0]
193753 t.fifo_in2.fifo_element[0]._reset_BX : 0 [by t.fifo_in2.fifo_element[0].reset_buf._y:=1]
193754 t.fifo_in2.fifo_element[0].inack_ctl._y : 1 [by t.fifo_in2.fifo_element[0]._reset_BX:=0]
193768 t.fifo_in2.fifo_element[0].buf_func._y : 1 [by t.fifo_in2.fifo_element[0]._reset_BX:=0]
193791 t.in2.a : 0 [by t.fifo_in2.fifo_element[0].inack_ctl._y:=1]
194507 t.fifo_in2.fifo_element[1].in.r : 0 [by t.fifo_in2.fifo_element[0].buf_func._y:=1]
194619 t.fifo_in2.fifo_element[0]._en : 1 [by t.fifo_in2.fifo_element[1].in.r:=0]
200288 t.fifo_in1.fifo_element[0]._reset_BX : 0 [by t.fifo_in1.fifo_element[0].reset_buf._y:=1]
200328 t.fifo_in1.fifo_element[0].inack_ctl._y : 1 [by t.fifo_in1.fifo_element[0]._reset_BX:=0]
200585 t.in1.a : 0 [by t.fifo_in1.fifo_element[0].inack_ctl._y:=1]
202809 t.fifo_in1.fifo_element[3].in.a : 0 [by t.fifo_in1.fifo_element[3].inack_ctl._y:=1]
202896 t.fifo_in1.fifo_element[3]._en : 1 [by t.fifo_in1.fifo_element[3].in.a:=0]
203103 t.fifo_in1.fifo_element[2]._out_a_B : 1 [by t.fifo_in1.fifo_element[3].in.a:=0]
210373 t.fifo_in2.fifo_element[1].reset_buf._y : 1 [by t.fifo_in2._reset_BXX[0]:=0]
210374 t.fifo_in2.fifo_element[1]._reset_BX : 0 [by t.fifo_in2.fifo_element[1].reset_buf._y:=1]
212180 t.fifo_in2.fifo_element[1].buf_func._y : 1 [by t.fifo_in2.fifo_element[1]._reset_BX:=0]
212381 t.fifo_in2.fifo_element[1].inack_ctl._y : 1 [by t.fifo_in2.fifo_element[1]._reset_BX:=0]
212971 t.fifo_in2.fifo_element[1].in.a : 0 [by t.fifo_in2.fifo_element[1].inack_ctl._y:=1]
213149 t.fifo_in2.fifo_element[0]._out_a_B : 1 [by t.fifo_in2.fifo_element[1].in.a:=0]
213389 t.fifo_in2.fifo_element[2].in.r : 0 [by t.fifo_in2.fifo_element[1].buf_func._y:=1]
214192 t.fifo_in2.fifo_element[1]._en : 1 [by t.fifo_in2.fifo_element[2].in.r:=0]
225979 t.fifo_in2.fifo_element[3].in.a : 0 [by t.fifo_in2.fifo_element[3].inack_ctl._y:=1]
226143 t.fifo_in2.fifo_element[2]._out_a_B : 1 [by t.fifo_in2.fifo_element[3].in.a:=0]
228796 t.fifo_in1.fifo_element[1].reset_buf._y : 1 [by t.fifo_in1._reset_BXX[0]:=0]
230991 t.fifo_in1.fifo_element[1]._reset_BX : 0 [by t.fifo_in1.fifo_element[1].reset_buf._y:=1]
231013 t.fifo_in1.fifo_element[1].buf_func._y : 1 [by t.fifo_in1.fifo_element[1]._reset_BX:=0]
231838 t.fifo_in1.fifo_element[1].inack_ctl._y : 1 [by t.fifo_in1.fifo_element[1]._reset_BX:=0]
231971 t.fifo_in1.fifo_element[1].in.a : 0 [by t.fifo_in1.fifo_element[1].inack_ctl._y:=1]
233690 t.fifo_in2.fifo_element[2].reset_buf._y : 1 [by t.fifo_in2._reset_BXX[0]:=0]
234049 t.fifo_in2.fifo_element[2]._reset_BX : 0 [by t.fifo_in2.fifo_element[2].reset_buf._y:=1]
234270 t.fifo_in2.fifo_element[2].inack_ctl._y : 1 [by t.fifo_in2.fifo_element[2]._reset_BX:=0]
234277 t.fifo_in2.fifo_element[2].in.a : 0 [by t.fifo_in2.fifo_element[2].inack_ctl._y:=1]
234307 t.fifo_in2.fifo_element[1]._out_a_B : 1 [by t.fifo_in2.fifo_element[2].in.a:=0]
236479 t.fifo_in1.fifo_element[2].in.a : 0 [by t.fifo_in1.fifo_element[2].inack_ctl._y:=1]
243134 t._out2.r : 0 [by t.fifo_in2.fifo_element[3].buf_func._y:=1]
243192 t.fifo_in1.fifo_element[2]._en : 1 [by t.fifo_in1.fifo_element[2].in.a:=0]
243225 t.fifo_in2.fifo_element[3]._en : 1 [by t._out2.r:=0]
245323 t.arb.arbiter._y2 : 1 [by t._out2.r:=0]
245330 t.arb._y2_arb : 0 [by t.arb.arbiter._y2:=1]
245436 t.arb.ack_cell2._y : 1 [by t.arb._y2_arb:=0]
245514 t._out2.a : 0 [by t.arb.ack_cell2._y:=1]
245789 t.fifo_in2.fifo_element[3]._out_a_B : 1 [by t._out2.a:=0]
247633 t.fifo_in1.fifo_element[0]._out_a_B : 1 [by t.fifo_in1.fifo_element[1].in.a:=0]
247800 t.fifo_in1.fifo_element[0].buf_func._y : 1 [by t.fifo_in1.fifo_element[0]._reset_BX:=0]
248117 t.arb.or_cell._y : 1 [by t.arb._y2_arb:=0]
248165 t.fifo_in2.fifo_element[2].buf_func._y : 1 [by t.fifo_in2.fifo_element[2]._reset_BX:=0]
248177 t.fifo_in2.fifo_element[3].in.r : 0 [by t.fifo_in2.fifo_element[2].buf_func._y:=1]
248572 t.out.r : 0 [by t.arb.or_cell._y:=1]
248581 t.fifo_in2.fifo_element[2]._en : 1 [by t.fifo_in2.fifo_element[3].in.r:=0]
261141 t.fifo_in1.fifo_element[2].in.r : 0 [by t.fifo_in1.fifo_element[1].buf_func._y:=1]
261153 t.fifo_in1.fifo_element[1]._en : 1 [by t.fifo_in1.fifo_element[2].in.r:=0]
266796 t.fifo_in1.fifo_element[1].in.r : 0 [by t.fifo_in1.fifo_element[0].buf_func._y:=1]
272712 t.fifo_in1.fifo_element[0]._en : 1 [by t.fifo_in1.fifo_element[1].in.r:=0]
293940 t.fifo_in1.fifo_element[1]._out_a_B : 1 [by t.fifo_in1.fifo_element[2].in.a:=0]
293940 Reset : 1
296839 t.fifo_in1.reset_buf._y : 0 [by Reset:=1]
298216 t.fifo_in2.reset_buf._y : 0 [by Reset:=1]
298218 t.fifo_in2._reset_BX : 1 [by t.fifo_in2.reset_buf._y:=0]
301134 t.fifo_in1._reset_BX : 1 [by t.fifo_in1.reset_buf._y:=0]
302383 t.fifo_in1.reset_bufarray.buf1._y : 0 [by t.fifo_in1._reset_BX:=1]
302753 t.fifo_in2.reset_bufarray.buf1._y : 0 [by t.fifo_in2._reset_BX:=1]
302919 t.fifo_in2._reset_BXX[0] : 1 [by t.fifo_in2.reset_bufarray.buf1._y:=0]
302994 t.fifo_in2.fifo_element[2].reset_buf._y : 0 [by t.fifo_in2._reset_BXX[0]:=1]
302996 t.fifo_in2.fifo_element[2]._reset_BX : 1 [by t.fifo_in2.fifo_element[2].reset_buf._y:=0]
303057 t.fifo_in2.fifo_element[0].reset_buf._y : 0 [by t.fifo_in2._reset_BXX[0]:=1]
303264 t.fifo_in2.fifo_element[1].reset_buf._y : 0 [by t.fifo_in2._reset_BXX[0]:=1]
303265 t.fifo_in2.fifo_element[1]._reset_BX : 1 [by t.fifo_in2.fifo_element[1].reset_buf._y:=0]
305882 t.fifo_in1._reset_BXX[0] : 1 [by t.fifo_in1.reset_bufarray.buf1._y:=0]
305893 t.fifo_in1.fifo_element[1].reset_buf._y : 0 [by t.fifo_in1._reset_BXX[0]:=1]
305949 t.fifo_in1.fifo_element[3].reset_buf._y : 0 [by t.fifo_in1._reset_BXX[0]:=1]
305965 t.fifo_in1.fifo_element[3]._reset_BX : 1 [by t.fifo_in1.fifo_element[3].reset_buf._y:=0]
306252 t.fifo_in1.fifo_element[0].reset_buf._y : 0 [by t.fifo_in1._reset_BXX[0]:=1]
306430 t.fifo_in1.fifo_element[2].reset_buf._y : 0 [by t.fifo_in1._reset_BXX[0]:=1]
306958 t.fifo_in1.fifo_element[2]._reset_BX : 1 [by t.fifo_in1.fifo_element[2].reset_buf._y:=0]
308182 t.fifo_in2.fifo_element[3].reset_buf._y : 0 [by t.fifo_in2._reset_BXX[0]:=1]
308534 t.fifo_in1.fifo_element[1]._reset_BX : 1 [by t.fifo_in1.fifo_element[1].reset_buf._y:=0]
310617 t.fifo_in2.fifo_element[3]._reset_BX : 1 [by t.fifo_in2.fifo_element[3].reset_buf._y:=0]
310814 t.fifo_in1.fifo_element[0]._reset_BX : 1 [by t.fifo_in1.fifo_element[0].reset_buf._y:=0]
346974 t.fifo_in2.fifo_element[0]._reset_BX : 1 [by t.fifo_in2.fifo_element[0].reset_buf._y:=0]
[1] reset done
----------------------------------------------------------------------------------------------------
346974 t.in1.r : 1
346974 t.in2.r : 1
370899 t.fifo_in2.fifo_element[0].buf_func._y : 0 [by t.in2.r:=1]
373854 t.fifo_in1.fifo_element[0].buf_func._y : 0 [by t.in1.r:=1]
373856 t.fifo_in1.fifo_element[1].in.r : 1 [by t.fifo_in1.fifo_element[0].buf_func._y:=0]
373859 t.fifo_in1.fifo_element[0].inack_ctl._y : 0 [by t.fifo_in1.fifo_element[1].in.r:=1]
373888 t.in1.a : 1 [by t.fifo_in1.fifo_element[0].inack_ctl._y:=0]
374205 t.fifo_in1.fifo_element[0]._en : 0 [by t.in1.a:=1]
383940 t.fifo_in2.fifo_element[1].in.r : 1 [by t.fifo_in2.fifo_element[0].buf_func._y:=0]
384093 t.fifo_in2.fifo_element[0].inack_ctl._y : 0 [by t.fifo_in2.fifo_element[1].in.r:=1]
384137 t.in2.a : 1 [by t.fifo_in2.fifo_element[0].inack_ctl._y:=0]
385541 t.fifo_in2.fifo_element[1].buf_func._y : 0 [by t.fifo_in2.fifo_element[1].in.r:=1]
386898 t.fifo_in2.fifo_element[0]._en : 0 [by t.in2.a:=1]
399224 t.fifo_in2.fifo_element[2].in.r : 1 [by t.fifo_in2.fifo_element[1].buf_func._y:=0]
399225 t.fifo_in2.fifo_element[2].buf_func._y : 0 [by t.fifo_in2.fifo_element[2].in.r:=1]
399247 t.fifo_in2.fifo_element[3].in.r : 1 [by t.fifo_in2.fifo_element[2].buf_func._y:=0]
399248 t.fifo_in2.fifo_element[3].buf_func._y : 0 [by t.fifo_in2.fifo_element[3].in.r:=1]
399441 t.fifo_in2.fifo_element[1].inack_ctl._y : 0 [by t.fifo_in2.fifo_element[2].in.r:=1]
399600 t.fifo_in2.fifo_element[1].in.a : 1 [by t.fifo_in2.fifo_element[1].inack_ctl._y:=0]
400828 t.fifo_in2.fifo_element[2].inack_ctl._y : 0 [by t.fifo_in2.fifo_element[3].in.r:=1]
400887 t.fifo_in2.fifo_element[0]._out_a_B : 0 [by t.fifo_in2.fifo_element[1].in.a:=1]
401032 t.fifo_in2.fifo_element[0].buf_func._y : 1 [by t.fifo_in2.fifo_element[0]._out_a_B:=0]
403060 t.fifo_in2.fifo_element[2].in.a : 1 [by t.fifo_in2.fifo_element[2].inack_ctl._y:=0]
403061 t.fifo_in2.fifo_element[1]._out_a_B : 0 [by t.fifo_in2.fifo_element[2].in.a:=1]
403864 t.fifo_in2.fifo_element[1].in.r : 0 [by t.fifo_in2.fifo_element[0].buf_func._y:=1]
408593 t._out2.r : 1 [by t.fifo_in2.fifo_element[3].buf_func._y:=0]
408755 t.fifo_in2.fifo_element[3].inack_ctl._y : 0 [by t._out2.r:=1]
409414 t.fifo_in2.fifo_element[2]._en : 0 [by t.fifo_in2.fifo_element[2].in.a:=1]
416124 t.fifo_in2.fifo_element[3].in.a : 1 [by t.fifo_in2.fifo_element[3].inack_ctl._y:=0]
416131 t.fifo_in2.fifo_element[2]._out_a_B : 0 [by t.fifo_in2.fifo_element[3].in.a:=1]
416138 t.fifo_in2.fifo_element[3]._en : 0 [by t.fifo_in2.fifo_element[3].in.a:=1]
416291 t.fifo_in2.fifo_element[2].buf_func._y : 1 [by t.fifo_in2.fifo_element[2]._out_a_B:=0]
419276 t.fifo_in2.fifo_element[1]._en : 0 [by t.fifo_in2.fifo_element[1].in.a:=1]
419277 t.fifo_in2.fifo_element[1].buf_func._y : 1 [by t.fifo_in2.fifo_element[1]._en:=0]
419277 t.fifo_in2.fifo_element[1].inack_ctl._y : 1 [by t.fifo_in2.fifo_element[1]._en:=0]
419278 t.fifo_in2.fifo_element[2].in.r : 0 [by t.fifo_in2.fifo_element[1].buf_func._y:=1]
419465 t.fifo_in2.fifo_element[2].inack_ctl._y : 1 [by t.fifo_in2.fifo_element[2].in.r:=0]
419466 t.fifo_in2.fifo_element[2].in.a : 0 [by t.fifo_in2.fifo_element[2].inack_ctl._y:=1]
421520 t.fifo_in2.fifo_element[1].in.a : 0 [by t.fifo_in2.fifo_element[1].inack_ctl._y:=1]
421521 t.fifo_in2.fifo_element[0]._out_a_B : 1 [by t.fifo_in2.fifo_element[1].in.a:=0]
423648 t.fifo_in2.fifo_element[1]._out_a_B : 1 [by t.fifo_in2.fifo_element[2].in.a:=0]
434814 t.fifo_in1.fifo_element[1].buf_func._y : 0 [by t.fifo_in1.fifo_element[1].in.r:=1]
435667 t.fifo_in1.fifo_element[2].in.r : 1 [by t.fifo_in1.fifo_element[1].buf_func._y:=0]
435672 t.fifo_in1.fifo_element[2].buf_func._y : 0 [by t.fifo_in1.fifo_element[2].in.r:=1]
435673 t.fifo_in1.fifo_element[3].in.r : 1 [by t.fifo_in1.fifo_element[2].buf_func._y:=0]
435690 t.fifo_in1.fifo_element[3].buf_func._y : 0 [by t.fifo_in1.fifo_element[3].in.r:=1]
436558 t.fifo_in1.fifo_element[1].inack_ctl._y : 0 [by t.fifo_in1.fifo_element[2].in.r:=1]
436561 t.fifo_in1.fifo_element[1].in.a : 1 [by t.fifo_in1.fifo_element[1].inack_ctl._y:=0]
437502 t.fifo_in1.fifo_element[1]._en : 0 [by t.fifo_in1.fifo_element[1].in.a:=1]
437848 t.fifo_in2.fifo_element[3].in.r : 0 [by t.fifo_in2.fifo_element[2].buf_func._y:=1]
437849 t.fifo_in2.fifo_element[3].inack_ctl._y : 1 [by t.fifo_in2.fifo_element[3].in.r:=0]
437890 t.fifo_in2.fifo_element[2]._en : 1 [by t.fifo_in2.fifo_element[3].in.r:=0]
438246 t.fifo_in1.fifo_element[2].inack_ctl._y : 0 [by t.fifo_in1.fifo_element[3].in.r:=1]
440666 t.fifo_in2.fifo_element[3].in.a : 0 [by t.fifo_in2.fifo_element[3].inack_ctl._y:=1]
440761 t.fifo_in2.fifo_element[2]._out_a_B : 1 [by t.fifo_in2.fifo_element[3].in.a:=0]
444051 t._out1.r : 1 [by t.fifo_in1.fifo_element[3].buf_func._y:=0]
444059 t.fifo_in1.fifo_element[3].inack_ctl._y : 0 [by t._out1.r:=1]
444093 t.fifo_in1.fifo_element[3].in.a : 1 [by t.fifo_in1.fifo_element[3].inack_ctl._y:=0]
445011 t.fifo_in1.fifo_element[2]._out_a_B : 0 [by t.fifo_in1.fifo_element[3].in.a:=1]
447877 t.arb.arbiter._y2 : 0 [by t._out2.r:=1]
447881 t.arb._y2_arb : 1 [by t.arb.arbiter._y2:=0]
451979 t.fifo_in1.fifo_element[2].in.a : 1 [by t.fifo_in1.fifo_element[2].inack_ctl._y:=0]
454377 t.fifo_in1.fifo_element[2]._en : 0 [by t.fifo_in1.fifo_element[2].in.a:=1]
455194 t.fifo_in1.fifo_element[1]._out_a_B : 0 [by t.fifo_in1.fifo_element[2].in.a:=1]
455242 t.fifo_in1.fifo_element[1].buf_func._y : 1 [by t.fifo_in1.fifo_element[1]._out_a_B:=0]
455245 t.fifo_in1.fifo_element[2].in.r : 0 [by t.fifo_in1.fifo_element[1].buf_func._y:=1]
455423 t.fifo_in1.fifo_element[2].inack_ctl._y : 1 [by t.fifo_in1.fifo_element[2].in.r:=0]
456302 t.fifo_in2.fifo_element[1]._en : 1 [by t.fifo_in2.fifo_element[1].in.a:=0]
457980 t.fifo_in1.fifo_element[3]._en : 0 [by t.fifo_in1.fifo_element[3].in.a:=1]
476400 t.fifo_in1.fifo_element[2].in.a : 0 [by t.fifo_in1.fifo_element[2].inack_ctl._y:=1]
488299 t.fifo_in1.fifo_element[1]._out_a_B : 1 [by t.fifo_in1.fifo_element[2].in.a:=0]
494259 t.arb.or_cell._y : 0 [by t.arb._y2_arb:=1]
495523 t.fifo_in1.fifo_element[0]._out_a_B : 0 [by t.fifo_in1.fifo_element[1].in.a:=1]
500210 t.out.r : 1 [by t.arb.or_cell._y:=0]
501496 t.fifo_in1.fifo_element[2].buf_func._y : 1 [by t.fifo_in1.fifo_element[2]._en:=0]
502323 t.fifo_in1.fifo_element[3].in.r : 0 [by t.fifo_in1.fifo_element[2].buf_func._y:=1]
502496 t.fifo_in1.fifo_element[3].inack_ctl._y : 1 [by t.fifo_in1.fifo_element[3].in.r:=0]
502497 t.fifo_in1.fifo_element[3].in.a : 0 [by t.fifo_in1.fifo_element[3].inack_ctl._y:=1]
502507 t.fifo_in1.fifo_element[2]._en : 1 [by t.fifo_in1.fifo_element[3].in.r:=0]
502570 t.fifo_in1.fifo_element[2]._out_a_B : 1 [by t.fifo_in1.fifo_element[3].in.a:=0]
535008 t.fifo_in1.fifo_element[0].buf_func._y : 1 [by t.fifo_in1.fifo_element[0]._out_a_B:=0]
535012 t.fifo_in1.fifo_element[1].in.r : 0 [by t.fifo_in1.fifo_element[0].buf_func._y:=1]
572300 t.fifo_in1.fifo_element[1].inack_ctl._y : 1 [by t.fifo_in1.fifo_element[1].in.r:=0]
572396 t.fifo_in1.fifo_element[1].in.a : 0 [by t.fifo_in1.fifo_element[1].inack_ctl._y:=1]
572397 t.fifo_in1.fifo_element[0]._out_a_B : 1 [by t.fifo_in1.fifo_element[1].in.a:=0]
572532 t.fifo_in1.fifo_element[1]._en : 1 [by t.fifo_in1.fifo_element[1].in.a:=0]
----------------------------------------------------------------------------------------------------
[2] 1 bit processed by the arbiter
572532 t.out.a : 1
591578 t.arb.ack_cell2._y : 0 [by t.out.a:=1]
591819 t._out2.a : 1 [by t.arb.ack_cell2._y:=0]
595778 t.fifo_in2.fifo_element[3]._out_a_B : 0 [by t._out2.a:=1]
595790 t.fifo_in2.fifo_element[3].buf_func._y : 1 [by t.fifo_in2.fifo_element[3]._out_a_B:=0]
599690 t._out2.r : 0 [by t.fifo_in2.fifo_element[3].buf_func._y:=1]
599691 t.arb.arbiter._y2 : 1 [by t._out2.r:=0]
599747 t.arb.arbiter._y1 : 0 [by t.arb.arbiter._y2:=1]
600719 t.fifo_in2.fifo_element[3]._en : 1 [by t._out2.r:=0]
644697 t.arb._y2_arb : 0 [by t.arb.arbiter._y2:=1]
644698 t.arb.or_cell._y : 1 [by t.arb._y2_arb:=0]
644735 t.out.r : 0 [by t.arb.or_cell._y:=1]
644735 t.out.a : 0
668110 t.arb.ack_cell2._y : 1 [by t.out.a:=0]
668111 t._out2.a : 0 [by t.arb.ack_cell2._y:=1]
669803 t.arb._y1_arb : 1 [by t._out2.a:=0]
669816 t.arb.or_cell._y : 0 [by t.arb._y1_arb:=1]
671675 t.fifo_in2.fifo_element[3]._out_a_B : 1 [by t._out2.a:=0]
686800 t.out.r : 1 [by t.arb.or_cell._y:=0]
----------------------------------------------------------------------------------------------------
[3] 2 bit processed by the arbiter
686800 t.out.a : 1
686800 t.in2.r : 0
686800 t.in1.r : 0
686821 t.fifo_in1.fifo_element[0].inack_ctl._y : 1 [by t.in1.r:=0]
686822 t.in1.a : 0 [by t.fifo_in1.fifo_element[0].inack_ctl._y:=1]
686825 t.fifo_in2.fifo_element[0].inack_ctl._y : 1 [by t.in2.r:=0]
686826 t.in2.a : 0 [by t.fifo_in2.fifo_element[0].inack_ctl._y:=1]
686827 t.fifo_in2.fifo_element[0]._en : 1 [by t.in2.a:=0]
687157 t.arb.ack_cell1._y : 0 [by t.out.a:=1]
687318 t._out1.a : 1 [by t.arb.ack_cell1._y:=0]
688355 t.fifo_in1.fifo_element[3]._out_a_B : 0 [by t._out1.a:=1]
688360 t.fifo_in1.fifo_element[3].buf_func._y : 1 [by t.fifo_in1.fifo_element[3]._out_a_B:=0]
688941 t._out1.r : 0 [by t.fifo_in1.fifo_element[3].buf_func._y:=1]
688952 t.fifo_in1.fifo_element[3]._en : 1 [by t._out1.r:=0]
689349 t.arb.arbiter._y1 : 1 [by t._out1.r:=0]
690396 t.arb._y1_arb : 0 [by t.arb.arbiter._y1:=1]
690410 t.arb.or_cell._y : 1 [by t.arb._y1_arb:=0]
690428 t.out.r : 0 [by t.arb.or_cell._y:=1]
696470 t.fifo_in1.fifo_element[0]._en : 1 [by t.in1.a:=0]
696470 t.out.a : 0
696470 t.in2.r : 1
696470 t.in1.r : 1
696474 t.arb.ack_cell1._y : 1 [by t.out.a:=0]
696574 t.fifo_in2.fifo_element[0].buf_func._y : 0 [by t.in2.r:=1]
697678 t._out1.a : 0 [by t.arb.ack_cell1._y:=1]
697906 t.fifo_in1.fifo_element[3]._out_a_B : 1 [by t._out1.a:=0]
705029 t.fifo_in2.fifo_element[1].in.r : 1 [by t.fifo_in2.fifo_element[0].buf_func._y:=0]
705872 t.fifo_in2.fifo_element[1].buf_func._y : 0 [by t.fifo_in2.fifo_element[1].in.r:=1]
705942 t.fifo_in2.fifo_element[2].in.r : 1 [by t.fifo_in2.fifo_element[1].buf_func._y:=0]
705953 t.fifo_in2.fifo_element[1].inack_ctl._y : 0 [by t.fifo_in2.fifo_element[2].in.r:=1]
705956 t.fifo_in2.fifo_element[1].in.a : 1 [by t.fifo_in2.fifo_element[1].inack_ctl._y:=0]
706010 t.fifo_in2.fifo_element[1]._en : 0 [by t.fifo_in2.fifo_element[1].in.a:=1]
706488 t.fifo_in2.fifo_element[0].inack_ctl._y : 0 [by t.fifo_in2.fifo_element[1].in.r:=1]
707104 t.fifo_in2.fifo_element[0]._out_a_B : 0 [by t.fifo_in2.fifo_element[1].in.a:=1]
707649 t.in2.a : 1 [by t.fifo_in2.fifo_element[0].inack_ctl._y:=0]
716301 t.fifo_in2.fifo_element[0]._en : 0 [by t.in2.a:=1]
716382 t.fifo_in2.fifo_element[0].buf_func._y : 1 [by t.fifo_in2.fifo_element[0]._en:=0]
727459 t.fifo_in2.fifo_element[1].in.r : 0 [by t.fifo_in2.fifo_element[0].buf_func._y:=1]
727914 t.fifo_in1.fifo_element[0].buf_func._y : 0 [by t.in1.r:=1]
728006 t.fifo_in1.fifo_element[1].in.r : 1 [by t.fifo_in1.fifo_element[0].buf_func._y:=0]
729750 t.fifo_in1.fifo_element[0].inack_ctl._y : 0 [by t.fifo_in1.fifo_element[1].in.r:=1]
730363 t.in1.a : 1 [by t.fifo_in1.fifo_element[0].inack_ctl._y:=0]
736317 t.fifo_in1.fifo_element[1].buf_func._y : 0 [by t.fifo_in1.fifo_element[1].in.r:=1]
736362 t.fifo_in1.fifo_element[2].in.r : 1 [by t.fifo_in1.fifo_element[1].buf_func._y:=0]
737359 t.fifo_in1.fifo_element[2].buf_func._y : 0 [by t.fifo_in1.fifo_element[2].in.r:=1]
737884 t.fifo_in1.fifo_element[3].in.r : 1 [by t.fifo_in1.fifo_element[2].buf_func._y:=0]
737936 t.fifo_in1.fifo_element[2].inack_ctl._y : 0 [by t.fifo_in1.fifo_element[3].in.r:=1]
737943 t.fifo_in1.fifo_element[2].in.a : 1 [by t.fifo_in1.fifo_element[2].inack_ctl._y:=0]
738011 t.fifo_in1.fifo_element[1].inack_ctl._y : 0 [by t.fifo_in1.fifo_element[2].in.r:=1]
738013 t.fifo_in1.fifo_element[1].in.a : 1 [by t.fifo_in1.fifo_element[1].inack_ctl._y:=0]
738146 t.fifo_in1.fifo_element[0]._out_a_B : 0 [by t.fifo_in1.fifo_element[1].in.a:=1]
738367 t.fifo_in1.fifo_element[1]._en : 0 [by t.fifo_in1.fifo_element[1].in.a:=1]
738784 t.fifo_in1.fifo_element[3].buf_func._y : 0 [by t.fifo_in1.fifo_element[3].in.r:=1]
738785 t._out1.r : 1 [by t.fifo_in1.fifo_element[3].buf_func._y:=0]
738789 t.arb.arbiter._y1 : 0 [by t._out1.r:=1]
739331 t.fifo_in1.fifo_element[3].inack_ctl._y : 0 [by t._out1.r:=1]
739332 t.fifo_in1.fifo_element[3].in.a : 1 [by t.fifo_in1.fifo_element[3].inack_ctl._y:=0]
739411 t.fifo_in1.fifo_element[2]._out_a_B : 0 [by t.fifo_in1.fifo_element[3].in.a:=1]
744385 t.fifo_in1.fifo_element[0]._en : 0 [by t.in1.a:=1]
744410 t.fifo_in1.fifo_element[1]._out_a_B : 0 [by t.fifo_in1.fifo_element[2].in.a:=1]
744498 t.fifo_in1.fifo_element[1].buf_func._y : 1 [by t.fifo_in1.fifo_element[1]._out_a_B:=0]
745442 t.fifo_in2.fifo_element[1].inack_ctl._y : 1 [by t.fifo_in2.fifo_element[1].in.r:=0]
746818 t.fifo_in1.fifo_element[0].buf_func._y : 1 [by t.fifo_in1.fifo_element[0]._en:=0]
746877 t.fifo_in1.fifo_element[1].in.r : 0 [by t.fifo_in1.fifo_element[0].buf_func._y:=1]
746907 t.fifo_in1.fifo_element[1].inack_ctl._y : 1 [by t.fifo_in1.fifo_element[1].in.r:=0]
748374 t.fifo_in1.fifo_element[1].in.a : 0 [by t.fifo_in1.fifo_element[1].inack_ctl._y:=1]
751710 t.fifo_in1.fifo_element[3]._en : 0 [by t.fifo_in1.fifo_element[3].in.a:=1]
752280 t.fifo_in1.fifo_element[2].in.r : 0 [by t.fifo_in1.fifo_element[1].buf_func._y:=1]
753555 t.fifo_in1.fifo_element[2]._en : 0 [by t.fifo_in1.fifo_element[2].in.a:=1]
754240 t.fifo_in1.fifo_element[2].buf_func._y : 1 [by t.fifo_in1.fifo_element[2]._en:=0]
754367 t.fifo_in1.fifo_element[3].in.r : 0 [by t.fifo_in1.fifo_element[2].buf_func._y:=1]
754536 t.fifo_in1.fifo_element[3].inack_ctl._y : 1 [by t.fifo_in1.fifo_element[3].in.r:=0]
754579 t.fifo_in1.fifo_element[3].in.a : 0 [by t.fifo_in1.fifo_element[3].inack_ctl._y:=1]
754591 t.fifo_in1.fifo_element[2]._out_a_B : 1 [by t.fifo_in1.fifo_element[3].in.a:=0]
756364 t.fifo_in2.fifo_element[2].buf_func._y : 0 [by t.fifo_in2.fifo_element[2].in.r:=1]
757643 t.fifo_in2.fifo_element[3].in.r : 1 [by t.fifo_in2.fifo_element[2].buf_func._y:=0]
757646 t.fifo_in2.fifo_element[2].inack_ctl._y : 0 [by t.fifo_in2.fifo_element[3].in.r:=1]
757684 t.fifo_in2.fifo_element[2].in.a : 1 [by t.fifo_in2.fifo_element[2].inack_ctl._y:=0]
757685 t.fifo_in2.fifo_element[2]._en : 0 [by t.fifo_in2.fifo_element[2].in.a:=1]
757876 t.fifo_in2.fifo_element[3].buf_func._y : 0 [by t.fifo_in2.fifo_element[3].in.r:=1]
757968 t._out2.r : 1 [by t.fifo_in2.fifo_element[3].buf_func._y:=0]
760695 t.fifo_in2.fifo_element[3].inack_ctl._y : 0 [by t._out2.r:=1]
760697 t.fifo_in2.fifo_element[3].in.a : 1 [by t.fifo_in2.fifo_element[3].inack_ctl._y:=0]
760698 t.fifo_in2.fifo_element[3]._en : 0 [by t.fifo_in2.fifo_element[3].in.a:=1]
762198 t.fifo_in2.fifo_element[2]._out_a_B : 0 [by t.fifo_in2.fifo_element[3].in.a:=1]
762200 t.fifo_in2.fifo_element[2].buf_func._y : 1 [by t.fifo_in2.fifo_element[2]._out_a_B:=0]
762218 t.fifo_in2.fifo_element[3].in.r : 0 [by t.fifo_in2.fifo_element[2].buf_func._y:=1]
762337 t.fifo_in2.fifo_element[3].inack_ctl._y : 1 [by t.fifo_in2.fifo_element[3].in.r:=0]
768057 t.fifo_in2.fifo_element[3].in.a : 0 [by t.fifo_in2.fifo_element[3].inack_ctl._y:=1]
768065 t.fifo_in2.fifo_element[2]._out_a_B : 1 [by t.fifo_in2.fifo_element[3].in.a:=0]
770270 t.fifo_in1.fifo_element[2].inack_ctl._y : 1 [by t.fifo_in1.fifo_element[2]._en:=0]
770324 t.fifo_in1.fifo_element[2].in.a : 0 [by t.fifo_in1.fifo_element[2].inack_ctl._y:=1]
770329 t.fifo_in1.fifo_element[1]._out_a_B : 1 [by t.fifo_in1.fifo_element[2].in.a:=0]
770436 t.fifo_in2.fifo_element[1]._out_a_B : 0 [by t.fifo_in2.fifo_element[2].in.a:=1]
771503 t.fifo_in2.fifo_element[1].buf_func._y : 1 [by t.fifo_in2.fifo_element[1]._out_a_B:=0]
771504 t.fifo_in2.fifo_element[2].in.r : 0 [by t.fifo_in2.fifo_element[1].buf_func._y:=1]
771642 t.fifo_in2.fifo_element[2].inack_ctl._y : 1 [by t.fifo_in2.fifo_element[2].in.r:=0]
771643 t.fifo_in2.fifo_element[2].in.a : 0 [by t.fifo_in2.fifo_element[2].inack_ctl._y:=1]
771664 t.fifo_in1.fifo_element[1]._en : 1 [by t.fifo_in1.fifo_element[2].in.r:=0]
771707 t.fifo_in2.fifo_element[2]._en : 1 [by t.fifo_in2.fifo_element[2].in.a:=0]
771766 t.fifo_in2.fifo_element[1]._out_a_B : 1 [by t.fifo_in2.fifo_element[2].in.a:=0]
773769 t.fifo_in2.fifo_element[1].in.a : 0 [by t.fifo_in2.fifo_element[1].inack_ctl._y:=1]
773771 t.fifo_in2.fifo_element[1]._en : 1 [by t.fifo_in2.fifo_element[1].in.a:=0]
773806 t.fifo_in2.fifo_element[0]._out_a_B : 1 [by t.fifo_in2.fifo_element[1].in.a:=0]
784352 t.arb._y1_arb : 1 [by t.arb.arbiter._y1:=0]
784495 t.arb.or_cell._y : 0 [by t.arb._y1_arb:=1]
784546 t.out.r : 1 [by t.arb.or_cell._y:=0]
807878 t.fifo_in1.fifo_element[0]._out_a_B : 1 [by t.fifo_in1.fifo_element[1].in.a:=0]
820862 t.fifo_in1.fifo_element[2]._en : 1 [by t.fifo_in1.fifo_element[2].in.a:=0]
----------------------------------------------------------------------------------------------------
[4] 3 bit processed by the arbiter
820862 t.out.a : 1
821304 t.arb.ack_cell1._y : 0 [by t.out.a:=1]
821315 t._out1.a : 1 [by t.arb.ack_cell1._y:=0]
821316 t.fifo_in1.fifo_element[3]._out_a_B : 0 [by t._out1.a:=1]
821325 t.fifo_in1.fifo_element[3].buf_func._y : 1 [by t.fifo_in1.fifo_element[3]._out_a_B:=0]
821350 t._out1.r : 0 [by t.fifo_in1.fifo_element[3].buf_func._y:=1]
824871 t.fifo_in1.fifo_element[3]._en : 1 [by t._out1.r:=0]
831603 t.arb.arbiter._y1 : 1 [by t._out1.r:=0]
831748 t.arb.arbiter._y2 : 0 [by t.arb.arbiter._y1:=1]
847771 t.arb._y1_arb : 0 [by t.arb.arbiter._y1:=1]
848001 t.arb.or_cell._y : 1 [by t.arb._y1_arb:=0]
848692 t.out.r : 0 [by t.arb.or_cell._y:=1]
848692 t.out.a : 0
848706 t.arb.ack_cell1._y : 1 [by t.out.a:=0]
850249 t._out1.a : 0 [by t.arb.ack_cell1._y:=1]
851860 t.arb._y2_arb : 1 [by t._out1.a:=0]
851871 t.arb.or_cell._y : 0 [by t.arb._y2_arb:=1]
851872 t.out.r : 1 [by t.arb.or_cell._y:=0]
867761 t.fifo_in1.fifo_element[3]._out_a_B : 1 [by t._out1.a:=0]
----------------------------------------------------------------------------------------------------
[5] 4 bit processed by the arbiter

606
test/unit_tests/arbiter_handshake_adv/run/test.prs
View File

@@ -1,606 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"t.fifo_in2.reset_bufarray.buf1.a"->"t.fifo_in2.reset_bufarray.buf1._y"-
~("t.fifo_in2.reset_bufarray.buf1.a")->"t.fifo_in2.reset_bufarray.buf1._y"+
"t.fifo_in2.reset_bufarray.buf1._y"->"t.fifo_in2.reset_bufarray.buf1.y"-
~("t.fifo_in2.reset_bufarray.buf1._y")->"t.fifo_in2.reset_bufarray.buf1.y"+
= "t.fifo_in2.reset_bufarray.supply.vdd" "t.fifo_in2.reset_bufarray.buf1.vdd"
= "t.fifo_in2.reset_bufarray.supply.vss" "t.fifo_in2.reset_bufarray.buf1.vss"
= "t.fifo_in2.reset_bufarray.out[0]" "t.fifo_in2.reset_bufarray.out[3]"
= "t.fifo_in2.reset_bufarray.out[0]" "t.fifo_in2.reset_bufarray.out[2]"
= "t.fifo_in2.reset_bufarray.out[0]" "t.fifo_in2.reset_bufarray.out[1]"
= "t.fifo_in2.reset_bufarray.out[0]" "t.fifo_in2.reset_bufarray.buf1.y"
= "t.fifo_in2.reset_bufarray.in" "t.fifo_in2.reset_bufarray.buf1.a"
"t.fifo_in2.reset_buf.a"->"t.fifo_in2.reset_buf._y"-
~("t.fifo_in2.reset_buf.a")->"t.fifo_in2.reset_buf._y"+
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= "t.fifo_in2.fifo_element[2].in.d.d[0]" "t.fifo_in2.fifo_element[2].inack_ctl.c2"
= "t.fifo_in2.fifo_element[2].in.d.d[0]" "t.fifo_in2.fifo_element[2].in.r"
= "t.fifo_in2.fifo_element[2].out.d.d[0]" "t.fifo_in2.fifo_element[2].out.r"
= "t.fifo_in2.fifo_element[2].out.a" "t.fifo_in2.fifo_element[2].inv_outa.a"
= "t.fifo_in2.fifo_element[2].out.d.d[0]" "t.fifo_in2.fifo_element[2].buf_func.y"
= "t.fifo_in2.fifo_element[2].out.d.d[0]" "t.fifo_in2.fifo_element[2].en_ctl.p1"
= "t.fifo_in2.fifo_element[2].out.d.d[0]" "t.fifo_in2.fifo_element[2].inack_ctl.n1"
= "t.fifo_in2.fifo_element[2].out.d.d[0]" "t.fifo_in2.fifo_element[2].out.r"
"t.fifo_in2.fifo_element[3].reset_buf.a"->"t.fifo_in2.fifo_element[3].reset_buf._y"-
~("t.fifo_in2.fifo_element[3].reset_buf.a")->"t.fifo_in2.fifo_element[3].reset_buf._y"+
"t.fifo_in2.fifo_element[3].reset_buf._y"->"t.fifo_in2.fifo_element[3].reset_buf.y"-
~("t.fifo_in2.fifo_element[3].reset_buf._y")->"t.fifo_in2.fifo_element[3].reset_buf.y"+
"t.fifo_in2.fifo_element[3].inv_outa.a"->"t.fifo_in2.fifo_element[3].inv_outa.y"-
~("t.fifo_in2.fifo_element[3].inv_outa.a")->"t.fifo_in2.fifo_element[3].inv_outa.y"+
~"t.fifo_in2.fifo_element[3].inack_ctl.c1"&~"t.fifo_in2.fifo_element[3].inack_ctl.c2"|~"t.fifo_in2.fifo_element[3].inack_ctl.pr_B"->"t.fifo_in2.fifo_element[3].inack_ctl._y"+
"t.fifo_in2.fifo_element[3].inack_ctl.c1"&"t.fifo_in2.fifo_element[3].inack_ctl.c2"&"t.fifo_in2.fifo_element[3].inack_ctl.n1"&"t.fifo_in2.fifo_element[3].inack_ctl.sr_B"->"t.fifo_in2.fifo_element[3].inack_ctl._y"-
"t.fifo_in2.fifo_element[3].inack_ctl._y"->"t.fifo_in2.fifo_element[3].inack_ctl.y"-
~("t.fifo_in2.fifo_element[3].inack_ctl._y")->"t.fifo_in2.fifo_element[3].inack_ctl.y"+
~"t.fifo_in2.fifo_element[3].buf_func.c1"&~"t.fifo_in2.fifo_element[3].buf_func.c2"|~"t.fifo_in2.fifo_element[3].buf_func.pr_B"->"t.fifo_in2.fifo_element[3].buf_func._y"+
"t.fifo_in2.fifo_element[3].buf_func.c1"&"t.fifo_in2.fifo_element[3].buf_func.c2"&"t.fifo_in2.fifo_element[3].buf_func.n1"&"t.fifo_in2.fifo_element[3].buf_func.sr_B"->"t.fifo_in2.fifo_element[3].buf_func._y"-
"t.fifo_in2.fifo_element[3].buf_func._y"->"t.fifo_in2.fifo_element[3].buf_func.y"-
~("t.fifo_in2.fifo_element[3].buf_func._y")->"t.fifo_in2.fifo_element[3].buf_func.y"+
= "t.fifo_in2.fifo_element[3].reset_B" "t.fifo_in2.fifo_element[3].reset_buf.a"
= "t.fifo_in2.fifo_element[3].supply.vdd" "t.fifo_in2.fifo_element[3].reset_buf.vdd"
= "t.fifo_in2.fifo_element[3].supply.vdd" "t.fifo_in2.fifo_element[3].buf_func.vdd"
= "t.fifo_in2.fifo_element[3].supply.vdd" "t.fifo_in2.fifo_element[3].inv_outa.vdd"
= "t.fifo_in2.fifo_element[3].supply.vdd" "t.fifo_in2.fifo_element[3].en_ctl.vdd"
= "t.fifo_in2.fifo_element[3].supply.vdd" "t.fifo_in2.fifo_element[3].inack_ctl.vdd"
= "t.fifo_in2.fifo_element[3].supply.vss" "t.fifo_in2.fifo_element[3].reset_buf.vss"
= "t.fifo_in2.fifo_element[3].supply.vss" "t.fifo_in2.fifo_element[3].buf_func.vss"
= "t.fifo_in2.fifo_element[3].supply.vss" "t.fifo_in2.fifo_element[3].inv_outa.vss"
= "t.fifo_in2.fifo_element[3].supply.vss" "t.fifo_in2.fifo_element[3].en_ctl.vss"
= "t.fifo_in2.fifo_element[3].supply.vss" "t.fifo_in2.fifo_element[3].inack_ctl.vss"
= "t.fifo_in2.fifo_element[3]._reset_BX" "t.fifo_in2.fifo_element[3].reset_buf.y"
= "t.fifo_in2.fifo_element[3]._reset_BX" "t.fifo_in2.fifo_element[3].buf_func.sr_B"
= "t.fifo_in2.fifo_element[3]._reset_BX" "t.fifo_in2.fifo_element[3].buf_func.pr_B"
= "t.fifo_in2.fifo_element[3]._reset_BX" "t.fifo_in2.fifo_element[3].inack_ctl.sr_B"
= "t.fifo_in2.fifo_element[3]._reset_BX" "t.fifo_in2.fifo_element[3].inack_ctl.pr_B"
= "t.fifo_in2.fifo_element[3]._en" "t.fifo_in2.fifo_element[3].buf_func.c1"
= "t.fifo_in2.fifo_element[3]._en" "t.fifo_in2.fifo_element[3].en_ctl.y"
= "t.fifo_in2.fifo_element[3]._en" "t.fifo_in2.fifo_element[3].inack_ctl.c1"
~"t.fifo_in2.fifo_element[3].en_ctl.p1"&~"t.fifo_in2.fifo_element[3].en_ctl.c1"->"t.fifo_in2.fifo_element[3].en_ctl.y"+
"t.fifo_in2.fifo_element[3].en_ctl.c1"->"t.fifo_in2.fifo_element[3].en_ctl.y"-
= "t.fifo_in2.fifo_element[3]._out_a_B" "t.fifo_in2.fifo_element[3].buf_func.c2"
= "t.fifo_in2.fifo_element[3]._out_a_B" "t.fifo_in2.fifo_element[3].inv_outa.y"
= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[3].in.r"
= "t.fifo_in2.fifo_element[3].in.a" "t.fifo_in2.fifo_element[3].en_ctl.c1"
= "t.fifo_in2.fifo_element[3].in.a" "t.fifo_in2.fifo_element[3].inack_ctl.y"
= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[3].buf_func.n1"
= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[3].inack_ctl.c2"
= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[3].in.r"
= "t.fifo_in2.fifo_element[3].out.d.d[0]" "t.fifo_in2.fifo_element[3].out.r"
= "t.fifo_in2.fifo_element[3].out.a" "t.fifo_in2.fifo_element[3].inv_outa.a"
= "t.fifo_in2.fifo_element[3].out.d.d[0]" "t.fifo_in2.fifo_element[3].buf_func.y"
= "t.fifo_in2.fifo_element[3].out.d.d[0]" "t.fifo_in2.fifo_element[3].en_ctl.p1"
= "t.fifo_in2.fifo_element[3].out.d.d[0]" "t.fifo_in2.fifo_element[3].inack_ctl.n1"
= "t.fifo_in2.fifo_element[3].out.d.d[0]" "t.fifo_in2.fifo_element[3].out.r"
= "t.fifo_in2.fifo_element[3].in.a" "t.fifo_in2.fifo_element[2].out.a"
= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[2].out.r"
= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[2].out.d.d[0]"
= "t.fifo_in2.fifo_element[3].in.d.d[0]" "t.fifo_in2.fifo_element[3].in.r"
= "t.fifo_in2.fifo_element[2].in.a" "t.fifo_in2.fifo_element[1].out.a"
= "t.fifo_in2.fifo_element[2].in.d.d[0]" "t.fifo_in2.fifo_element[1].out.r"
= "t.fifo_in2.fifo_element[2].in.d.d[0]" "t.fifo_in2.fifo_element[1].out.d.d[0]"
= "t.fifo_in2.fifo_element[2].in.d.d[0]" "t.fifo_in2.fifo_element[2].in.r"
= "t.fifo_in2.fifo_element[1].in.a" "t.fifo_in2.fifo_element[0].out.a"
= "t.fifo_in2.fifo_element[1].in.d.d[0]" "t.fifo_in2.fifo_element[0].out.r"
= "t.fifo_in2.fifo_element[1].in.d.d[0]" "t.fifo_in2.fifo_element[0].out.d.d[0]"
= "t.fifo_in2.fifo_element[1].in.d.d[0]" "t.fifo_in2.fifo_element[1].in.r"
= "t.fifo_in2._reset_BXX[0]" "t.fifo_in2.reset_bufarray.out[0]"
= "t.fifo_in2._reset_BXX[1]" "t.fifo_in2.reset_bufarray.out[1]"
= "t.fifo_in2._reset_BXX[2]" "t.fifo_in2.reset_bufarray.out[2]"
= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2.reset_bufarray.out[3]"
= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2.fifo_element[2].reset_B"
= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2._reset_BXX[2]"
= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2.fifo_element[1].reset_B"
= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2._reset_BXX[1]"
= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2.fifo_element[0].reset_B"
= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2._reset_BXX[0]"
= "t.fifo_in2._reset_BXX[3]" "t.fifo_in2.fifo_element[3].reset_B"
= "t.fifo_in2.in.d.d[0]" "t.fifo_in2.in.r"
= "t.fifo_in2.in.a" "t.fifo_in2.fifo_element[0].in.a"
= "t.fifo_in2.in.d.d[0]" "t.fifo_in2.fifo_element[0].in.r"
= "t.fifo_in2.in.d.d[0]" "t.fifo_in2.fifo_element[0].in.d.d[0]"
= "t.fifo_in2.in.d.d[0]" "t.fifo_in2.in.r"
= "t.fifo_in2.out.d.d[0]" "t.fifo_in2.out.r"
= "t.fifo_in2.out.a" "t.fifo_in2.fifo_element[3].out.a"
= "t.fifo_in2.out.d.d[0]" "t.fifo_in2.fifo_element[3].out.r"
= "t.fifo_in2.out.d.d[0]" "t.fifo_in2.fifo_element[3].out.d.d[0]"
= "t.fifo_in2.out.d.d[0]" "t.fifo_in2.out.r"
= "Reset" "t.fifo_in2.reset_B"
= "Vdd" "t.fifo_in2.supply.vdd"
= "GND" "t.fifo_in2.supply.vss"
= "t._out2.d.d[0]" "t._out2.r"
= "t._out2.r" "t.arb.in2.r"
= "t._out2.a" "t.arb.in2.a"
= "t._out2.d.d[0]" "t.arb.in2.d.d[0]"
= "t._out2.r" "t.fifo_in2.out.r"
= "t._out2.a" "t.fifo_in2.out.a"
= "t._out2.d.d[0]" "t.fifo_in2.out.d.d[0]"
= "t._out2.d.d[0]" "t._out2.r"
= "t._out1.d.d[0]" "t._out1.r"
= "t._out1.r" "t.arb.in1.r"
= "t._out1.a" "t.arb.in1.a"
= "t._out1.d.d[0]" "t.arb.in1.d.d[0]"
= "t._out1.r" "t.fifo_in1.out.r"
= "t._out1.a" "t.fifo_in1.out.a"
= "t._out1.d.d[0]" "t.fifo_in1.out.d.d[0]"
= "t._out1.d.d[0]" "t._out1.r"
= "t.in1.d.d[0]" "t.in1.r"
= "t.in1.r" "t.fifo_in1.in.r"
= "t.in1.a" "t.fifo_in1.in.a"
= "t.in1.d.d[0]" "t.fifo_in1.in.d.d[0]"
= "t.in1.d.d[0]" "t.in1.r"
= "t.arb.in1.d.d[0]" "t.arb.in1.r"
= "t.arb.in1.a" "t.arb.arbiter.d"
= "t.arb.in1.a" "t.arb.ack_cell1.y"
= "t.arb.in1.d.d[0]" "t.arb.arbiter.a"
= "t.arb.in1.d.d[0]" "t.arb.in1.r"
~"t.arb.ack_cell1.c1"&~"t.arb.ack_cell1.c2"->"t.arb.ack_cell1._y"+
"t.arb.ack_cell1.c1"&"t.arb.ack_cell1.c2"->"t.arb.ack_cell1._y"-
"t.arb.ack_cell1._y"->"t.arb.ack_cell1.y"-
~("t.arb.ack_cell1._y")->"t.arb.ack_cell1.y"+
= "t.arb.in2.d.d[0]" "t.arb.in2.r"
= "t.arb.in2.a" "t.arb.arbiter.c"
= "t.arb.in2.a" "t.arb.ack_cell2.y"
= "t.arb.in2.d.d[0]" "t.arb.arbiter.b"
= "t.arb.in2.d.d[0]" "t.arb.in2.r"
= "t.arb.supply.vdd" "t.arb.arbiter.vdd"
= "t.arb.supply.vdd" "t.arb.or_cell.vdd"
= "t.arb.supply.vdd" "t.arb.ack_cell2.vdd"
= "t.arb.supply.vdd" "t.arb.ack_cell1.vdd"
= "t.arb.supply.vss" "t.arb.arbiter.vss"
= "t.arb.supply.vss" "t.arb.or_cell.vss"
= "t.arb.supply.vss" "t.arb.ack_cell2.vss"
= "t.arb.supply.vss" "t.arb.ack_cell1.vss"
"t.arb.arbiter.a"&"t.arb.arbiter._y2"->"t.arb.arbiter._y1"-
~"t.arb.arbiter.a"|~"t.arb.arbiter._y2"->"t.arb.arbiter._y1"+
"t.arb.arbiter.b"&"t.arb.arbiter._y1"->"t.arb.arbiter._y2"-
~"t.arb.arbiter.b"|~"t.arb.arbiter._y1"->"t.arb.arbiter._y2"+
"t.arb.arbiter._y1"|"t.arb.arbiter.c"->"t.arb.arbiter.y1"-
~("t.arb.arbiter._y1"|"t.arb.arbiter.c")->"t.arb.arbiter.y1"+
"t.arb.arbiter._y2"|"t.arb.arbiter.d"->"t.arb.arbiter.y2"-
~("t.arb.arbiter._y2"|"t.arb.arbiter.d")->"t.arb.arbiter.y2"+
mk_excllo("t.arb.arbiter._y1","t.arb.arbiter._y2")
= "t.arb._y1_arb" "t.arb.arbiter.y1"
= "t.arb._y1_arb" "t.arb.or_cell.a"
= "t.arb._y1_arb" "t.arb.ack_cell1.c2"
~"t.arb.ack_cell2.c1"&~"t.arb.ack_cell2.c2"->"t.arb.ack_cell2._y"+
"t.arb.ack_cell2.c1"&"t.arb.ack_cell2.c2"->"t.arb.ack_cell2._y"-
"t.arb.ack_cell2._y"->"t.arb.ack_cell2.y"-
~("t.arb.ack_cell2._y")->"t.arb.ack_cell2.y"+
"t.arb.or_cell.a"|"t.arb.or_cell.b"->"t.arb.or_cell._y"-
~("t.arb.or_cell.a"|"t.arb.or_cell.b")->"t.arb.or_cell._y"+
"t.arb.or_cell._y"->"t.arb.or_cell.y"-
~("t.arb.or_cell._y")->"t.arb.or_cell.y"+
= "t.arb.out.d.d[0]" "t.arb.out.r"
= "t.arb.out.a" "t.arb.ack_cell2.c1"
= "t.arb.out.a" "t.arb.ack_cell1.c1"
= "t.arb.out.d.d[0]" "t.arb.or_cell.y"
= "t.arb.out.d.d[0]" "t.arb.out.r"
= "t.arb._y2_arb" "t.arb.arbiter.y2"
= "t.arb._y2_arb" "t.arb.or_cell.b"
= "t.arb._y2_arb" "t.arb.ack_cell2.c2"
= "Vdd" "t.arb.supply.vdd"
= "GND" "t.arb.supply.vss"
"t.fifo_in1.reset_bufarray.buf1.a"->"t.fifo_in1.reset_bufarray.buf1._y"-
~("t.fifo_in1.reset_bufarray.buf1.a")->"t.fifo_in1.reset_bufarray.buf1._y"+
"t.fifo_in1.reset_bufarray.buf1._y"->"t.fifo_in1.reset_bufarray.buf1.y"-
~("t.fifo_in1.reset_bufarray.buf1._y")->"t.fifo_in1.reset_bufarray.buf1.y"+
= "t.fifo_in1.reset_bufarray.supply.vdd" "t.fifo_in1.reset_bufarray.buf1.vdd"
= "t.fifo_in1.reset_bufarray.supply.vss" "t.fifo_in1.reset_bufarray.buf1.vss"
= "t.fifo_in1.reset_bufarray.out[0]" "t.fifo_in1.reset_bufarray.out[3]"
= "t.fifo_in1.reset_bufarray.out[0]" "t.fifo_in1.reset_bufarray.out[2]"
= "t.fifo_in1.reset_bufarray.out[0]" "t.fifo_in1.reset_bufarray.out[1]"
= "t.fifo_in1.reset_bufarray.out[0]" "t.fifo_in1.reset_bufarray.buf1.y"
= "t.fifo_in1.reset_bufarray.in" "t.fifo_in1.reset_bufarray.buf1.a"
"t.fifo_in1.reset_buf.a"->"t.fifo_in1.reset_buf._y"-
~("t.fifo_in1.reset_buf.a")->"t.fifo_in1.reset_buf._y"+
"t.fifo_in1.reset_buf._y"->"t.fifo_in1.reset_buf.y"-
~("t.fifo_in1.reset_buf._y")->"t.fifo_in1.reset_buf.y"+
= "t.fifo_in1.reset_B" "t.fifo_in1.reset_buf.a"
= "t.fifo_in1.supply.vss" "t.fifo_in1.fifo_element[3].supply.vss"
= "t.fifo_in1.supply.vdd" "t.fifo_in1.fifo_element[3].supply.vdd"
= "t.fifo_in1.supply.vss" "t.fifo_in1.fifo_element[2].supply.vss"
= "t.fifo_in1.supply.vdd" "t.fifo_in1.fifo_element[2].supply.vdd"
= "t.fifo_in1.supply.vss" "t.fifo_in1.fifo_element[1].supply.vss"
= "t.fifo_in1.supply.vdd" "t.fifo_in1.fifo_element[1].supply.vdd"
= "t.fifo_in1.supply.vss" "t.fifo_in1.fifo_element[0].supply.vss"
= "t.fifo_in1.supply.vdd" "t.fifo_in1.fifo_element[0].supply.vdd"
= "t.fifo_in1.supply.vdd" "t.fifo_in1.reset_buf.vdd"
= "t.fifo_in1.supply.vss" "t.fifo_in1.reset_buf.vss"
= "t.fifo_in1._reset_BX" "t.fifo_in1.reset_bufarray.in"
= "t.fifo_in1._reset_BX" "t.fifo_in1.reset_buf.y"
"t.fifo_in1.fifo_element[0].reset_buf.a"->"t.fifo_in1.fifo_element[0].reset_buf._y"-
~("t.fifo_in1.fifo_element[0].reset_buf.a")->"t.fifo_in1.fifo_element[0].reset_buf._y"+
"t.fifo_in1.fifo_element[0].reset_buf._y"->"t.fifo_in1.fifo_element[0].reset_buf.y"-
~("t.fifo_in1.fifo_element[0].reset_buf._y")->"t.fifo_in1.fifo_element[0].reset_buf.y"+
"t.fifo_in1.fifo_element[0].inv_outa.a"->"t.fifo_in1.fifo_element[0].inv_outa.y"-
~("t.fifo_in1.fifo_element[0].inv_outa.a")->"t.fifo_in1.fifo_element[0].inv_outa.y"+
~"t.fifo_in1.fifo_element[0].inack_ctl.c1"&~"t.fifo_in1.fifo_element[0].inack_ctl.c2"|~"t.fifo_in1.fifo_element[0].inack_ctl.pr_B"->"t.fifo_in1.fifo_element[0].inack_ctl._y"+
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"t.fifo_in1.fifo_element[3].inack_ctl._y"->"t.fifo_in1.fifo_element[3].inack_ctl.y"-
~("t.fifo_in1.fifo_element[3].inack_ctl._y")->"t.fifo_in1.fifo_element[3].inack_ctl.y"+
~"t.fifo_in1.fifo_element[3].buf_func.c1"&~"t.fifo_in1.fifo_element[3].buf_func.c2"|~"t.fifo_in1.fifo_element[3].buf_func.pr_B"->"t.fifo_in1.fifo_element[3].buf_func._y"+
"t.fifo_in1.fifo_element[3].buf_func.c1"&"t.fifo_in1.fifo_element[3].buf_func.c2"&"t.fifo_in1.fifo_element[3].buf_func.n1"&"t.fifo_in1.fifo_element[3].buf_func.sr_B"->"t.fifo_in1.fifo_element[3].buf_func._y"-
"t.fifo_in1.fifo_element[3].buf_func._y"->"t.fifo_in1.fifo_element[3].buf_func.y"-
~("t.fifo_in1.fifo_element[3].buf_func._y")->"t.fifo_in1.fifo_element[3].buf_func.y"+
= "t.fifo_in1.fifo_element[3].reset_B" "t.fifo_in1.fifo_element[3].reset_buf.a"
= "t.fifo_in1.fifo_element[3].supply.vdd" "t.fifo_in1.fifo_element[3].reset_buf.vdd"
= "t.fifo_in1.fifo_element[3].supply.vdd" "t.fifo_in1.fifo_element[3].buf_func.vdd"
= "t.fifo_in1.fifo_element[3].supply.vdd" "t.fifo_in1.fifo_element[3].inv_outa.vdd"
= "t.fifo_in1.fifo_element[3].supply.vdd" "t.fifo_in1.fifo_element[3].en_ctl.vdd"
= "t.fifo_in1.fifo_element[3].supply.vdd" "t.fifo_in1.fifo_element[3].inack_ctl.vdd"
= "t.fifo_in1.fifo_element[3].supply.vss" "t.fifo_in1.fifo_element[3].reset_buf.vss"
= "t.fifo_in1.fifo_element[3].supply.vss" "t.fifo_in1.fifo_element[3].buf_func.vss"
= "t.fifo_in1.fifo_element[3].supply.vss" "t.fifo_in1.fifo_element[3].inv_outa.vss"
= "t.fifo_in1.fifo_element[3].supply.vss" "t.fifo_in1.fifo_element[3].en_ctl.vss"
= "t.fifo_in1.fifo_element[3].supply.vss" "t.fifo_in1.fifo_element[3].inack_ctl.vss"
= "t.fifo_in1.fifo_element[3]._reset_BX" "t.fifo_in1.fifo_element[3].reset_buf.y"
= "t.fifo_in1.fifo_element[3]._reset_BX" "t.fifo_in1.fifo_element[3].buf_func.sr_B"
= "t.fifo_in1.fifo_element[3]._reset_BX" "t.fifo_in1.fifo_element[3].buf_func.pr_B"
= "t.fifo_in1.fifo_element[3]._reset_BX" "t.fifo_in1.fifo_element[3].inack_ctl.sr_B"
= "t.fifo_in1.fifo_element[3]._reset_BX" "t.fifo_in1.fifo_element[3].inack_ctl.pr_B"
= "t.fifo_in1.fifo_element[3]._en" "t.fifo_in1.fifo_element[3].buf_func.c1"
= "t.fifo_in1.fifo_element[3]._en" "t.fifo_in1.fifo_element[3].en_ctl.y"
= "t.fifo_in1.fifo_element[3]._en" "t.fifo_in1.fifo_element[3].inack_ctl.c1"
~"t.fifo_in1.fifo_element[3].en_ctl.p1"&~"t.fifo_in1.fifo_element[3].en_ctl.c1"->"t.fifo_in1.fifo_element[3].en_ctl.y"+
"t.fifo_in1.fifo_element[3].en_ctl.c1"->"t.fifo_in1.fifo_element[3].en_ctl.y"-
= "t.fifo_in1.fifo_element[3]._out_a_B" "t.fifo_in1.fifo_element[3].buf_func.c2"
= "t.fifo_in1.fifo_element[3]._out_a_B" "t.fifo_in1.fifo_element[3].inv_outa.y"
= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[3].in.r"
= "t.fifo_in1.fifo_element[3].in.a" "t.fifo_in1.fifo_element[3].en_ctl.c1"
= "t.fifo_in1.fifo_element[3].in.a" "t.fifo_in1.fifo_element[3].inack_ctl.y"
= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[3].buf_func.n1"
= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[3].inack_ctl.c2"
= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[3].in.r"
= "t.fifo_in1.fifo_element[3].out.d.d[0]" "t.fifo_in1.fifo_element[3].out.r"
= "t.fifo_in1.fifo_element[3].out.a" "t.fifo_in1.fifo_element[3].inv_outa.a"
= "t.fifo_in1.fifo_element[3].out.d.d[0]" "t.fifo_in1.fifo_element[3].buf_func.y"
= "t.fifo_in1.fifo_element[3].out.d.d[0]" "t.fifo_in1.fifo_element[3].en_ctl.p1"
= "t.fifo_in1.fifo_element[3].out.d.d[0]" "t.fifo_in1.fifo_element[3].inack_ctl.n1"
= "t.fifo_in1.fifo_element[3].out.d.d[0]" "t.fifo_in1.fifo_element[3].out.r"
= "t.fifo_in1.fifo_element[3].in.a" "t.fifo_in1.fifo_element[2].out.a"
= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[2].out.r"
= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[2].out.d.d[0]"
= "t.fifo_in1.fifo_element[3].in.d.d[0]" "t.fifo_in1.fifo_element[3].in.r"
= "t.fifo_in1.fifo_element[2].in.a" "t.fifo_in1.fifo_element[1].out.a"
= "t.fifo_in1.fifo_element[2].in.d.d[0]" "t.fifo_in1.fifo_element[1].out.r"
= "t.fifo_in1.fifo_element[2].in.d.d[0]" "t.fifo_in1.fifo_element[1].out.d.d[0]"
= "t.fifo_in1.fifo_element[2].in.d.d[0]" "t.fifo_in1.fifo_element[2].in.r"
= "t.fifo_in1.fifo_element[1].in.a" "t.fifo_in1.fifo_element[0].out.a"
= "t.fifo_in1.fifo_element[1].in.d.d[0]" "t.fifo_in1.fifo_element[0].out.r"
= "t.fifo_in1.fifo_element[1].in.d.d[0]" "t.fifo_in1.fifo_element[0].out.d.d[0]"
= "t.fifo_in1.fifo_element[1].in.d.d[0]" "t.fifo_in1.fifo_element[1].in.r"
= "t.fifo_in1._reset_BXX[0]" "t.fifo_in1.reset_bufarray.out[0]"
= "t.fifo_in1._reset_BXX[1]" "t.fifo_in1.reset_bufarray.out[1]"
= "t.fifo_in1._reset_BXX[2]" "t.fifo_in1.reset_bufarray.out[2]"
= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1.reset_bufarray.out[3]"
= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1.fifo_element[2].reset_B"
= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1._reset_BXX[2]"
= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1.fifo_element[1].reset_B"
= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1._reset_BXX[1]"
= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1.fifo_element[0].reset_B"
= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1._reset_BXX[0]"
= "t.fifo_in1._reset_BXX[3]" "t.fifo_in1.fifo_element[3].reset_B"
= "t.fifo_in1.in.d.d[0]" "t.fifo_in1.in.r"
= "t.fifo_in1.in.a" "t.fifo_in1.fifo_element[0].in.a"
= "t.fifo_in1.in.d.d[0]" "t.fifo_in1.fifo_element[0].in.r"
= "t.fifo_in1.in.d.d[0]" "t.fifo_in1.fifo_element[0].in.d.d[0]"
= "t.fifo_in1.in.d.d[0]" "t.fifo_in1.in.r"
= "t.fifo_in1.out.d.d[0]" "t.fifo_in1.out.r"
= "t.fifo_in1.out.a" "t.fifo_in1.fifo_element[3].out.a"
= "t.fifo_in1.out.d.d[0]" "t.fifo_in1.fifo_element[3].out.r"
= "t.fifo_in1.out.d.d[0]" "t.fifo_in1.fifo_element[3].out.d.d[0]"
= "t.fifo_in1.out.d.d[0]" "t.fifo_in1.out.r"
= "Reset" "t.fifo_in1.reset_B"
= "Vdd" "t.fifo_in1.supply.vdd"
= "GND" "t.fifo_in1.supply.vss"
= "t.out.d.d[0]" "t.out.r"
= "t.out.r" "t.arb.out.r"
= "t.out.a" "t.arb.out.a"
= "t.out.d.d[0]" "t.arb.out.d.d[0]"
= "t.out.d.d[0]" "t.out.r"
= "t.in2.d.d[0]" "t.in2.r"
= "t.in2.r" "t.fifo_in2.in.r"
= "t.in2.a" "t.fifo_in2.in.a"
= "t.in2.d.d[0]" "t.fifo_in2.in.d.d[0]"
= "t.in2.d.d[0]" "t.in2.r"

52
test/unit_tests/arbiter_handshake_adv/test.act
View File

@@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_test(a1of1 in1; a1of1 in2; a1of1 out)
{
a1of1 _out1,_out2;
fifo_t<4> fifo_in1(.in = in1,.out = _out1);
fifo_t<4> fifo_in2(.in = in2,.out = _out2);
fifo_in1.supply.vdd = Vdd;
fifo_in1.supply.vss = GND;
fifo_in1.reset_B = Reset;
fifo_in2.supply.vdd = Vdd;
fifo_in2.supply.vss = GND;
fifo_in2.reset_B = Reset;
arbiter_handshake arb(.in1 = _out1, .in2 = _out2, .out = out);
arb.supply.vdd = Vdd;
arb.supply.vss = GND;
}
arbiter_test t;

45
test/unit_tests/arbiter_handshake_adv/test.prsim
View File

@@ -1,45 +0,0 @@
watchall
system "echo '[0] code starts'"
set t.in1.r 0
set t.in2.r 0
set t.out.a 0
set Reset 0
cycle
status X
mode run
set Reset 1
cycle
system "echo '[1] reset done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in1.r 1
set t.in2.r 1
cycle
assert t.out.r 1
set t.out.a 1
system "echo '----------------------------------------------------------------------------------------------------'"
system "echo '[2] 1 bit processed by the arbiter'"
cycle
set t.out.a 0
cycle
assert t.out.r 1
set t.out.a 1
set t.in1.r 0
set t.in2.r 0
system "echo '----------------------------------------------------------------------------------------------------'"
system "echo '[3] 2 bit processed by the arbiter'"
cycle
set t.out.a 0
set t.in1.r 1
set t.in2.r 1
cycle
assert t.out.r 1
set t.out.a 1
system "echo '----------------------------------------------------------------------------------------------------'"
system "echo '[4] 3 bit processed by the arbiter'"
cycle
set t.out.a 0
cycle
assert t.out.r 1
set t.out.a 1
system "echo '----------------------------------------------------------------------------------------------------'"
system "echo '[5] 4 bit processed by the arbiter'"

58
test/unit_tests/arbiter_handshake_simple/run/prsim.out
View File

@@ -1,58 +0,0 @@
t.in1.r t.in2.r t.out.r t.a.arbiter._y1 t.a.arbiter._y2 t.out.a t.in1.a t.a._y1_arb t.a._y2_arb t.in2.a t.a.or_cell._y t.a.ack_cell1._y t.a.ack_cell2._y
[0] code starts
0 t.in1.r : 0
0 t.out.a : 0
0 t.in2.r : 0
1 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
7092 t.a.arbiter._y2 : 1 [by t.in2.r:=0]
7094 t.a._y2_arb : 0 [by t.a.arbiter._y2:=1]
10468 t.a._y1_arb : 0 [by t.a.arbiter._y1:=1]
10582 t.a.or_cell._y : 1 [by t.a._y1_arb:=0]
11605 t.a.ack_cell1._y : 1 [by t.a._y1_arb:=0]
11847 t.a.ack_cell2._y : 1 [by t.a._y2_arb:=0]
11886 t.in2.a : 0 [by t.a.ack_cell2._y:=1]
13331 t.in1.a : 0 [by t.a.ack_cell1._y:=1]
75948 t.out.r : 0 [by t.a.or_cell._y:=1]
[1] reset done
----------------------------------------------------------------------------------------------------
75948 t.in1.r : 1
75963 t.a.arbiter._y1 : 0 [by t.in1.r:=1]
76454 t.a._y1_arb : 1 [by t.a.arbiter._y1:=0]
76467 t.a.or_cell._y : 0 [by t.a._y1_arb:=1]
76507 t.out.r : 1 [by t.a.or_cell._y:=0]
76507 t.out.a : 1
76922 t.a.ack_cell1._y : 0 [by t.out.a:=1]
76942 t.in1.a : 1 [by t.a.ack_cell1._y:=0]
[2] test in1 done
----------------------------------------------------------------------------------------------------
76942 t.in1.r : 0
83003 t.a.arbiter._y1 : 1 [by t.in1.r:=0]
83050 t.a._y1_arb : 0 [by t.a.arbiter._y1:=1]
83066 t.a.or_cell._y : 1 [by t.a._y1_arb:=0]
127164 t.out.r : 0 [by t.a.or_cell._y:=1]
127164 t.out.a : 0
140888 t.a.ack_cell1._y : 1 [by t.out.a:=0]
140892 t.in1.a : 0 [by t.a.ack_cell1._y:=1]
[3] reset done
----------------------------------------------------------------------------------------------------
140892 t.in2.r : 1
150021 t.a.arbiter._y2 : 0 [by t.in2.r:=1]
150036 t.a._y2_arb : 1 [by t.a.arbiter._y2:=0]
193284 t.a.or_cell._y : 0 [by t.a._y2_arb:=1]
230215 t.out.r : 1 [by t.a.or_cell._y:=0]
230215 t.out.a : 1
230270 t.a.ack_cell2._y : 0 [by t.out.a:=1]
281923 t.in2.a : 1 [by t.a.ack_cell2._y:=0]
[4] test in2 done
----------------------------------------------------------------------------------------------------
281923 t.in2.r : 0
311703 t.a.arbiter._y2 : 1 [by t.in2.r:=0]
325552 t.a._y2_arb : 0 [by t.a.arbiter._y2:=1]
350364 t.a.or_cell._y : 1 [by t.a._y2_arb:=0]
364707 t.out.r : 0 [by t.a.or_cell._y:=1]
364707 t.out.a : 0
365129 t.a.ack_cell2._y : 1 [by t.out.a:=0]
413843 t.in2.a : 0 [by t.a.ack_cell2._y:=1]
[5] reset done
----------------------------------------------------------------------------------------------------

70
test/unit_tests/arbiter_handshake_simple/run/test.prs
View File

@@ -1,70 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
= "t.a.in1.d.d[0]" "t.a.in1.r"
= "t.a.in1.a" "t.a.arbiter.d"
= "t.a.in1.a" "t.a.ack_cell1.y"
= "t.a.in1.d.d[0]" "t.a.arbiter.a"
= "t.a.in1.d.d[0]" "t.a.in1.r"
~"t.a.ack_cell1.c1"&~"t.a.ack_cell1.c2"->"t.a.ack_cell1._y"+
"t.a.ack_cell1.c1"&"t.a.ack_cell1.c2"->"t.a.ack_cell1._y"-
"t.a.ack_cell1._y"->"t.a.ack_cell1.y"-
~("t.a.ack_cell1._y")->"t.a.ack_cell1.y"+
= "t.a.in2.d.d[0]" "t.a.in2.r"
= "t.a.in2.a" "t.a.arbiter.c"
= "t.a.in2.a" "t.a.ack_cell2.y"
= "t.a.in2.d.d[0]" "t.a.arbiter.b"
= "t.a.in2.d.d[0]" "t.a.in2.r"
= "t.a.supply.vdd" "t.a.arbiter.vdd"
= "t.a.supply.vdd" "t.a.or_cell.vdd"
= "t.a.supply.vdd" "t.a.ack_cell2.vdd"
= "t.a.supply.vdd" "t.a.ack_cell1.vdd"
= "t.a.supply.vss" "t.a.arbiter.vss"
= "t.a.supply.vss" "t.a.or_cell.vss"
= "t.a.supply.vss" "t.a.ack_cell2.vss"
= "t.a.supply.vss" "t.a.ack_cell1.vss"
"t.a.arbiter.a"&"t.a.arbiter._y2"->"t.a.arbiter._y1"-
~"t.a.arbiter.a"|~"t.a.arbiter._y2"->"t.a.arbiter._y1"+
"t.a.arbiter.b"&"t.a.arbiter._y1"->"t.a.arbiter._y2"-
~"t.a.arbiter.b"|~"t.a.arbiter._y1"->"t.a.arbiter._y2"+
"t.a.arbiter._y1"|"t.a.arbiter.c"->"t.a.arbiter.y1"-
~("t.a.arbiter._y1"|"t.a.arbiter.c")->"t.a.arbiter.y1"+
"t.a.arbiter._y2"|"t.a.arbiter.d"->"t.a.arbiter.y2"-
~("t.a.arbiter._y2"|"t.a.arbiter.d")->"t.a.arbiter.y2"+
mk_excllo("t.a.arbiter._y1","t.a.arbiter._y2")
= "t.a._y1_arb" "t.a.arbiter.y1"
= "t.a._y1_arb" "t.a.or_cell.a"
= "t.a._y1_arb" "t.a.ack_cell1.c2"
~"t.a.ack_cell2.c1"&~"t.a.ack_cell2.c2"->"t.a.ack_cell2._y"+
"t.a.ack_cell2.c1"&"t.a.ack_cell2.c2"->"t.a.ack_cell2._y"-
"t.a.ack_cell2._y"->"t.a.ack_cell2.y"-
~("t.a.ack_cell2._y")->"t.a.ack_cell2.y"+
"t.a.or_cell.a"|"t.a.or_cell.b"->"t.a.or_cell._y"-
~("t.a.or_cell.a"|"t.a.or_cell.b")->"t.a.or_cell._y"+
"t.a.or_cell._y"->"t.a.or_cell.y"-
~("t.a.or_cell._y")->"t.a.or_cell.y"+
= "t.a.out.d.d[0]" "t.a.out.r"
= "t.a.out.a" "t.a.ack_cell2.c1"
= "t.a.out.a" "t.a.ack_cell1.c1"
= "t.a.out.d.d[0]" "t.a.or_cell.y"
= "t.a.out.d.d[0]" "t.a.out.r"
= "t.a._y2_arb" "t.a.arbiter.y2"
= "t.a._y2_arb" "t.a.or_cell.b"
= "t.a._y2_arb" "t.a.ack_cell2.c2"
= "Vdd" "t.a.supply.vdd"
= "GND" "t.a.supply.vss"
= "t.in1.d.d[0]" "t.in1.r"
= "t.in1.r" "t.a.in1.r"
= "t.in1.a" "t.a.in1.a"
= "t.in1.d.d[0]" "t.a.in1.d.d[0]"
= "t.in1.d.d[0]" "t.in1.r"
= "t.out.d.d[0]" "t.out.r"
= "t.out.r" "t.a.out.r"
= "t.out.a" "t.a.out.a"
= "t.out.d.d[0]" "t.a.out.d.d[0]"
= "t.out.d.d[0]" "t.out.r"
= "t.in2.d.d[0]" "t.in2.r"
= "t.in2.r" "t.a.in2.r"
= "t.in2.a" "t.a.in2.a"
= "t.in2.d.d[0]" "t.a.in2.d.d[0]"
= "t.in2.d.d[0]" "t.in2.r"

41
test/unit_tests/arbiter_handshake_simple/test.act
View File

@@ -1,41 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_test(a1of1 in1; a1of1 in2; a1of1 out)
{
arbiter_handshake a(.in1 = in1, .in2 = in2, .out = out);
a.supply.vdd = Vdd;
a.supply.vss = GND;
}
arbiter_test t;

42
test/unit_tests/arbiter_handshake_simple/test.prsim
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@@ -1,42 +0,0 @@
watchall
system "echo '[0] code starts'"
set t.in1.r 0
set t.in2.r 0
set t.out.a 0
cycle
status X
mode run
system "echo '[1] reset done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in1.r 1
cycle
assert t.out.r 1
set t.out.a 1
cycle
assert t.in1.a 1
system "echo '[2] test in1 done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in1.r 0
cycle
assert t.out.r 0
set t.out.a 0
cycle
assert t.in1.a 0
system "echo '[3] reset done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in2.r 1
cycle
assert t.out.r 1
set t.out.a 1
cycle
assert t.in2.a 1
system "echo '[4] test in2 done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in2.r 0
cycle
assert t.out.r 0
set t.out.a 0
cycle
assert t.in2.a 0
system "echo '[5] reset done'"
system "echo '----------------------------------------------------------------------------------------------------'"

98
test/unit_tests/arbiter_tree_simple_nosim/run/prsim.out
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@@ -1,98 +0,0 @@
my_tree.in[4].r my_tree.at_cell.tmp[6].r my_tree.at_cell.arbs[0].arbiter._y1 my_tree.in[2].a my_tree.at_cell.tmp[8].a my_tree.at_cell.arbs[0]._y1_arb my_tree.out.r my_tree.at_cell.tmp[5].a my_tree.at_cell.arbs[2]._y2_arb my_tree.at_cell.arbs[3].ack_cell1._y my_tree.in[0].a my_tree.at_cell.tmp[6].a my_tree.in[4].a my_tree.at_cell.arbs[2].arbiter._y2 my_tree.in[1].a my_tree.out.a my_tree.at_cell.arbs[0].ack_cell1._y my_tree.in[0].r my_tree.at_cell.arbs[3].ack_cell2._y my_tree.in[3].r my_tree.at_cell.tmp[5].r my_tree.in[1].r my_tree.at_cell.arbs[0]._y2_arb my_tree.at_cell.arbs[2].ack_cell2._y my_tree.at_cell.arbs[1]._y1_arb my_tree.at_cell.arbs[1].ack_cell2._y my_tree.in[2].r my_tree.in[3].a my_tree.at_cell.tmp[8].r my_tree.at_cell.arbs[1]._y2_arb my_tree.at_cell.arbs[3]._y1_arb my_tree.at_cell.arbs[3].or_cell._y my_tree.at_cell.arbs[1].arbiter._y2 my_tree.at_cell.arbs[3].arbiter._y2 my_tree.at_cell.arbs[1].ack_cell1._y my_tree.at_cell.arbs[3].arbiter._y1 my_tree.at_cell.arbs[0].ack_cell2._y my_tree.at_cell.arbs[3]._y2_arb my_tree.at_cell.arbs[2].ack_cell1._y my_tree.at_cell.arbs[1].or_cell._y my_tree.at_cell.arbs[2]._y1_arb my_tree.at_cell.arbs[1].arbiter._y1 my_tree.at_cell.arbs[0].or_cell._y my_tree.at_cell.arbs[0].arbiter._y2 my_tree.at_cell.arbs[2].or_cell._y my_tree.at_cell.arbs[2].arbiter._y1
1 my_tree.in[0].r : 0
1 my_tree.out.a : 0
1 my_tree.in[2].r : 0
1 my_tree.in[4].r : 0
1 my_tree.in[1].r : 0
1 my_tree.in[3].r : 0
3 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree.in[4].r:=0]
117 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
1138 my_tree.at_cell.arbs[1].arbiter._y2 : 1 [by my_tree.in[3].r:=0]
2864 my_tree.at_cell.arbs[1]._y2_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y2:=1]
4754 my_tree.at_cell.arbs[0].arbiter._y2 : 1 [by my_tree.in[1].r:=0]
4793 my_tree.at_cell.arbs[0]._y2_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y2:=1]
7093 my_tree.at_cell.arbs[0].arbiter._y1 : 1 [by my_tree.in[0].r:=0]
7108 my_tree.at_cell.arbs[0]._y1_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y1:=1]
7599 my_tree.at_cell.arbs[0].or_cell._y : 1 [by my_tree.at_cell.arbs[0]._y1_arb:=0]
7612 my_tree.at_cell.tmp[5].r : 0 [by my_tree.at_cell.arbs[0].or_cell._y:=1]
7652 my_tree.at_cell.arbs[2].arbiter._y1 : 1 [by my_tree.at_cell.tmp[5].r:=0]
8067 my_tree.at_cell.arbs[2]._y1_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
10468 my_tree.at_cell.arbs[1].arbiter._y1 : 1 [by my_tree.in[2].r:=0]
10488 my_tree.at_cell.arbs[1]._y1_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y1:=1]
16549 my_tree.at_cell.arbs[1].or_cell._y : 1 [by my_tree.at_cell.arbs[1]._y1_arb:=0]
16596 my_tree.at_cell.tmp[6].r : 0 [by my_tree.at_cell.arbs[1].or_cell._y:=1]
16612 my_tree.at_cell.arbs[2].arbiter._y2 : 1 [by my_tree.at_cell.tmp[6].r:=0]
60710 my_tree.at_cell.arbs[2]._y2_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y2:=1]
65483 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
65487 my_tree.in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
74434 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y2_arb:=0]
83563 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
83578 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
126826 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
126881 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
163757 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
178534 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
193537 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
207386 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
218349 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
218771 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
218772 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
218773 my_tree.in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
221729 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
222011 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
222779 my_tree.in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
241934 my_tree.at_cell.arbs[1].ack_cell2._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
241937 my_tree.in[3].a : 0 [by my_tree.at_cell.arbs[1].ack_cell2._y:=1]
267485 my_tree.at_cell.arbs[0].ack_cell2._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
289926 my_tree.in[1].a : 0 [by my_tree.at_cell.arbs[0].ack_cell2._y:=1]
-------------------------------------------------
[0] System initialized
289926 Reset : 0
290477 my_tree._reset_B : 1 [by Reset:=0]
-------------------------------------------------
[1] System reset completed
290477 my_tree.in[0].r : 1
290477 my_tree.in[4].r : 1
290477 my_tree.in[2].r : 1
291431 my_tree.at_cell.arbs[3].arbiter._y2 : 0 [by my_tree.in[4].r:=1]
291548 my_tree.at_cell.arbs[0].arbiter._y1 : 0 [by my_tree.in[0].r:=1]
291558 my_tree.at_cell.arbs[1].arbiter._y1 : 0 [by my_tree.in[2].r:=1]
291576 my_tree.at_cell.arbs[1]._y1_arb : 1 [by my_tree.at_cell.arbs[1].arbiter._y1:=0]
292530 my_tree.at_cell.arbs[0]._y1_arb : 1 [by my_tree.at_cell.arbs[0].arbiter._y1:=0]
295589 my_tree.at_cell.arbs[1].or_cell._y : 0 [by my_tree.at_cell.arbs[1]._y1_arb:=1]
296533 my_tree.at_cell.arbs[0].or_cell._y : 0 [by my_tree.at_cell.arbs[0]._y1_arb:=1]
318117 my_tree.at_cell.tmp[5].r : 1 [by my_tree.at_cell.arbs[0].or_cell._y:=0]
322877 my_tree.at_cell.arbs[2].arbiter._y1 : 0 [by my_tree.at_cell.tmp[5].r:=1]
323379 my_tree.at_cell.arbs[2]._y1_arb : 1 [by my_tree.at_cell.arbs[2].arbiter._y1:=0]
323582 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y1_arb:=1]
325436 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
340490 my_tree.at_cell.tmp[6].r : 1 [by my_tree.at_cell.arbs[1].or_cell._y:=0]
345901 my_tree.at_cell.arbs[3]._y2_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y2:=0]
346040 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y2_arb:=1]
382386 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
382386 my_tree.out.a : 1
382455 my_tree.at_cell.arbs[3].ack_cell2._y : 0 [by my_tree.out.a:=1]
382466 my_tree.in[4].a : 1 [by my_tree.at_cell.arbs[3].ack_cell2._y:=0]
-------------------------------------------------
[2] Number 4 was chosen, move to the next one
382466 my_tree.in[4].r : 0
434252 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree.in[4].r:=0]
434267 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
434268 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
434305 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
434456 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
434456 my_tree.out.a : 0
435195 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
435307 my_tree.in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
482819 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree.in[4].a:=0]
482859 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
483116 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
483116 my_tree.out.a : 1
483203 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
483497 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
483498 my_tree.at_cell.arbs[2].ack_cell1._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
485304 my_tree.at_cell.tmp[5].a : 1 [by my_tree.at_cell.arbs[2].ack_cell1._y:=0]
487311 my_tree.at_cell.arbs[0].ack_cell1._y : 0 [by my_tree.at_cell.tmp[5].a:=1]
488520 my_tree.in[0].a : 1 [by my_tree.at_cell.arbs[0].ack_cell1._y:=0]
-------------------------------------------------
[2] Number 0 was chosen, finish test

325
test/unit_tests/arbiter_tree_simple_nosim/run/test.prs
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@@ -1,325 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"my_tree._reset_B"-
~("Reset")->"my_tree._reset_B"+
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].in1.r"
= "my_tree.at_cell.arbs[0].in1.a" "my_tree.at_cell.arbs[0].arbiter.d"
= "my_tree.at_cell.arbs[0].in1.a" "my_tree.at_cell.arbs[0].ack_cell1.y"
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].arbiter.a"
= "my_tree.at_cell.arbs[0].in1.d.d[0]" "my_tree.at_cell.arbs[0].in1.r"
~"my_tree.at_cell.arbs[0].ack_cell1.c1"&~"my_tree.at_cell.arbs[0].ack_cell1.c2"->"my_tree.at_cell.arbs[0].ack_cell1._y"+
"my_tree.at_cell.arbs[0].ack_cell1.c1"&"my_tree.at_cell.arbs[0].ack_cell1.c2"->"my_tree.at_cell.arbs[0].ack_cell1._y"-
"my_tree.at_cell.arbs[0].ack_cell1._y"->"my_tree.at_cell.arbs[0].ack_cell1.y"-
~("my_tree.at_cell.arbs[0].ack_cell1._y")->"my_tree.at_cell.arbs[0].ack_cell1.y"+
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.arbs[0].in2.a" "my_tree.at_cell.arbs[0].arbiter.c"
= "my_tree.at_cell.arbs[0].in2.a" "my_tree.at_cell.arbs[0].ack_cell2.y"
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].arbiter.b"
= "my_tree.at_cell.arbs[0].in2.d.d[0]" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].arbiter.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].or_cell.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].ack_cell2.vdd"
= "my_tree.at_cell.arbs[0].supply.vdd" "my_tree.at_cell.arbs[0].ack_cell1.vdd"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].arbiter.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].or_cell.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].ack_cell2.vss"
= "my_tree.at_cell.arbs[0].supply.vss" "my_tree.at_cell.arbs[0].ack_cell1.vss"
"my_tree.at_cell.arbs[0].arbiter.a"&"my_tree.at_cell.arbs[0].arbiter._y2"->"my_tree.at_cell.arbs[0].arbiter._y1"-
~"my_tree.at_cell.arbs[0].arbiter.a"|~"my_tree.at_cell.arbs[0].arbiter._y2"->"my_tree.at_cell.arbs[0].arbiter._y1"+
"my_tree.at_cell.arbs[0].arbiter.b"&"my_tree.at_cell.arbs[0].arbiter._y1"->"my_tree.at_cell.arbs[0].arbiter._y2"-
~"my_tree.at_cell.arbs[0].arbiter.b"|~"my_tree.at_cell.arbs[0].arbiter._y1"->"my_tree.at_cell.arbs[0].arbiter._y2"+
"my_tree.at_cell.arbs[0].arbiter._y1"|"my_tree.at_cell.arbs[0].arbiter.c"->"my_tree.at_cell.arbs[0].arbiter.y1"-
~("my_tree.at_cell.arbs[0].arbiter._y1"|"my_tree.at_cell.arbs[0].arbiter.c")->"my_tree.at_cell.arbs[0].arbiter.y1"+
"my_tree.at_cell.arbs[0].arbiter._y2"|"my_tree.at_cell.arbs[0].arbiter.d"->"my_tree.at_cell.arbs[0].arbiter.y2"-
~("my_tree.at_cell.arbs[0].arbiter._y2"|"my_tree.at_cell.arbs[0].arbiter.d")->"my_tree.at_cell.arbs[0].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[0].arbiter._y1","my_tree.at_cell.arbs[0].arbiter._y2")
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].arbiter.y1"
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].or_cell.a"
= "my_tree.at_cell.arbs[0]._y1_arb" "my_tree.at_cell.arbs[0].ack_cell1.c2"
~"my_tree.at_cell.arbs[0].ack_cell2.c1"&~"my_tree.at_cell.arbs[0].ack_cell2.c2"->"my_tree.at_cell.arbs[0].ack_cell2._y"+
"my_tree.at_cell.arbs[0].ack_cell2.c1"&"my_tree.at_cell.arbs[0].ack_cell2.c2"->"my_tree.at_cell.arbs[0].ack_cell2._y"-
"my_tree.at_cell.arbs[0].ack_cell2._y"->"my_tree.at_cell.arbs[0].ack_cell2.y"-
~("my_tree.at_cell.arbs[0].ack_cell2._y")->"my_tree.at_cell.arbs[0].ack_cell2.y"+
"my_tree.at_cell.arbs[0].or_cell.a"|"my_tree.at_cell.arbs[0].or_cell.b"->"my_tree.at_cell.arbs[0].or_cell._y"-
~("my_tree.at_cell.arbs[0].or_cell.a"|"my_tree.at_cell.arbs[0].or_cell.b")->"my_tree.at_cell.arbs[0].or_cell._y"+
"my_tree.at_cell.arbs[0].or_cell._y"->"my_tree.at_cell.arbs[0].or_cell.y"-
~("my_tree.at_cell.arbs[0].or_cell._y")->"my_tree.at_cell.arbs[0].or_cell.y"+
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.arbs[0].out.a" "my_tree.at_cell.arbs[0].ack_cell2.c1"
= "my_tree.at_cell.arbs[0].out.a" "my_tree.at_cell.arbs[0].ack_cell1.c1"
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].or_cell.y"
= "my_tree.at_cell.arbs[0].out.d.d[0]" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].arbiter.y2"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].or_cell.b"
= "my_tree.at_cell.arbs[0]._y2_arb" "my_tree.at_cell.arbs[0].ack_cell2.c2"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].in1.r"
= "my_tree.at_cell.arbs[1].in1.a" "my_tree.at_cell.arbs[1].arbiter.d"
= "my_tree.at_cell.arbs[1].in1.a" "my_tree.at_cell.arbs[1].ack_cell1.y"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].arbiter.a"
= "my_tree.at_cell.arbs[1].in1.d.d[0]" "my_tree.at_cell.arbs[1].in1.r"
~"my_tree.at_cell.arbs[1].ack_cell1.c1"&~"my_tree.at_cell.arbs[1].ack_cell1.c2"->"my_tree.at_cell.arbs[1].ack_cell1._y"+
"my_tree.at_cell.arbs[1].ack_cell1.c1"&"my_tree.at_cell.arbs[1].ack_cell1.c2"->"my_tree.at_cell.arbs[1].ack_cell1._y"-
"my_tree.at_cell.arbs[1].ack_cell1._y"->"my_tree.at_cell.arbs[1].ack_cell1.y"-
~("my_tree.at_cell.arbs[1].ack_cell1._y")->"my_tree.at_cell.arbs[1].ack_cell1.y"+
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.arbs[1].in2.a" "my_tree.at_cell.arbs[1].arbiter.c"
= "my_tree.at_cell.arbs[1].in2.a" "my_tree.at_cell.arbs[1].ack_cell2.y"
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].arbiter.b"
= "my_tree.at_cell.arbs[1].in2.d.d[0]" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].arbiter.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].or_cell.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].ack_cell2.vdd"
= "my_tree.at_cell.arbs[1].supply.vdd" "my_tree.at_cell.arbs[1].ack_cell1.vdd"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].arbiter.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].or_cell.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].ack_cell2.vss"
= "my_tree.at_cell.arbs[1].supply.vss" "my_tree.at_cell.arbs[1].ack_cell1.vss"
"my_tree.at_cell.arbs[1].arbiter.a"&"my_tree.at_cell.arbs[1].arbiter._y2"->"my_tree.at_cell.arbs[1].arbiter._y1"-
~"my_tree.at_cell.arbs[1].arbiter.a"|~"my_tree.at_cell.arbs[1].arbiter._y2"->"my_tree.at_cell.arbs[1].arbiter._y1"+
"my_tree.at_cell.arbs[1].arbiter.b"&"my_tree.at_cell.arbs[1].arbiter._y1"->"my_tree.at_cell.arbs[1].arbiter._y2"-
~"my_tree.at_cell.arbs[1].arbiter.b"|~"my_tree.at_cell.arbs[1].arbiter._y1"->"my_tree.at_cell.arbs[1].arbiter._y2"+
"my_tree.at_cell.arbs[1].arbiter._y1"|"my_tree.at_cell.arbs[1].arbiter.c"->"my_tree.at_cell.arbs[1].arbiter.y1"-
~("my_tree.at_cell.arbs[1].arbiter._y1"|"my_tree.at_cell.arbs[1].arbiter.c")->"my_tree.at_cell.arbs[1].arbiter.y1"+
"my_tree.at_cell.arbs[1].arbiter._y2"|"my_tree.at_cell.arbs[1].arbiter.d"->"my_tree.at_cell.arbs[1].arbiter.y2"-
~("my_tree.at_cell.arbs[1].arbiter._y2"|"my_tree.at_cell.arbs[1].arbiter.d")->"my_tree.at_cell.arbs[1].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[1].arbiter._y1","my_tree.at_cell.arbs[1].arbiter._y2")
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].arbiter.y1"
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].or_cell.a"
= "my_tree.at_cell.arbs[1]._y1_arb" "my_tree.at_cell.arbs[1].ack_cell1.c2"
~"my_tree.at_cell.arbs[1].ack_cell2.c1"&~"my_tree.at_cell.arbs[1].ack_cell2.c2"->"my_tree.at_cell.arbs[1].ack_cell2._y"+
"my_tree.at_cell.arbs[1].ack_cell2.c1"&"my_tree.at_cell.arbs[1].ack_cell2.c2"->"my_tree.at_cell.arbs[1].ack_cell2._y"-
"my_tree.at_cell.arbs[1].ack_cell2._y"->"my_tree.at_cell.arbs[1].ack_cell2.y"-
~("my_tree.at_cell.arbs[1].ack_cell2._y")->"my_tree.at_cell.arbs[1].ack_cell2.y"+
"my_tree.at_cell.arbs[1].or_cell.a"|"my_tree.at_cell.arbs[1].or_cell.b"->"my_tree.at_cell.arbs[1].or_cell._y"-
~("my_tree.at_cell.arbs[1].or_cell.a"|"my_tree.at_cell.arbs[1].or_cell.b")->"my_tree.at_cell.arbs[1].or_cell._y"+
"my_tree.at_cell.arbs[1].or_cell._y"->"my_tree.at_cell.arbs[1].or_cell.y"-
~("my_tree.at_cell.arbs[1].or_cell._y")->"my_tree.at_cell.arbs[1].or_cell.y"+
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.arbs[1].out.a" "my_tree.at_cell.arbs[1].ack_cell2.c1"
= "my_tree.at_cell.arbs[1].out.a" "my_tree.at_cell.arbs[1].ack_cell1.c1"
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].or_cell.y"
= "my_tree.at_cell.arbs[1].out.d.d[0]" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].arbiter.y2"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].or_cell.b"
= "my_tree.at_cell.arbs[1]._y2_arb" "my_tree.at_cell.arbs[1].ack_cell2.c2"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].in1.r"
= "my_tree.at_cell.arbs[2].in1.a" "my_tree.at_cell.arbs[2].arbiter.d"
= "my_tree.at_cell.arbs[2].in1.a" "my_tree.at_cell.arbs[2].ack_cell1.y"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].arbiter.a"
= "my_tree.at_cell.arbs[2].in1.d.d[0]" "my_tree.at_cell.arbs[2].in1.r"
~"my_tree.at_cell.arbs[2].ack_cell1.c1"&~"my_tree.at_cell.arbs[2].ack_cell1.c2"->"my_tree.at_cell.arbs[2].ack_cell1._y"+
"my_tree.at_cell.arbs[2].ack_cell1.c1"&"my_tree.at_cell.arbs[2].ack_cell1.c2"->"my_tree.at_cell.arbs[2].ack_cell1._y"-
"my_tree.at_cell.arbs[2].ack_cell1._y"->"my_tree.at_cell.arbs[2].ack_cell1.y"-
~("my_tree.at_cell.arbs[2].ack_cell1._y")->"my_tree.at_cell.arbs[2].ack_cell1.y"+
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.arbs[2].in2.a" "my_tree.at_cell.arbs[2].arbiter.c"
= "my_tree.at_cell.arbs[2].in2.a" "my_tree.at_cell.arbs[2].ack_cell2.y"
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].arbiter.b"
= "my_tree.at_cell.arbs[2].in2.d.d[0]" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].arbiter.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].or_cell.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].ack_cell2.vdd"
= "my_tree.at_cell.arbs[2].supply.vdd" "my_tree.at_cell.arbs[2].ack_cell1.vdd"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].arbiter.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].or_cell.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].ack_cell2.vss"
= "my_tree.at_cell.arbs[2].supply.vss" "my_tree.at_cell.arbs[2].ack_cell1.vss"
"my_tree.at_cell.arbs[2].arbiter.a"&"my_tree.at_cell.arbs[2].arbiter._y2"->"my_tree.at_cell.arbs[2].arbiter._y1"-
~"my_tree.at_cell.arbs[2].arbiter.a"|~"my_tree.at_cell.arbs[2].arbiter._y2"->"my_tree.at_cell.arbs[2].arbiter._y1"+
"my_tree.at_cell.arbs[2].arbiter.b"&"my_tree.at_cell.arbs[2].arbiter._y1"->"my_tree.at_cell.arbs[2].arbiter._y2"-
~"my_tree.at_cell.arbs[2].arbiter.b"|~"my_tree.at_cell.arbs[2].arbiter._y1"->"my_tree.at_cell.arbs[2].arbiter._y2"+
"my_tree.at_cell.arbs[2].arbiter._y1"|"my_tree.at_cell.arbs[2].arbiter.c"->"my_tree.at_cell.arbs[2].arbiter.y1"-
~("my_tree.at_cell.arbs[2].arbiter._y1"|"my_tree.at_cell.arbs[2].arbiter.c")->"my_tree.at_cell.arbs[2].arbiter.y1"+
"my_tree.at_cell.arbs[2].arbiter._y2"|"my_tree.at_cell.arbs[2].arbiter.d"->"my_tree.at_cell.arbs[2].arbiter.y2"-
~("my_tree.at_cell.arbs[2].arbiter._y2"|"my_tree.at_cell.arbs[2].arbiter.d")->"my_tree.at_cell.arbs[2].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[2].arbiter._y1","my_tree.at_cell.arbs[2].arbiter._y2")
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].arbiter.y1"
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].or_cell.a"
= "my_tree.at_cell.arbs[2]._y1_arb" "my_tree.at_cell.arbs[2].ack_cell1.c2"
~"my_tree.at_cell.arbs[2].ack_cell2.c1"&~"my_tree.at_cell.arbs[2].ack_cell2.c2"->"my_tree.at_cell.arbs[2].ack_cell2._y"+
"my_tree.at_cell.arbs[2].ack_cell2.c1"&"my_tree.at_cell.arbs[2].ack_cell2.c2"->"my_tree.at_cell.arbs[2].ack_cell2._y"-
"my_tree.at_cell.arbs[2].ack_cell2._y"->"my_tree.at_cell.arbs[2].ack_cell2.y"-
~("my_tree.at_cell.arbs[2].ack_cell2._y")->"my_tree.at_cell.arbs[2].ack_cell2.y"+
"my_tree.at_cell.arbs[2].or_cell.a"|"my_tree.at_cell.arbs[2].or_cell.b"->"my_tree.at_cell.arbs[2].or_cell._y"-
~("my_tree.at_cell.arbs[2].or_cell.a"|"my_tree.at_cell.arbs[2].or_cell.b")->"my_tree.at_cell.arbs[2].or_cell._y"+
"my_tree.at_cell.arbs[2].or_cell._y"->"my_tree.at_cell.arbs[2].or_cell.y"-
~("my_tree.at_cell.arbs[2].or_cell._y")->"my_tree.at_cell.arbs[2].or_cell.y"+
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.arbs[2].out.a" "my_tree.at_cell.arbs[2].ack_cell2.c1"
= "my_tree.at_cell.arbs[2].out.a" "my_tree.at_cell.arbs[2].ack_cell1.c1"
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].or_cell.y"
= "my_tree.at_cell.arbs[2].out.d.d[0]" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].arbiter.y2"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].or_cell.b"
= "my_tree.at_cell.arbs[2]._y2_arb" "my_tree.at_cell.arbs[2].ack_cell2.c2"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].in1.r"
= "my_tree.at_cell.arbs[3].in1.a" "my_tree.at_cell.arbs[3].arbiter.d"
= "my_tree.at_cell.arbs[3].in1.a" "my_tree.at_cell.arbs[3].ack_cell1.y"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].arbiter.a"
= "my_tree.at_cell.arbs[3].in1.d.d[0]" "my_tree.at_cell.arbs[3].in1.r"
~"my_tree.at_cell.arbs[3].ack_cell1.c1"&~"my_tree.at_cell.arbs[3].ack_cell1.c2"->"my_tree.at_cell.arbs[3].ack_cell1._y"+
"my_tree.at_cell.arbs[3].ack_cell1.c1"&"my_tree.at_cell.arbs[3].ack_cell1.c2"->"my_tree.at_cell.arbs[3].ack_cell1._y"-
"my_tree.at_cell.arbs[3].ack_cell1._y"->"my_tree.at_cell.arbs[3].ack_cell1.y"-
~("my_tree.at_cell.arbs[3].ack_cell1._y")->"my_tree.at_cell.arbs[3].ack_cell1.y"+
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.arbs[3].in2.a" "my_tree.at_cell.arbs[3].arbiter.c"
= "my_tree.at_cell.arbs[3].in2.a" "my_tree.at_cell.arbs[3].ack_cell2.y"
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].arbiter.b"
= "my_tree.at_cell.arbs[3].in2.d.d[0]" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].arbiter.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].or_cell.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].ack_cell2.vdd"
= "my_tree.at_cell.arbs[3].supply.vdd" "my_tree.at_cell.arbs[3].ack_cell1.vdd"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].arbiter.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].or_cell.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].ack_cell2.vss"
= "my_tree.at_cell.arbs[3].supply.vss" "my_tree.at_cell.arbs[3].ack_cell1.vss"
"my_tree.at_cell.arbs[3].arbiter.a"&"my_tree.at_cell.arbs[3].arbiter._y2"->"my_tree.at_cell.arbs[3].arbiter._y1"-
~"my_tree.at_cell.arbs[3].arbiter.a"|~"my_tree.at_cell.arbs[3].arbiter._y2"->"my_tree.at_cell.arbs[3].arbiter._y1"+
"my_tree.at_cell.arbs[3].arbiter.b"&"my_tree.at_cell.arbs[3].arbiter._y1"->"my_tree.at_cell.arbs[3].arbiter._y2"-
~"my_tree.at_cell.arbs[3].arbiter.b"|~"my_tree.at_cell.arbs[3].arbiter._y1"->"my_tree.at_cell.arbs[3].arbiter._y2"+
"my_tree.at_cell.arbs[3].arbiter._y1"|"my_tree.at_cell.arbs[3].arbiter.c"->"my_tree.at_cell.arbs[3].arbiter.y1"-
~("my_tree.at_cell.arbs[3].arbiter._y1"|"my_tree.at_cell.arbs[3].arbiter.c")->"my_tree.at_cell.arbs[3].arbiter.y1"+
"my_tree.at_cell.arbs[3].arbiter._y2"|"my_tree.at_cell.arbs[3].arbiter.d"->"my_tree.at_cell.arbs[3].arbiter.y2"-
~("my_tree.at_cell.arbs[3].arbiter._y2"|"my_tree.at_cell.arbs[3].arbiter.d")->"my_tree.at_cell.arbs[3].arbiter.y2"+
mk_excllo("my_tree.at_cell.arbs[3].arbiter._y1","my_tree.at_cell.arbs[3].arbiter._y2")
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].arbiter.y1"
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].or_cell.a"
= "my_tree.at_cell.arbs[3]._y1_arb" "my_tree.at_cell.arbs[3].ack_cell1.c2"
~"my_tree.at_cell.arbs[3].ack_cell2.c1"&~"my_tree.at_cell.arbs[3].ack_cell2.c2"->"my_tree.at_cell.arbs[3].ack_cell2._y"+
"my_tree.at_cell.arbs[3].ack_cell2.c1"&"my_tree.at_cell.arbs[3].ack_cell2.c2"->"my_tree.at_cell.arbs[3].ack_cell2._y"-
"my_tree.at_cell.arbs[3].ack_cell2._y"->"my_tree.at_cell.arbs[3].ack_cell2.y"-
~("my_tree.at_cell.arbs[3].ack_cell2._y")->"my_tree.at_cell.arbs[3].ack_cell2.y"+
"my_tree.at_cell.arbs[3].or_cell.a"|"my_tree.at_cell.arbs[3].or_cell.b"->"my_tree.at_cell.arbs[3].or_cell._y"-
~("my_tree.at_cell.arbs[3].or_cell.a"|"my_tree.at_cell.arbs[3].or_cell.b")->"my_tree.at_cell.arbs[3].or_cell._y"+
"my_tree.at_cell.arbs[3].or_cell._y"->"my_tree.at_cell.arbs[3].or_cell.y"-
~("my_tree.at_cell.arbs[3].or_cell._y")->"my_tree.at_cell.arbs[3].or_cell.y"+
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.arbs[3].out.a" "my_tree.at_cell.arbs[3].ack_cell2.c1"
= "my_tree.at_cell.arbs[3].out.a" "my_tree.at_cell.arbs[3].ack_cell1.c1"
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].or_cell.y"
= "my_tree.at_cell.arbs[3].out.d.d[0]" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].arbiter.y2"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].or_cell.b"
= "my_tree.at_cell.arbs[3]._y2_arb" "my_tree.at_cell.arbs[3].ack_cell2.c2"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.tmp[5].r"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.tmp[6].r"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.tmp[8].r"
= "my_tree.at_cell.tmp[5].r" "my_tree.at_cell.arbs[2].in1.r"
= "my_tree.at_cell.tmp[5].a" "my_tree.at_cell.arbs[2].in1.a"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.arbs[2].in1.d.d[0]"
= "my_tree.at_cell.tmp[5].r" "my_tree.at_cell.arbs[0].out.r"
= "my_tree.at_cell.tmp[5].a" "my_tree.at_cell.arbs[0].out.a"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.arbs[0].out.d.d[0]"
= "my_tree.at_cell.tmp[6].r" "my_tree.at_cell.arbs[2].in2.r"
= "my_tree.at_cell.tmp[6].a" "my_tree.at_cell.arbs[2].in2.a"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.arbs[2].in2.d.d[0]"
= "my_tree.at_cell.tmp[6].r" "my_tree.at_cell.arbs[1].out.r"
= "my_tree.at_cell.tmp[6].a" "my_tree.at_cell.arbs[1].out.a"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.arbs[1].out.d.d[0]"
= "my_tree.at_cell.tmp[8].r" "my_tree.at_cell.arbs[3].in1.r"
= "my_tree.at_cell.tmp[8].a" "my_tree.at_cell.arbs[3].in1.a"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.arbs[3].in1.d.d[0]"
= "my_tree.at_cell.tmp[8].r" "my_tree.at_cell.arbs[2].out.r"
= "my_tree.at_cell.tmp[8].a" "my_tree.at_cell.arbs[2].out.a"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.arbs[2].out.d.d[0]"
= "my_tree.at_cell.tmp[8].d.d[0]" "my_tree.at_cell.tmp[8].r"
= "my_tree.at_cell.tmp[6].d.d[0]" "my_tree.at_cell.tmp[6].r"
= "my_tree.at_cell.tmp[5].d.d[0]" "my_tree.at_cell.tmp[5].r"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[3].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[3].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[2].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[2].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[1].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[1].supply.vdd"
= "my_tree.at_cell.supply.vss" "my_tree.at_cell.arbs[0].supply.vss"
= "my_tree.at_cell.supply.vdd" "my_tree.at_cell.arbs[0].supply.vdd"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.in[0].r"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.in[1].r"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.in[2].r"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.in[3].r"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.in[4].r"
= "my_tree.at_cell.in[0].r" "my_tree.at_cell.arbs[0].in1.r"
= "my_tree.at_cell.in[0].a" "my_tree.at_cell.arbs[0].in1.a"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.arbs[0].in1.d.d[0]"
= "my_tree.at_cell.in[0].r" "my_tree.at_cell.tmp[0].r"
= "my_tree.at_cell.in[0].a" "my_tree.at_cell.tmp[0].a"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.tmp[0].d.d[0]"
= "my_tree.at_cell.in[1].r" "my_tree.at_cell.arbs[0].in2.r"
= "my_tree.at_cell.in[1].a" "my_tree.at_cell.arbs[0].in2.a"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.arbs[0].in2.d.d[0]"
= "my_tree.at_cell.in[1].r" "my_tree.at_cell.tmp[1].r"
= "my_tree.at_cell.in[1].a" "my_tree.at_cell.tmp[1].a"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.tmp[1].d.d[0]"
= "my_tree.at_cell.in[2].r" "my_tree.at_cell.arbs[1].in1.r"
= "my_tree.at_cell.in[2].a" "my_tree.at_cell.arbs[1].in1.a"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.arbs[1].in1.d.d[0]"
= "my_tree.at_cell.in[2].r" "my_tree.at_cell.tmp[2].r"
= "my_tree.at_cell.in[2].a" "my_tree.at_cell.tmp[2].a"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.tmp[2].d.d[0]"
= "my_tree.at_cell.in[3].r" "my_tree.at_cell.arbs[1].in2.r"
= "my_tree.at_cell.in[3].a" "my_tree.at_cell.arbs[1].in2.a"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.arbs[1].in2.d.d[0]"
= "my_tree.at_cell.in[3].r" "my_tree.at_cell.tmp[3].r"
= "my_tree.at_cell.in[3].a" "my_tree.at_cell.tmp[3].a"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.tmp[3].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.arbs[3].in2.r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.arbs[3].in2.a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.arbs[3].in2.d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[9].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[9].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[9].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[7].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[7].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[7].d.d[0]"
= "my_tree.at_cell.in[4].r" "my_tree.at_cell.tmp[4].r"
= "my_tree.at_cell.in[4].a" "my_tree.at_cell.tmp[4].a"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.tmp[4].d.d[0]"
= "my_tree.at_cell.in[4].d.d[0]" "my_tree.at_cell.in[4].r"
= "my_tree.at_cell.in[3].d.d[0]" "my_tree.at_cell.in[3].r"
= "my_tree.at_cell.in[2].d.d[0]" "my_tree.at_cell.in[2].r"
= "my_tree.at_cell.in[1].d.d[0]" "my_tree.at_cell.in[1].r"
= "my_tree.at_cell.in[0].d.d[0]" "my_tree.at_cell.in[0].r"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.out.r"
= "my_tree.at_cell.out.r" "my_tree.at_cell.arbs[3].out.r"
= "my_tree.at_cell.out.a" "my_tree.at_cell.arbs[3].out.a"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.arbs[3].out.d.d[0]"
= "my_tree.at_cell.out.r" "my_tree.at_cell.tmp[10].r"
= "my_tree.at_cell.out.a" "my_tree.at_cell.tmp[10].a"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.tmp[10].d.d[0]"
= "my_tree.at_cell.out.d.d[0]" "my_tree.at_cell.out.r"
= "my_tree._supply.vss" "my_tree.at_cell.supply.vss"
= "my_tree._supply.vdd" "my_tree.at_cell.supply.vdd"
= "Vdd" "my_tree._supply.vdd"
= "GND" "my_tree._supply.vss"
= "my_tree.out.d.d[0]" "my_tree.out.r"
= "my_tree.out.r" "my_tree.at_cell.out.r"
= "my_tree.out.a" "my_tree.at_cell.out.a"
= "my_tree.out.d.d[0]" "my_tree.at_cell.out.d.d[0]"
= "my_tree.out.d.d[0]" "my_tree.out.r"
= "my_tree.in[0].d.d[0]" "my_tree.in[0].r"
= "my_tree.in[1].d.d[0]" "my_tree.in[1].r"
= "my_tree.in[2].d.d[0]" "my_tree.in[2].r"
= "my_tree.in[3].d.d[0]" "my_tree.in[3].r"
= "my_tree.in[4].d.d[0]" "my_tree.in[4].r"
= "my_tree.in[0].r" "my_tree.at_cell.in[0].r"
= "my_tree.in[1].r" "my_tree.at_cell.in[1].r"
= "my_tree.in[2].r" "my_tree.at_cell.in[2].r"
= "my_tree.in[3].r" "my_tree.at_cell.in[3].r"
= "my_tree.in[4].r" "my_tree.at_cell.in[4].r"
= "my_tree.in[0].a" "my_tree.at_cell.in[0].a"
= "my_tree.in[1].a" "my_tree.at_cell.in[1].a"
= "my_tree.in[2].a" "my_tree.at_cell.in[2].a"
= "my_tree.in[3].a" "my_tree.at_cell.in[3].a"
= "my_tree.in[4].a" "my_tree.at_cell.in[4].a"
= "my_tree.in[0].d.d[0]" "my_tree.at_cell.in[0].d.d[0]"
= "my_tree.in[1].d.d[0]" "my_tree.at_cell.in[1].d.d[0]"
= "my_tree.in[2].d.d[0]" "my_tree.at_cell.in[2].d.d[0]"
= "my_tree.in[3].d.d[0]" "my_tree.at_cell.in[3].d.d[0]"
= "my_tree.in[4].d.d[0]" "my_tree.at_cell.in[4].d.d[0]"
= "my_tree.in[4].d.d[0]" "my_tree.in[4].r"
= "my_tree.in[3].d.d[0]" "my_tree.in[3].r"
= "my_tree.in[2].d.d[0]" "my_tree.in[2].r"
= "my_tree.in[1].d.d[0]" "my_tree.in[1].r"
= "my_tree.in[0].d.d[0]" "my_tree.in[0].r"

55
test/unit_tests/arbiter_tree_simple_nosim/test.act
View File

@@ -1,55 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_treee (a1of1 in[5]; a1of1 out)
{
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
power _supply;
_supply.vdd = Vdd;
_supply.vss = GND;
arbtree<5> at_cell(.in=in, .out = out);
at_cell.supply = _supply;
}
arbiter_treee my_tree;

52
test/unit_tests/arbiter_tree_simple_nosim/test.prsim
View File

@@ -1,52 +0,0 @@
watchall
set my_tree.in[0].r 0
set my_tree.in[1].r 0
set my_tree.in[2].r 0
set my_tree.in[3].r 0
set my_tree.in[4].r 0
set my_tree.out.a 0
cycle
assert my_tree.in[0].a 0
assert my_tree.in[1].a 0
assert my_tree.in[2].a 0
assert my_tree.in[3].a 0
assert my_tree.in[4].a 0
assert my_tree.out.r 0
system "echo '-------------------------------------------------'"
system "echo '[0] System initialized'"
set Reset 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[1] System reset completed'"
set my_tree.in[0].r 1
set my_tree.in[2].r 1
set my_tree.in[4].r 1
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.in[4].a 1
set my_tree.in[4].r 0
system "echo '-------------------------------------------------'"
system "echo '[2] Number 4 was chosen, move to the next one'"
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.in[4].a 0
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.in[0].a 1
system "echo '-------------------------------------------------'"
system "echo '[2] Number 0 was chosen, finish test'"

232
test/unit_tests/arbiter_tree_test/run/prsim.out
View File

@@ -1,232 +0,0 @@
my_tree.in[1].r my_tree.at_cell.tmp[8].a my_tree.in[3].r my_tree.at_cell.tmp[5].a my_tree.at_cell.arbs[3].ack_cell1._y my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B my_tree._in[1].a my_tree.fifo_to_tree[3].fifo_element[1]._out_a_B my_tree._in[3].a my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B my_tree._in[2].a my_tree.at_cell.arbs[2].ack_cell2._y my_tree.at_cell.arbs[1].ack_cell2._y my_tree._in[4].a my_tree.out.a my_tree._in[0].a my_tree.at_cell.arbs[1].ack_cell1._y my_tree.at_cell.tmp[6].a my_tree.in[2].r my_tree.in[4].r my_tree.at_cell.arbs[2].ack_cell1._y my_tree.in[0].r my_tree.fifo_to_tree[1].fifo_element[1]._out_a_B my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B my_tree.at_cell.arbs[0].ack_cell1._y my_tree.at_cell.arbs[3].ack_cell2._y my_tree.at_cell.arbs[0].ack_cell2._y
217204 my_tree.in[0].r : 0
217204 my_tree.out.a : 0
217204 my_tree.in[4].r : 0
217204 my_tree.in[2].r : 0
217204 my_tree.in[1].r : 0
217204 my_tree.in[3].r : 0
217205 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
217216 my_tree._in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
217586 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 1 [by my_tree._in[4].a:=0]
217752 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
217819 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
217835 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
220460 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
220988 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
222397 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
223423 my_tree.at_cell.arbs[1].ack_cell2._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
223425 my_tree._in[3].a : 0 [by my_tree.at_cell.arbs[1].ack_cell2._y:=1]
235438 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
235441 my_tree._in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
235470 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 1 [by my_tree._in[0].a:=0]
246322 my_tree.at_cell.arbs[0].ack_cell2._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
246639 my_tree._in[1].a : 0 [by my_tree.at_cell.arbs[0].ack_cell2._y:=1]
247868 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
248021 my_tree._in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
248065 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 1 [by my_tree._in[2].a:=0]
248240 my_tree.fifo_to_tree[1].fifo_element[1]._out_a_B : 1 [by my_tree._in[1].a:=0]
284383 my_tree.fifo_to_tree[3].fifo_element[1]._out_a_B : 1 [by my_tree._in[3].a:=0]
-------------------------------------------------
[0] System initialized
284383 Reset : 0
287144 my_tree._reset_B : 1 [by Reset:=0]
287145 my_tree.fifo_to_tree[3].reset_buf._y : 0 [by my_tree._reset_B:=1]
287145 my_tree.fifo_to_tree[0].reset_buf._y : 0 [by my_tree._reset_B:=1]
287166 my_tree.fifo_to_tree[1].reset_buf._y : 0 [by my_tree._reset_B:=1]
287325 my_tree.fifo_to_tree[1]._reset_BX : 1 [by my_tree.fifo_to_tree[1].reset_buf._y:=0]
287361 my_tree.fifo_to_tree[2].reset_buf._y : 0 [by my_tree._reset_B:=1]
288648 my_tree.fifo_to_tree[2]._reset_BX : 1 [by my_tree.fifo_to_tree[2].reset_buf._y:=0]
288726 my_tree.fifo_to_tree[3]._reset_BX : 1 [by my_tree.fifo_to_tree[3].reset_buf._y:=0]
288871 my_tree.fifo_to_tree[3].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[3]._reset_BX:=1]
290880 my_tree.fifo_to_tree[2].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[2]._reset_BX:=1]
291703 my_tree.fifo_to_tree[3]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[3].reset_bufarray.buf1._y:=0]
291704 my_tree.fifo_to_tree[3].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[3]._reset_BXX[0]:=1]
291866 my_tree.fifo_to_tree[3].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[3].fifo_element[0].reset_buf._y:=0]
296490 my_tree.fifo_to_tree[0]._reset_BX : 1 [by my_tree.fifo_to_tree[0].reset_buf._y:=0]
297234 my_tree.fifo_to_tree[2]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[2].reset_bufarray.buf1._y:=0]
297241 my_tree.fifo_to_tree[2].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[2]._reset_BXX[0]:=1]
297248 my_tree.fifo_to_tree[2].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[2]._reset_BXX[0]:=1]
297401 my_tree.fifo_to_tree[2].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].reset_buf._y:=0]
300827 my_tree.fifo_to_tree[4].reset_buf._y : 0 [by my_tree._reset_B:=1]
300828 my_tree.fifo_to_tree[4]._reset_BX : 1 [by my_tree.fifo_to_tree[4].reset_buf._y:=0]
300829 my_tree.fifo_to_tree[4].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[4]._reset_BX:=1]
300830 my_tree.fifo_to_tree[4]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[4].reset_bufarray.buf1._y:=0]
301017 my_tree.fifo_to_tree[4].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[4]._reset_BXX[0]:=1]
301018 my_tree.fifo_to_tree[4].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].reset_buf._y:=0]
303073 my_tree.fifo_to_tree[4].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[4]._reset_BXX[0]:=1]
303859 my_tree.fifo_to_tree[0].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[0]._reset_BX:=1]
307001 my_tree.fifo_to_tree[1].reset_bufarray.buf1._y : 0 [by my_tree.fifo_to_tree[1]._reset_BX:=1]
307002 my_tree.fifo_to_tree[1]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[1].reset_bufarray.buf1._y:=0]
307007 my_tree.fifo_to_tree[1].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[1]._reset_BXX[0]:=1]
307255 my_tree.fifo_to_tree[4].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].reset_buf._y:=0]
307855 my_tree.fifo_to_tree[1].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[1]._reset_BXX[0]:=1]
307856 my_tree.fifo_to_tree[1].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[1].fifo_element[0].reset_buf._y:=0]
307898 my_tree.fifo_to_tree[1].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[1].fifo_element[1].reset_buf._y:=0]
318805 my_tree.fifo_to_tree[2].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].reset_buf._y:=0]
330987 my_tree.fifo_to_tree[3].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[3]._reset_BXX[0]:=1]
331004 my_tree.fifo_to_tree[3].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[3].fifo_element[1].reset_buf._y:=0]
338641 my_tree.fifo_to_tree[0]._reset_BXX[0] : 1 [by my_tree.fifo_to_tree[0].reset_bufarray.buf1._y:=0]
341214 my_tree.fifo_to_tree[0].fifo_element[0].reset_buf._y : 0 [by my_tree.fifo_to_tree[0]._reset_BXX[0]:=1]
341217 my_tree.fifo_to_tree[0].fifo_element[0]._reset_BX : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].reset_buf._y:=0]
347002 my_tree.fifo_to_tree[0].fifo_element[1].reset_buf._y : 0 [by my_tree.fifo_to_tree[0]._reset_BXX[0]:=1]
347943 my_tree.fifo_to_tree[0].fifo_element[1]._reset_BX : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].reset_buf._y:=0]
-------------------------------------------------
[1] System reset completed
347943 my_tree.in[0].r : 1
347943 my_tree.in[4].r : 1
347943 my_tree.in[2].r : 1
347944 my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y : 0 [by my_tree.in[4].r:=1]
347985 my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y : 0 [by my_tree.in[2].r:=1]
350761 my_tree.fifo_to_tree[4].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y:=0]
350856 my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=1]
350864 my_tree._in[4].r : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y:=0]
350898 my_tree.at_cell.arbs[3].arbiter._y2 : 0 [by my_tree._in[4].r:=1]
351096 my_tree.fifo_to_tree[4].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=1]
351100 my_tree.in[4].a : 1 [by my_tree.fifo_to_tree[4].fifo_element[0].inack_ctl._y:=0]
351816 my_tree.at_cell.arbs[3]._y2_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y2:=0]
354214 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y2_arb:=1]
357429 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
361718 my_tree.fifo_to_tree[2].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y:=0]
361766 my_tree.fifo_to_tree[2].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.r:=1]
361769 my_tree.in[2].a : 1 [by my_tree.fifo_to_tree[2].fifo_element[0].inack_ctl._y:=0]
361947 my_tree.fifo_to_tree[2].fifo_element[0]._en : 0 [by my_tree.in[2].a:=1]
364751 my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[4].r:=1]
385728 my_tree.fifo_to_tree[4].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y:=0]
391679 my_tree.fifo_to_tree[4].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=1]
397478 my_tree.fifo_to_tree[4].fifo_element[0]._en : 0 [by my_tree.in[4].a:=1]
397627 my_tree.fifo_to_tree[4].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=1]
406905 my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y : 0 [by my_tree.in[0].r:=1]
407732 my_tree.fifo_to_tree[0].fifo_element[1].in.r : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y:=0]
407905 my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=1]
407906 my_tree._in[0].r : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y:=0]
407910 my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[0].r:=1]
407916 my_tree.fifo_to_tree[0].fifo_element[0].inack_ctl._y : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=1]
407979 my_tree.at_cell.arbs[0].arbiter._y1 : 0 [by my_tree._in[0].r:=1]
408012 my_tree.in[0].a : 1 [by my_tree.fifo_to_tree[0].fifo_element[0].inack_ctl._y:=0]
408013 my_tree.fifo_to_tree[0].fifo_element[0]._en : 0 [by my_tree.in[0].a:=1]
408115 my_tree.at_cell.arbs[0]._y1_arb : 1 [by my_tree.at_cell.arbs[0].arbiter._y1:=0]
408837 my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.r:=1]
409078 my_tree._in[2].r : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y:=0]
409090 my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y : 0 [by my_tree._in[2].r:=1]
412990 my_tree.fifo_to_tree[2].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y:=0]
412991 my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=1]
413037 my_tree.at_cell.arbs[1].arbiter._y1 : 0 [by my_tree._in[2].r:=1]
413047 my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B:=0]
413048 my_tree.fifo_to_tree[2].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[2].fifo_element[0].buf_func._y:=1]
414019 my_tree.fifo_to_tree[2].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=1]
414056 my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[1]._en:=0]
427161 my_tree.at_cell.arbs[0].or_cell._y : 0 [by my_tree.at_cell.arbs[0]._y1_arb:=1]
427162 my_tree.at_cell.tmp[5].r : 1 [by my_tree.at_cell.arbs[0].or_cell._y:=0]
430726 my_tree.at_cell.arbs[2].arbiter._y1 : 0 [by my_tree.at_cell.tmp[5].r:=1]
432418 my_tree.at_cell.arbs[2]._y1_arb : 1 [by my_tree.at_cell.arbs[2].arbiter._y1:=0]
432431 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y1_arb:=1]
436963 my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[0]._en:=0]
437320 my_tree.fifo_to_tree[4].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[4].fifo_element[0].buf_func._y:=1]
437345 my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].in.r:=0]
437366 my_tree.fifo_to_tree[4].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].inack_ctl._y:=1]
437367 my_tree.fifo_to_tree[4].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[4].fifo_element[1].in.a:=0]
437431 my_tree.fifo_to_tree[2].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].inack_ctl._y:=1]
445198 my_tree.fifo_to_tree[0].fifo_element[1].in.a : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y:=0]
445199 my_tree.fifo_to_tree[0].fifo_element[1]._en : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=1]
445199 my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=1]
445360 my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B:=0]
446397 my_tree.fifo_to_tree[0].fifo_element[1].in.r : 0 [by my_tree.fifo_to_tree[0].fifo_element[0].buf_func._y:=1]
446402 my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].in.r:=0]
446983 my_tree.fifo_to_tree[0].fifo_element[1].in.a : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].inack_ctl._y:=1]
447079 my_tree.fifo_to_tree[2].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[2].fifo_element[1].in.a:=0]
447391 my_tree.fifo_to_tree[0].fifo_element[0]._out_a_B : 1 [by my_tree.fifo_to_tree[0].fifo_element[1].in.a:=0]
449415 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
458043 my_tree.at_cell.arbs[1]._y1_arb : 1 [by my_tree.at_cell.arbs[1].arbiter._y1:=0]
458054 my_tree.at_cell.arbs[1].or_cell._y : 0 [by my_tree.at_cell.arbs[1]._y1_arb:=1]
459101 my_tree.at_cell.tmp[6].r : 1 [by my_tree.at_cell.arbs[1].or_cell._y:=0]
459101 my_tree.out.a : 1
459115 my_tree.at_cell.arbs[3].ack_cell2._y : 0 [by my_tree.out.a:=1]
459133 my_tree._in[4].a : 1 [by my_tree.at_cell.arbs[3].ack_cell2._y:=0]
459137 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 0 [by my_tree._in[4].a:=1]
459241 my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B:=0]
490685 my_tree._in[4].r : 0 [by my_tree.fifo_to_tree[4].fifo_element[1].buf_func._y:=1]
491889 my_tree.at_cell.arbs[3].arbiter._y2 : 1 [by my_tree._in[4].r:=0]
492117 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
492732 my_tree.at_cell.arbs[3]._y2_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y2:=1]
494191 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y2_arb:=0]
494261 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
499140 my_tree.fifo_to_tree[4].fifo_element[1]._en : 1 [by my_tree._in[4].r:=0]
499140 my_tree.out.a : 0
549562 my_tree.at_cell.arbs[3].ack_cell2._y : 1 [by my_tree.out.a:=0]
549573 my_tree._in[4].a : 0 [by my_tree.at_cell.arbs[3].ack_cell2._y:=1]
549576 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree._in[4].a:=0]
549627 my_tree.fifo_to_tree[4].fifo_element[1]._out_a_B : 1 [by my_tree._in[4].a:=0]
550724 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
551885 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
551885 my_tree.out.a : 1
560537 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
560618 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
571695 my_tree.at_cell.arbs[2].ack_cell1._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
589678 my_tree.at_cell.tmp[5].a : 1 [by my_tree.at_cell.arbs[2].ack_cell1._y:=0]
589770 my_tree.at_cell.arbs[0].ack_cell1._y : 0 [by my_tree.at_cell.tmp[5].a:=1]
598081 my_tree._in[0].a : 1 [by my_tree.at_cell.arbs[0].ack_cell1._y:=0]
599825 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 0 [by my_tree._in[0].a:=1]
600438 my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B:=0]
614460 my_tree._in[0].r : 0 [by my_tree.fifo_to_tree[0].fifo_element[1].buf_func._y:=1]
614505 my_tree.at_cell.arbs[0].arbiter._y1 : 1 [by my_tree._in[0].r:=0]
615457 my_tree.fifo_to_tree[0].fifo_element[1]._en : 1 [by my_tree._in[0].r:=0]
616154 my_tree.at_cell.arbs[0]._y1_arb : 0 [by my_tree.at_cell.arbs[0].arbiter._y1:=1]
616679 my_tree.at_cell.arbs[0].or_cell._y : 1 [by my_tree.at_cell.arbs[0]._y1_arb:=0]
617579 my_tree.at_cell.tmp[5].r : 0 [by my_tree.at_cell.arbs[0].or_cell._y:=1]
617631 my_tree.at_cell.arbs[2].arbiter._y1 : 1 [by my_tree.at_cell.tmp[5].r:=0]
617638 my_tree.at_cell.arbs[2].arbiter._y2 : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
633243 my_tree.at_cell.arbs[2]._y1_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y1:=1]
639710 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y1_arb:=0]
639712 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
640066 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
640199 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
640200 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
640204 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
640204 my_tree.out.a : 0
640750 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
686313 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
686314 my_tree.at_cell.arbs[2].ack_cell1._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
698692 my_tree.at_cell.tmp[5].a : 0 [by my_tree.at_cell.arbs[2].ack_cell1._y:=1]
698771 my_tree.at_cell.arbs[2]._y2_arb : 1 [by my_tree.at_cell.tmp[5].a:=0]
698859 my_tree.at_cell.arbs[2].or_cell._y : 0 [by my_tree.at_cell.arbs[2]._y2_arb:=1]
701125 my_tree.at_cell.arbs[0].ack_cell1._y : 1 [by my_tree.at_cell.tmp[5].a:=0]
706641 my_tree.at_cell.tmp[8].r : 1 [by my_tree.at_cell.arbs[2].or_cell._y:=0]
706700 my_tree.at_cell.arbs[3].arbiter._y1 : 0 [by my_tree.at_cell.tmp[8].r:=1]
706730 my_tree.at_cell.arbs[3]._y1_arb : 1 [by my_tree.at_cell.arbs[3].arbiter._y1:=0]
708197 my_tree.at_cell.arbs[3].or_cell._y : 0 [by my_tree.at_cell.arbs[3]._y1_arb:=1]
729452 my_tree._in[0].a : 0 [by my_tree.at_cell.arbs[0].ack_cell1._y:=1]
748836 my_tree.fifo_to_tree[0].fifo_element[1]._out_a_B : 1 [by my_tree._in[0].a:=0]
767701 my_tree.out.r : 1 [by my_tree.at_cell.arbs[3].or_cell._y:=0]
767701 my_tree.out.a : 1
768386 my_tree.at_cell.arbs[3].ack_cell1._y : 0 [by my_tree.out.a:=1]
785101 my_tree.at_cell.tmp[8].a : 1 [by my_tree.at_cell.arbs[3].ack_cell1._y:=0]
785228 my_tree.at_cell.arbs[2].ack_cell2._y : 0 [by my_tree.at_cell.tmp[8].a:=1]
785397 my_tree.at_cell.tmp[6].a : 1 [by my_tree.at_cell.arbs[2].ack_cell2._y:=0]
785440 my_tree.at_cell.arbs[1].ack_cell1._y : 0 [by my_tree.at_cell.tmp[6].a:=1]
785452 my_tree._in[2].a : 1 [by my_tree.at_cell.arbs[1].ack_cell1._y:=0]
786731 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 0 [by my_tree._in[2].a:=1]
786964 my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y : 1 [by my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B:=0]
786967 my_tree._in[2].r : 0 [by my_tree.fifo_to_tree[2].fifo_element[1].buf_func._y:=1]
786968 my_tree.fifo_to_tree[2].fifo_element[1]._en : 1 [by my_tree._in[2].r:=0]
787005 my_tree.at_cell.arbs[1].arbiter._y1 : 1 [by my_tree._in[2].r:=0]
799757 my_tree.at_cell.arbs[1]._y1_arb : 0 [by my_tree.at_cell.arbs[1].arbiter._y1:=1]
799849 my_tree.at_cell.arbs[1].or_cell._y : 1 [by my_tree.at_cell.arbs[1]._y1_arb:=0]
802576 my_tree.at_cell.tmp[6].r : 0 [by my_tree.at_cell.arbs[1].or_cell._y:=1]
802578 my_tree.at_cell.arbs[2].arbiter._y2 : 1 [by my_tree.at_cell.tmp[6].r:=0]
802579 my_tree.at_cell.arbs[2]._y2_arb : 0 [by my_tree.at_cell.arbs[2].arbiter._y2:=1]
804080 my_tree.at_cell.arbs[2].or_cell._y : 1 [by my_tree.at_cell.arbs[2]._y2_arb:=0]
804082 my_tree.at_cell.tmp[8].r : 0 [by my_tree.at_cell.arbs[2].or_cell._y:=1]
804100 my_tree.at_cell.arbs[3].arbiter._y1 : 1 [by my_tree.at_cell.tmp[8].r:=0]
804219 my_tree.at_cell.arbs[3]._y1_arb : 0 [by my_tree.at_cell.arbs[3].arbiter._y1:=1]
809939 my_tree.at_cell.arbs[3].or_cell._y : 1 [by my_tree.at_cell.arbs[3]._y1_arb:=0]
809947 my_tree.out.r : 0 [by my_tree.at_cell.arbs[3].or_cell._y:=1]
809947 my_tree.out.a : 0
810001 my_tree.at_cell.arbs[3].ack_cell1._y : 1 [by my_tree.out.a:=0]
860539 my_tree.at_cell.tmp[8].a : 0 [by my_tree.at_cell.arbs[3].ack_cell1._y:=1]
860544 my_tree.at_cell.arbs[2].ack_cell2._y : 1 [by my_tree.at_cell.tmp[8].a:=0]
861611 my_tree.at_cell.tmp[6].a : 0 [by my_tree.at_cell.arbs[2].ack_cell2._y:=1]
861612 my_tree.at_cell.arbs[1].ack_cell1._y : 1 [by my_tree.at_cell.tmp[6].a:=0]
861750 my_tree._in[2].a : 0 [by my_tree.at_cell.arbs[1].ack_cell1._y:=1]
861751 my_tree.fifo_to_tree[2].fifo_element[1]._out_a_B : 1 [by my_tree._in[2].a:=0]
-------------------------------------------------
[3] Sent three inputs, received 3 outputs

1085
test/unit_tests/arbiter_tree_test/run/test.prs
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64
test/unit_tests/arbiter_tree_test/test.act
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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbiter_treee (a1of1 in[5]; a1of1 out)
{
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
a1of1 _in[5];
power _supply;
_supply.vdd = Vdd;
_supply.vss = GND;
fifo_t<2> fifo_to_tree[5];
(i:5:
fifo_to_tree[i].in = in[i];
fifo_to_tree[i].out = _in[i];
fifo_to_tree[i].supply = _supply;
fifo_to_tree[i].reset_B = _reset_B;
)
arbtree<5> at_cell(.in=_in, .out = out);
at_cell.supply = _supply;
}
arbiter_treee my_tree;

63
test/unit_tests/arbiter_tree_test/test.prsim
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watchall
set my_tree.in[0].r 0
set my_tree.in[1].r 0
set my_tree.in[2].r 0
set my_tree.in[3].r 0
set my_tree.in[4].r 0
set my_tree.out.a 0
cycle
assert my_tree.in[0].a 0
assert my_tree.in[1].a 0
assert my_tree.in[2].a 0
assert my_tree.in[3].a 0
assert my_tree.in[4].a 0
assert my_tree.out.r 0
system "echo '-------------------------------------------------'"
system "echo '[0] System initialized'"
set Reset 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[1] System reset completed'"
set my_tree.in[0].r 1
set my_tree.in[2].r 1
set my_tree.in[4].r 1
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
assert my_tree.out.r 1
set my_tree.out.a 1
cycle
assert my_tree.out.r 0
set my_tree.out.a 0
cycle
system "echo '-------------------------------------------------'"
system "echo '[3] Sent three inputs, received 3 outputs'"

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test/unit_tests/arbtree_5/.DS_Store vendored
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test/unit_tests/arbtree_5/run/prsim.out
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t.at.arbs[2]._y1_arb t.in[2].r t.at.arbs[0].ack_cell1._y t.at.arbs[0]._y1_arb t.at.tmp[6].a t.at.arbs[1]._y1_arb t.at.arbs[3]._y1_arb t.in[1].a t.out.r t.in[4].r t.at.tmp[8].a t.at.tmp[5].r t.in[1].r t.in[3].r t.in[0].r t.at.tmp[6].r t.at.arbs[0].ack_cell2._y t.in[3].a t.at.tmp[8].r t.at.tmp[5].a t.at.arbs[2]._y2_arb t.in[0].a t.at.arbs[2].arbiter._y1 t.at.arbs[3]._y2_arb t.in[2].a t.out.a t.at.arbs[1].arbiter._y2 t.at.arbs[0].arbiter._y1 t.in[4].a t.at.arbs[2].arbiter._y2 t.at.arbs[0]._y2_arb t.at.arbs[3].ack_cell2._y t.at.arbs[2].ack_cell2._y t.at.arbs[1]._y2_arb t.at.arbs[1].or_cell._y t.at.arbs[1].arbiter._y1 t.at.arbs[3].arbiter._y1 t.at.arbs[3].ack_cell1._y t.at.arbs[0].or_cell._y t.at.arbs[1].ack_cell2._y t.at.arbs[2].ack_cell1._y t.at.arbs[3].arbiter._y2 t.at.arbs[0].arbiter._y2 t.at.arbs[2].or_cell._y t.at.arbs[1].ack_cell1._y t.at.arbs[3].or_cell._y
0

321
test/unit_tests/arbtree_5/run/test.prs
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@@ -1,321 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].in1.r"
= "t.at.arbs[0].in1.a" "t.at.arbs[0].arbiter.d"
= "t.at.arbs[0].in1.a" "t.at.arbs[0].ack_cell1.y"
= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].arbiter.a"
= "t.at.arbs[0].in1.d.d[0]" "t.at.arbs[0].in1.r"
~"t.at.arbs[0].ack_cell1.c1"&~"t.at.arbs[0].ack_cell1.c2"->"t.at.arbs[0].ack_cell1._y"+
"t.at.arbs[0].ack_cell1.c1"&"t.at.arbs[0].ack_cell1.c2"->"t.at.arbs[0].ack_cell1._y"-
"t.at.arbs[0].ack_cell1._y"->"t.at.arbs[0].ack_cell1.y"-
~("t.at.arbs[0].ack_cell1._y")->"t.at.arbs[0].ack_cell1.y"+
= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].in2.r"
= "t.at.arbs[0].in2.a" "t.at.arbs[0].arbiter.c"
= "t.at.arbs[0].in2.a" "t.at.arbs[0].ack_cell2.y"
= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].arbiter.b"
= "t.at.arbs[0].in2.d.d[0]" "t.at.arbs[0].in2.r"
= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].arbiter.vdd"
= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].or_cell.vdd"
= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].ack_cell2.vdd"
= "t.at.arbs[0].supply.vdd" "t.at.arbs[0].ack_cell1.vdd"
= "t.at.arbs[0].supply.vss" "t.at.arbs[0].arbiter.vss"
= "t.at.arbs[0].supply.vss" "t.at.arbs[0].or_cell.vss"
= "t.at.arbs[0].supply.vss" "t.at.arbs[0].ack_cell2.vss"
= "t.at.arbs[0].supply.vss" "t.at.arbs[0].ack_cell1.vss"
"t.at.arbs[0].arbiter.a"&"t.at.arbs[0].arbiter._y2"->"t.at.arbs[0].arbiter._y1"-
~"t.at.arbs[0].arbiter.a"|~"t.at.arbs[0].arbiter._y2"->"t.at.arbs[0].arbiter._y1"+
"t.at.arbs[0].arbiter.b"&"t.at.arbs[0].arbiter._y1"->"t.at.arbs[0].arbiter._y2"-
~"t.at.arbs[0].arbiter.b"|~"t.at.arbs[0].arbiter._y1"->"t.at.arbs[0].arbiter._y2"+
"t.at.arbs[0].arbiter._y1"|"t.at.arbs[0].arbiter.c"->"t.at.arbs[0].arbiter.y1"-
~("t.at.arbs[0].arbiter._y1"|"t.at.arbs[0].arbiter.c")->"t.at.arbs[0].arbiter.y1"+
"t.at.arbs[0].arbiter._y2"|"t.at.arbs[0].arbiter.d"->"t.at.arbs[0].arbiter.y2"-
~("t.at.arbs[0].arbiter._y2"|"t.at.arbs[0].arbiter.d")->"t.at.arbs[0].arbiter.y2"+
mk_excllo("t.at.arbs[0].arbiter._y1","t.at.arbs[0].arbiter._y2")
= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].arbiter.y1"
= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].or_cell.a"
= "t.at.arbs[0]._y1_arb" "t.at.arbs[0].ack_cell1.c2"
~"t.at.arbs[0].ack_cell2.c1"&~"t.at.arbs[0].ack_cell2.c2"->"t.at.arbs[0].ack_cell2._y"+
"t.at.arbs[0].ack_cell2.c1"&"t.at.arbs[0].ack_cell2.c2"->"t.at.arbs[0].ack_cell2._y"-
"t.at.arbs[0].ack_cell2._y"->"t.at.arbs[0].ack_cell2.y"-
~("t.at.arbs[0].ack_cell2._y")->"t.at.arbs[0].ack_cell2.y"+
"t.at.arbs[0].or_cell.a"|"t.at.arbs[0].or_cell.b"->"t.at.arbs[0].or_cell._y"-
~("t.at.arbs[0].or_cell.a"|"t.at.arbs[0].or_cell.b")->"t.at.arbs[0].or_cell._y"+
"t.at.arbs[0].or_cell._y"->"t.at.arbs[0].or_cell.y"-
~("t.at.arbs[0].or_cell._y")->"t.at.arbs[0].or_cell.y"+
= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].out.r"
= "t.at.arbs[0].out.a" "t.at.arbs[0].ack_cell2.c1"
= "t.at.arbs[0].out.a" "t.at.arbs[0].ack_cell1.c1"
= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].or_cell.y"
= "t.at.arbs[0].out.d.d[0]" "t.at.arbs[0].out.r"
= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].arbiter.y2"
= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].or_cell.b"
= "t.at.arbs[0]._y2_arb" "t.at.arbs[0].ack_cell2.c2"
= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].in1.r"
= "t.at.arbs[1].in1.a" "t.at.arbs[1].arbiter.d"
= "t.at.arbs[1].in1.a" "t.at.arbs[1].ack_cell1.y"
= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].arbiter.a"
= "t.at.arbs[1].in1.d.d[0]" "t.at.arbs[1].in1.r"
~"t.at.arbs[1].ack_cell1.c1"&~"t.at.arbs[1].ack_cell1.c2"->"t.at.arbs[1].ack_cell1._y"+
"t.at.arbs[1].ack_cell1.c1"&"t.at.arbs[1].ack_cell1.c2"->"t.at.arbs[1].ack_cell1._y"-
"t.at.arbs[1].ack_cell1._y"->"t.at.arbs[1].ack_cell1.y"-
~("t.at.arbs[1].ack_cell1._y")->"t.at.arbs[1].ack_cell1.y"+
= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].in2.r"
= "t.at.arbs[1].in2.a" "t.at.arbs[1].arbiter.c"
= "t.at.arbs[1].in2.a" "t.at.arbs[1].ack_cell2.y"
= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].arbiter.b"
= "t.at.arbs[1].in2.d.d[0]" "t.at.arbs[1].in2.r"
= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].arbiter.vdd"
= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].or_cell.vdd"
= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].ack_cell2.vdd"
= "t.at.arbs[1].supply.vdd" "t.at.arbs[1].ack_cell1.vdd"
= "t.at.arbs[1].supply.vss" "t.at.arbs[1].arbiter.vss"
= "t.at.arbs[1].supply.vss" "t.at.arbs[1].or_cell.vss"
= "t.at.arbs[1].supply.vss" "t.at.arbs[1].ack_cell2.vss"
= "t.at.arbs[1].supply.vss" "t.at.arbs[1].ack_cell1.vss"
"t.at.arbs[1].arbiter.a"&"t.at.arbs[1].arbiter._y2"->"t.at.arbs[1].arbiter._y1"-
~"t.at.arbs[1].arbiter.a"|~"t.at.arbs[1].arbiter._y2"->"t.at.arbs[1].arbiter._y1"+
"t.at.arbs[1].arbiter.b"&"t.at.arbs[1].arbiter._y1"->"t.at.arbs[1].arbiter._y2"-
~"t.at.arbs[1].arbiter.b"|~"t.at.arbs[1].arbiter._y1"->"t.at.arbs[1].arbiter._y2"+
"t.at.arbs[1].arbiter._y1"|"t.at.arbs[1].arbiter.c"->"t.at.arbs[1].arbiter.y1"-
~("t.at.arbs[1].arbiter._y1"|"t.at.arbs[1].arbiter.c")->"t.at.arbs[1].arbiter.y1"+
"t.at.arbs[1].arbiter._y2"|"t.at.arbs[1].arbiter.d"->"t.at.arbs[1].arbiter.y2"-
~("t.at.arbs[1].arbiter._y2"|"t.at.arbs[1].arbiter.d")->"t.at.arbs[1].arbiter.y2"+
mk_excllo("t.at.arbs[1].arbiter._y1","t.at.arbs[1].arbiter._y2")
= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].arbiter.y1"
= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].or_cell.a"
= "t.at.arbs[1]._y1_arb" "t.at.arbs[1].ack_cell1.c2"
~"t.at.arbs[1].ack_cell2.c1"&~"t.at.arbs[1].ack_cell2.c2"->"t.at.arbs[1].ack_cell2._y"+
"t.at.arbs[1].ack_cell2.c1"&"t.at.arbs[1].ack_cell2.c2"->"t.at.arbs[1].ack_cell2._y"-
"t.at.arbs[1].ack_cell2._y"->"t.at.arbs[1].ack_cell2.y"-
~("t.at.arbs[1].ack_cell2._y")->"t.at.arbs[1].ack_cell2.y"+
"t.at.arbs[1].or_cell.a"|"t.at.arbs[1].or_cell.b"->"t.at.arbs[1].or_cell._y"-
~("t.at.arbs[1].or_cell.a"|"t.at.arbs[1].or_cell.b")->"t.at.arbs[1].or_cell._y"+
"t.at.arbs[1].or_cell._y"->"t.at.arbs[1].or_cell.y"-
~("t.at.arbs[1].or_cell._y")->"t.at.arbs[1].or_cell.y"+
= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].out.r"
= "t.at.arbs[1].out.a" "t.at.arbs[1].ack_cell2.c1"
= "t.at.arbs[1].out.a" "t.at.arbs[1].ack_cell1.c1"
= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].or_cell.y"
= "t.at.arbs[1].out.d.d[0]" "t.at.arbs[1].out.r"
= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].arbiter.y2"
= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].or_cell.b"
= "t.at.arbs[1]._y2_arb" "t.at.arbs[1].ack_cell2.c2"
= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].in1.r"
= "t.at.arbs[2].in1.a" "t.at.arbs[2].arbiter.d"
= "t.at.arbs[2].in1.a" "t.at.arbs[2].ack_cell1.y"
= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].arbiter.a"
= "t.at.arbs[2].in1.d.d[0]" "t.at.arbs[2].in1.r"
~"t.at.arbs[2].ack_cell1.c1"&~"t.at.arbs[2].ack_cell1.c2"->"t.at.arbs[2].ack_cell1._y"+
"t.at.arbs[2].ack_cell1.c1"&"t.at.arbs[2].ack_cell1.c2"->"t.at.arbs[2].ack_cell1._y"-
"t.at.arbs[2].ack_cell1._y"->"t.at.arbs[2].ack_cell1.y"-
~("t.at.arbs[2].ack_cell1._y")->"t.at.arbs[2].ack_cell1.y"+
= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].in2.r"
= "t.at.arbs[2].in2.a" "t.at.arbs[2].arbiter.c"
= "t.at.arbs[2].in2.a" "t.at.arbs[2].ack_cell2.y"
= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].arbiter.b"
= "t.at.arbs[2].in2.d.d[0]" "t.at.arbs[2].in2.r"
= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].arbiter.vdd"
= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].or_cell.vdd"
= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].ack_cell2.vdd"
= "t.at.arbs[2].supply.vdd" "t.at.arbs[2].ack_cell1.vdd"
= "t.at.arbs[2].supply.vss" "t.at.arbs[2].arbiter.vss"
= "t.at.arbs[2].supply.vss" "t.at.arbs[2].or_cell.vss"
= "t.at.arbs[2].supply.vss" "t.at.arbs[2].ack_cell2.vss"
= "t.at.arbs[2].supply.vss" "t.at.arbs[2].ack_cell1.vss"
"t.at.arbs[2].arbiter.a"&"t.at.arbs[2].arbiter._y2"->"t.at.arbs[2].arbiter._y1"-
~"t.at.arbs[2].arbiter.a"|~"t.at.arbs[2].arbiter._y2"->"t.at.arbs[2].arbiter._y1"+
"t.at.arbs[2].arbiter.b"&"t.at.arbs[2].arbiter._y1"->"t.at.arbs[2].arbiter._y2"-
~"t.at.arbs[2].arbiter.b"|~"t.at.arbs[2].arbiter._y1"->"t.at.arbs[2].arbiter._y2"+
"t.at.arbs[2].arbiter._y1"|"t.at.arbs[2].arbiter.c"->"t.at.arbs[2].arbiter.y1"-
~("t.at.arbs[2].arbiter._y1"|"t.at.arbs[2].arbiter.c")->"t.at.arbs[2].arbiter.y1"+
"t.at.arbs[2].arbiter._y2"|"t.at.arbs[2].arbiter.d"->"t.at.arbs[2].arbiter.y2"-
~("t.at.arbs[2].arbiter._y2"|"t.at.arbs[2].arbiter.d")->"t.at.arbs[2].arbiter.y2"+
mk_excllo("t.at.arbs[2].arbiter._y1","t.at.arbs[2].arbiter._y2")
= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].arbiter.y1"
= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].or_cell.a"
= "t.at.arbs[2]._y1_arb" "t.at.arbs[2].ack_cell1.c2"
~"t.at.arbs[2].ack_cell2.c1"&~"t.at.arbs[2].ack_cell2.c2"->"t.at.arbs[2].ack_cell2._y"+
"t.at.arbs[2].ack_cell2.c1"&"t.at.arbs[2].ack_cell2.c2"->"t.at.arbs[2].ack_cell2._y"-
"t.at.arbs[2].ack_cell2._y"->"t.at.arbs[2].ack_cell2.y"-
~("t.at.arbs[2].ack_cell2._y")->"t.at.arbs[2].ack_cell2.y"+
"t.at.arbs[2].or_cell.a"|"t.at.arbs[2].or_cell.b"->"t.at.arbs[2].or_cell._y"-
~("t.at.arbs[2].or_cell.a"|"t.at.arbs[2].or_cell.b")->"t.at.arbs[2].or_cell._y"+
"t.at.arbs[2].or_cell._y"->"t.at.arbs[2].or_cell.y"-
~("t.at.arbs[2].or_cell._y")->"t.at.arbs[2].or_cell.y"+
= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].out.r"
= "t.at.arbs[2].out.a" "t.at.arbs[2].ack_cell2.c1"
= "t.at.arbs[2].out.a" "t.at.arbs[2].ack_cell1.c1"
= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].or_cell.y"
= "t.at.arbs[2].out.d.d[0]" "t.at.arbs[2].out.r"
= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].arbiter.y2"
= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].or_cell.b"
= "t.at.arbs[2]._y2_arb" "t.at.arbs[2].ack_cell2.c2"
= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].in1.r"
= "t.at.arbs[3].in1.a" "t.at.arbs[3].arbiter.d"
= "t.at.arbs[3].in1.a" "t.at.arbs[3].ack_cell1.y"
= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].arbiter.a"
= "t.at.arbs[3].in1.d.d[0]" "t.at.arbs[3].in1.r"
~"t.at.arbs[3].ack_cell1.c1"&~"t.at.arbs[3].ack_cell1.c2"->"t.at.arbs[3].ack_cell1._y"+
"t.at.arbs[3].ack_cell1.c1"&"t.at.arbs[3].ack_cell1.c2"->"t.at.arbs[3].ack_cell1._y"-
"t.at.arbs[3].ack_cell1._y"->"t.at.arbs[3].ack_cell1.y"-
~("t.at.arbs[3].ack_cell1._y")->"t.at.arbs[3].ack_cell1.y"+
= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].in2.r"
= "t.at.arbs[3].in2.a" "t.at.arbs[3].arbiter.c"
= "t.at.arbs[3].in2.a" "t.at.arbs[3].ack_cell2.y"
= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].arbiter.b"
= "t.at.arbs[3].in2.d.d[0]" "t.at.arbs[3].in2.r"
= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].arbiter.vdd"
= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].or_cell.vdd"
= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].ack_cell2.vdd"
= "t.at.arbs[3].supply.vdd" "t.at.arbs[3].ack_cell1.vdd"
= "t.at.arbs[3].supply.vss" "t.at.arbs[3].arbiter.vss"
= "t.at.arbs[3].supply.vss" "t.at.arbs[3].or_cell.vss"
= "t.at.arbs[3].supply.vss" "t.at.arbs[3].ack_cell2.vss"
= "t.at.arbs[3].supply.vss" "t.at.arbs[3].ack_cell1.vss"
"t.at.arbs[3].arbiter.a"&"t.at.arbs[3].arbiter._y2"->"t.at.arbs[3].arbiter._y1"-
~"t.at.arbs[3].arbiter.a"|~"t.at.arbs[3].arbiter._y2"->"t.at.arbs[3].arbiter._y1"+
"t.at.arbs[3].arbiter.b"&"t.at.arbs[3].arbiter._y1"->"t.at.arbs[3].arbiter._y2"-
~"t.at.arbs[3].arbiter.b"|~"t.at.arbs[3].arbiter._y1"->"t.at.arbs[3].arbiter._y2"+
"t.at.arbs[3].arbiter._y1"|"t.at.arbs[3].arbiter.c"->"t.at.arbs[3].arbiter.y1"-
~("t.at.arbs[3].arbiter._y1"|"t.at.arbs[3].arbiter.c")->"t.at.arbs[3].arbiter.y1"+
"t.at.arbs[3].arbiter._y2"|"t.at.arbs[3].arbiter.d"->"t.at.arbs[3].arbiter.y2"-
~("t.at.arbs[3].arbiter._y2"|"t.at.arbs[3].arbiter.d")->"t.at.arbs[3].arbiter.y2"+
mk_excllo("t.at.arbs[3].arbiter._y1","t.at.arbs[3].arbiter._y2")
= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].arbiter.y1"
= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].or_cell.a"
= "t.at.arbs[3]._y1_arb" "t.at.arbs[3].ack_cell1.c2"
~"t.at.arbs[3].ack_cell2.c1"&~"t.at.arbs[3].ack_cell2.c2"->"t.at.arbs[3].ack_cell2._y"+
"t.at.arbs[3].ack_cell2.c1"&"t.at.arbs[3].ack_cell2.c2"->"t.at.arbs[3].ack_cell2._y"-
"t.at.arbs[3].ack_cell2._y"->"t.at.arbs[3].ack_cell2.y"-
~("t.at.arbs[3].ack_cell2._y")->"t.at.arbs[3].ack_cell2.y"+
"t.at.arbs[3].or_cell.a"|"t.at.arbs[3].or_cell.b"->"t.at.arbs[3].or_cell._y"-
~("t.at.arbs[3].or_cell.a"|"t.at.arbs[3].or_cell.b")->"t.at.arbs[3].or_cell._y"+
"t.at.arbs[3].or_cell._y"->"t.at.arbs[3].or_cell.y"-
~("t.at.arbs[3].or_cell._y")->"t.at.arbs[3].or_cell.y"+
= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].out.r"
= "t.at.arbs[3].out.a" "t.at.arbs[3].ack_cell2.c1"
= "t.at.arbs[3].out.a" "t.at.arbs[3].ack_cell1.c1"
= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].or_cell.y"
= "t.at.arbs[3].out.d.d[0]" "t.at.arbs[3].out.r"
= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].arbiter.y2"
= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].or_cell.b"
= "t.at.arbs[3]._y2_arb" "t.at.arbs[3].ack_cell2.c2"
= "t.at.tmp[5].d.d[0]" "t.at.tmp[5].r"
= "t.at.tmp[6].d.d[0]" "t.at.tmp[6].r"
= "t.at.tmp[8].d.d[0]" "t.at.tmp[8].r"
= "t.at.tmp[5].r" "t.at.arbs[2].in1.r"
= "t.at.tmp[5].a" "t.at.arbs[2].in1.a"
= "t.at.tmp[5].d.d[0]" "t.at.arbs[2].in1.d.d[0]"
= "t.at.tmp[5].r" "t.at.arbs[0].out.r"
= "t.at.tmp[5].a" "t.at.arbs[0].out.a"
= "t.at.tmp[5].d.d[0]" "t.at.arbs[0].out.d.d[0]"
= "t.at.tmp[6].r" "t.at.arbs[2].in2.r"
= "t.at.tmp[6].a" "t.at.arbs[2].in2.a"
= "t.at.tmp[6].d.d[0]" "t.at.arbs[2].in2.d.d[0]"
= "t.at.tmp[6].r" "t.at.arbs[1].out.r"
= "t.at.tmp[6].a" "t.at.arbs[1].out.a"
= "t.at.tmp[6].d.d[0]" "t.at.arbs[1].out.d.d[0]"
= "t.at.tmp[8].r" "t.at.arbs[3].in1.r"
= "t.at.tmp[8].a" "t.at.arbs[3].in1.a"
= "t.at.tmp[8].d.d[0]" "t.at.arbs[3].in1.d.d[0]"
= "t.at.tmp[8].r" "t.at.arbs[2].out.r"
= "t.at.tmp[8].a" "t.at.arbs[2].out.a"
= "t.at.tmp[8].d.d[0]" "t.at.arbs[2].out.d.d[0]"
= "t.at.tmp[8].d.d[0]" "t.at.tmp[8].r"
= "t.at.tmp[6].d.d[0]" "t.at.tmp[6].r"
= "t.at.tmp[5].d.d[0]" "t.at.tmp[5].r"
= "t.at.supply.vss" "t.at.arbs[3].supply.vss"
= "t.at.supply.vdd" "t.at.arbs[3].supply.vdd"
= "t.at.supply.vss" "t.at.arbs[2].supply.vss"
= "t.at.supply.vdd" "t.at.arbs[2].supply.vdd"
= "t.at.supply.vss" "t.at.arbs[1].supply.vss"
= "t.at.supply.vdd" "t.at.arbs[1].supply.vdd"
= "t.at.supply.vss" "t.at.arbs[0].supply.vss"
= "t.at.supply.vdd" "t.at.arbs[0].supply.vdd"
= "t.at.in[0].d.d[0]" "t.at.in[0].r"
= "t.at.in[1].d.d[0]" "t.at.in[1].r"
= "t.at.in[2].d.d[0]" "t.at.in[2].r"
= "t.at.in[3].d.d[0]" "t.at.in[3].r"
= "t.at.in[4].d.d[0]" "t.at.in[4].r"
= "t.at.in[0].r" "t.at.arbs[0].in1.r"
= "t.at.in[0].a" "t.at.arbs[0].in1.a"
= "t.at.in[0].d.d[0]" "t.at.arbs[0].in1.d.d[0]"
= "t.at.in[0].r" "t.at.tmp[0].r"
= "t.at.in[0].a" "t.at.tmp[0].a"
= "t.at.in[0].d.d[0]" "t.at.tmp[0].d.d[0]"
= "t.at.in[1].r" "t.at.arbs[0].in2.r"
= "t.at.in[1].a" "t.at.arbs[0].in2.a"
= "t.at.in[1].d.d[0]" "t.at.arbs[0].in2.d.d[0]"
= "t.at.in[1].r" "t.at.tmp[1].r"
= "t.at.in[1].a" "t.at.tmp[1].a"
= "t.at.in[1].d.d[0]" "t.at.tmp[1].d.d[0]"
= "t.at.in[2].r" "t.at.arbs[1].in1.r"
= "t.at.in[2].a" "t.at.arbs[1].in1.a"
= "t.at.in[2].d.d[0]" "t.at.arbs[1].in1.d.d[0]"
= "t.at.in[2].r" "t.at.tmp[2].r"
= "t.at.in[2].a" "t.at.tmp[2].a"
= "t.at.in[2].d.d[0]" "t.at.tmp[2].d.d[0]"
= "t.at.in[3].r" "t.at.arbs[1].in2.r"
= "t.at.in[3].a" "t.at.arbs[1].in2.a"
= "t.at.in[3].d.d[0]" "t.at.arbs[1].in2.d.d[0]"
= "t.at.in[3].r" "t.at.tmp[3].r"
= "t.at.in[3].a" "t.at.tmp[3].a"
= "t.at.in[3].d.d[0]" "t.at.tmp[3].d.d[0]"
= "t.at.in[4].r" "t.at.arbs[3].in2.r"
= "t.at.in[4].a" "t.at.arbs[3].in2.a"
= "t.at.in[4].d.d[0]" "t.at.arbs[3].in2.d.d[0]"
= "t.at.in[4].r" "t.at.tmp[9].r"
= "t.at.in[4].a" "t.at.tmp[9].a"
= "t.at.in[4].d.d[0]" "t.at.tmp[9].d.d[0]"
= "t.at.in[4].r" "t.at.tmp[7].r"
= "t.at.in[4].a" "t.at.tmp[7].a"
= "t.at.in[4].d.d[0]" "t.at.tmp[7].d.d[0]"
= "t.at.in[4].r" "t.at.tmp[4].r"
= "t.at.in[4].a" "t.at.tmp[4].a"
= "t.at.in[4].d.d[0]" "t.at.tmp[4].d.d[0]"
= "t.at.in[4].d.d[0]" "t.at.in[4].r"
= "t.at.in[3].d.d[0]" "t.at.in[3].r"
= "t.at.in[2].d.d[0]" "t.at.in[2].r"
= "t.at.in[1].d.d[0]" "t.at.in[1].r"
= "t.at.in[0].d.d[0]" "t.at.in[0].r"
= "t.at.out.d.d[0]" "t.at.out.r"
= "t.at.out.r" "t.at.arbs[3].out.r"
= "t.at.out.a" "t.at.arbs[3].out.a"
= "t.at.out.d.d[0]" "t.at.arbs[3].out.d.d[0]"
= "t.at.out.r" "t.at.tmp[10].r"
= "t.at.out.a" "t.at.tmp[10].a"
= "t.at.out.d.d[0]" "t.at.tmp[10].d.d[0]"
= "t.at.out.d.d[0]" "t.at.out.r"
= "Vdd" "t.at.supply.vdd"
= "GND" "t.at.supply.vss"
= "t.out.d.d[0]" "t.out.r"
= "t.out.r" "t.at.out.r"
= "t.out.a" "t.at.out.a"
= "t.out.d.d[0]" "t.at.out.d.d[0]"
= "t.out.d.d[0]" "t.out.r"
= "t.in[0].d.d[0]" "t.in[0].r"
= "t.in[1].d.d[0]" "t.in[1].r"
= "t.in[2].d.d[0]" "t.in[2].r"
= "t.in[3].d.d[0]" "t.in[3].r"
= "t.in[4].d.d[0]" "t.in[4].r"
= "t.in[0].r" "t.at.in[0].r"
= "t.in[1].r" "t.at.in[1].r"
= "t.in[2].r" "t.at.in[2].r"
= "t.in[3].r" "t.at.in[3].r"
= "t.in[4].r" "t.at.in[4].r"
= "t.in[0].a" "t.at.in[0].a"
= "t.in[1].a" "t.at.in[1].a"
= "t.in[2].a" "t.at.in[2].a"
= "t.in[3].a" "t.at.in[3].a"
= "t.in[4].a" "t.at.in[4].a"
= "t.in[0].d.d[0]" "t.at.in[0].d.d[0]"
= "t.in[1].d.d[0]" "t.at.in[1].d.d[0]"
= "t.in[2].d.d[0]" "t.at.in[2].d.d[0]"
= "t.in[3].d.d[0]" "t.at.in[3].d.d[0]"
= "t.in[4].d.d[0]" "t.at.in[4].d.d[0]"
= "t.in[4].d.d[0]" "t.in[4].r"
= "t.in[3].d.d[0]" "t.in[3].r"
= "t.in[2].d.d[0]" "t.in[2].r"
= "t.in[1].d.d[0]" "t.in[1].r"
= "t.in[0].d.d[0]" "t.in[0].r"

53
test/unit_tests/arbtree_5/test.act
View File

@@ -1,53 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
open tmpl::dataflow_neuro;
defproc arbtree (a1of1 in[5]; a1of1 out)
{
a1of1 _in[5];
power _supply
_supply.vdd = Vdd;
_supply.vss = GND;
fifo_t<2> fifo_to_tree[5];
(i:5:
fifo_to_tree[i].in = in[i];
fifo_to_tree[i].out = _in[i];
fifo_to_tree.supply = _supply;
fifo_to_tree.reset_B = _reset_B;
)
arbtree<5> at(.in=_in, .out = out);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
at.supply = _supply;
}
arbtree t;

127
test/unit_tests/arbtree_5/test.prsim
View File

@@ -1,127 +0,0 @@
watchall
system "echo '[] setting channels neutral'"
set t.in[0].r 0
set t.in[1].r 0
set t.in[2].r 0
set t.in[3].r 0
set t.in[4].r 0
set t.out.a 0
cycle
mode run
assert t.out.r 0
assert t.in[0].a 0
assert t.in[1].a 0
assert t.in[2].a 0
assert t.in[3].a 0
assert t.in[4].a 0
system "echo '[] setting some reqs high'"
set t.in[0].r 1
set t.in[1].r 1
set t.in[2].r 1
cycle
assert t.out.r 1
system "echo '[] receiving ack'"
set t.out.a 1
cycle
assert t.in.a 1
system "echo '[] removing first req (guess)'"
set t.in[0].r 0
cycle
assert t.out.r
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# system "echo '1'"
# cycle
# mode run
# # assert t.out 0
# system "echo '[] setting all low'"
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# system "echo '[] setting bit 0 high'"
# set t.in[0] 1
# cycle
# system "echo '[] setting all low'"
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# system "echo '[] setting bit 1 high'"
# set t.in[0] 0
# set t.in[1] 1
# cycle
# system "echo '[] setting all low'"
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# system "echo '[] setting bit 2 high'"
# set t.in[1] 0
# set t.in[2] 1
# cycle
# system "echo '[] setting all low'"
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# system "echo '[] setting bit 3 high'"
# set t.in[2] 0
# set t.in[3] 1
# cycle
# system "echo '[] setting all low'"
# set t.in[0] 0
# set t.in[1] 0
# set t.in[2] 0
# set t.in[3] 0
# set t.in[4] 0
# cycle
# system "echo '[] setting bit 4 high'"
# set t.in[3] 0
# set t.in[4] 1
# cycle

1
test/unit_tests/async_instantiate/run/prsim.out
View File

@@ -1 +0,0 @@
cell27._y cell25.c3 cell18._y cell14._y cell27.pr_B cell21.y cell23.c3 cell10._y cell30.p3 cell20.c1 cell10.n1 cell30._y cell12.sr_B cell8.c1 cell16.c2 cell2.p1 cell28.c2 cell5.c1 cell21._y cell19.c2 cell6.p2 cell9.pr_B cell9.p3 cell4.p1 cell28.sr_B cell11.pr_B cell26.c4 cell9.n2 cell27.c2 cell12.c2 cell28.pr_B cell21.pr_B cell22.pr_B cell11.c2 cell13.y cell9.n1 cell1.n1 cell12.c1 cell28.c4 cell1.n2 cell22.sr_B cell26.y cell11.n2 cell13.n4 cell15.rs_B cell6.c1 cell28._y cell2.n2 cell10.pr_B cell16.y cell16.c1 cell11.sr_B cell15._y cell2.pr_B cell11._y cell20.y cell21.c2 cell22.c1 cell27.sr_B cell4.y cell10.n4 cell23.pr_B cell2.sr_B cell6.p1 cell9.p4 cell23._y cell11.c1 cell9.sr_B cell9.c1 cell27.y cell29.c3 cell12.n1 cell1.sr_B cell29.sr_B cell13.n3 cell13.n2 cell11.n4 cell15.n2 cell15.rp_B cell2.y cell3.n1 cell15.c2 cell26.c3 cell24.c2 cell17._y cell28.c1 cell6.n1 cell14.n1 cell31.n1 cell21.c3 cell27.c3 cell19.sr_B cell26._y cell7._y cell20.c2 cell10.n2 cell9.p2 cell14.rs_B cell31.y cell13.pr_B cell31.p1 cell30.n2 cell18.sr_B cell10.y cell6.y cell24.sr_B cell14.n2 cell30.n1 cell22.y cell10.sr_B cell10.n3 cell13.c2 cell13.n1 cell24.y cell12.pr_B cell29.pr_B cell24.c1 cell16.n1 cell24.pr_B cell28.c3 cell17.c2 cell11.n3 cell16.rs_B cell4._y cell14.c1 cell8.p2 cell14.c2 cell8.p1 cell15.n1 cell15.y cell23.c2 cell18.c1 cell7.p2 cell9.y cell7.y cell29.c1 cell30.p1 cell12.n3 cell11.n1 cell26.pr_B cell29.y cell22._y cell13.c1 cell18.y cell7.c1 cell19.y cell27.c4 cell25.c1 cell21.c1 cell30.y cell1.y cell26.c1 cell17.c1 cell2.n1 cell25.y cell5.y cell30.p4 cell31.p3 cell25.c2 cell3.p1 cell9.p5 cell9.p1 cell26.sr_B cell19.c1 cell8.y cell23.c1 cell18.c2 cell7.p1 cell22.c2 cell23.y cell14.rp_B cell30.p2 cell29.c4 cell23.sr_B cell1.c1 cell26.c2 cell3.y cell10.c1 cell16.n2 cell21.sr_B cell24.c3 cell31.p4 cell1.pr_B cell12.n2 cell31.p2 cell11.y cell12.n4 cell12._y cell18.pr_B cell10.c2 cell2.c1 cell5.p1 cell31.n2 cell13.sr_B cell12.y cell27.c1 cell1._y cell14.y cell16.rp_B cell15.c1 cell4.c1 cell29.c2 cell17.y cell19.pr_B cell3.c1 cell22.c3 cell28.y cell1.p1

96
test/unit_tests/async_instantiate/run/test.prs
View File

@@ -1,96 +0,0 @@
~"cell26.c1"&~"cell26.c2"&~"cell26.c3"&~"cell26.c4"|~"cell26.pr_B"->"cell26._y"+
"cell26.c1"&"cell26.c2"&"cell26.c3"&"cell26.c4"&"cell26.sr_B"->"cell26._y"-
"cell26._y"->"cell26.y"-
~("cell26._y")->"cell26.y"+
~"cell16.c1"&~"cell16.c2"|~"cell16.rp_B"->"cell16.y"+
"cell16.c1"&"cell16.c2"&"cell16.n1"&"cell16.n2"&"cell16.rs_B"->"cell16.y"-
~"cell8.p1"&~"cell8.p2"&~"cell8.c1"->"cell8.y"+
"cell8.c1"->"cell8.y"-
~"cell22.c1"&~"cell22.c2"&~"cell22.c3"|~"cell22.pr_B"->"cell22._y"+
"cell22.c1"&"cell22.c2"&"cell22.c3"&"cell22.sr_B"->"cell22._y"-
"cell22._y"->"cell22.y"-
~("cell22._y")->"cell22.y"+
~"cell19.c1"&~"cell19.c2"|~"cell19.pr_B"->"cell19.y"+
"cell19.c1"&"cell19.c2"&"cell19.sr_B"->"cell19.y"-
~"cell12.c1"&~"cell12.c2"|~"cell12.pr_B"->"cell12._y"+
"cell12.c1"&"cell12.c2"&("cell12.n1"&"cell12.n2"|"cell12.n3"&"cell12.n4")&"cell12.sr_B"->"cell12._y"-
"cell12._y"->"cell12.y"-
~("cell12._y")->"cell12.y"+
~"cell30.p1"&~"cell30.p2"&~"cell30.p3"&~"cell30.p4"->"cell30._y"+
"cell30.n1"|"cell30.n2"->"cell30._y"-
"cell30._y"->"cell30.y"-
~("cell30._y")->"cell30.y"+
~"cell17.c1"&~"cell17.c2"->"cell17._y"+
"cell17.c1"&"cell17.c2"->"cell17._y"-
"cell17._y"->"cell17.y"-
~("cell17._y")->"cell17.y"+
~"cell14.c1"&~"cell14.c2"|~"cell14.rp_B"->"cell14._y"+
"cell14.c1"&"cell14.c2"&"cell14.n1"&"cell14.n2"&"cell14.rs_B"->"cell14._y"-
"cell14._y"->"cell14.y"-
~("cell14._y")->"cell14.y"+
~"cell7.p1"&~"cell7.p2"&~"cell7.c1"->"cell7._y"-
"cell7.c1"->"cell7._y"+
"cell7._y"->"cell7.y"-
~("cell7._y")->"cell7.y"+
~"cell1.p1"&~"cell1.c1"|~"cell1.pr_B"->"cell1._y"+
"cell1.c1"&"cell1.n1"&"cell1.n2"&"cell1.sr_B"->"cell1._y"-
"cell1._y"->"cell1.y"-
~("cell1._y")->"cell1.y"+
~"cell21.c1"&~"cell21.c2"&~"cell21.c3"|~"cell21.pr_B"->"cell21._y"+
"cell21.c1"&"cell21.c2"&"cell21.c3"&"cell21.sr_B"->"cell21._y"-
"cell21._y"->"cell21.y"-
~("cell21._y")->"cell21.y"+
~"cell18.c1"&~"cell18.c2"|~"cell18.pr_B"->"cell18._y"+
"cell18.c1"&"cell18.c2"&"cell18.sr_B"->"cell18._y"-
"cell18._y"->"cell18.y"-
~("cell18._y")->"cell18.y"+
~"cell15.c1"&~"cell15.c2"|~"cell15.rp_B"->"cell15._y"+
"cell15.c1"&"cell15.c2"&"cell15.n1"&"cell15.n2"&"cell15.rs_B"->"cell15._y"-
"cell15._y"->"cell15.y"-
~("cell15._y")->"cell15.y"+
~"cell13.c1"&~"cell13.c2"|~"cell13.pr_B"->"cell13.y"+
"cell13.c1"&"cell13.c2"&("cell13.n1"&"cell13.n2"|"cell13.n3"&"cell13.n4")&"cell13.sr_B"->"cell13.y"-
~"cell11.c1"&~"cell11.c2"|~"cell11.pr_B"->"cell11._y"+
"cell11.c1"&"cell11.c2"&("cell11.n1"&"cell11.n2"|"cell11.n3"&"cell11.n4")&"cell11.sr_B"->"cell11._y"-
"cell11._y"->"cell11.y"-
~("cell11._y")->"cell11.y"+
~"cell28.c1"&~"cell28.c2"&~"cell28.c3"&~"cell28.c4"|~"cell28.pr_B"->"cell28._y"+
"cell28.c1"&"cell28.c2"&"cell28.c3"&"cell28.c4"&"cell28.sr_B"->"cell28._y"-
"cell28._y"->"cell28.y"-
~("cell28._y")->"cell28.y"+
~"cell24.c1"&~"cell24.c2"&~"cell24.c3"|~"cell24.pr_B"->"cell24.y"+
"cell24.c1"&"cell24.c2"&"cell24.c3"&"cell24.sr_B"->"cell24.y"-
~"cell23.c1"&~"cell23.c2"&~"cell23.c3"|~"cell23.pr_B"->"cell23._y"+
"cell23.c1"&"cell23.c2"&"cell23.c3"&"cell23.sr_B"->"cell23._y"-
"cell23._y"->"cell23.y"-
~("cell23._y")->"cell23.y"+
~"cell10.c1"&~"cell10.c2"|~"cell10.pr_B"->"cell10._y"+
"cell10.c1"&"cell10.c2"&("cell10.n1"&"cell10.n2"|"cell10.n3"&"cell10.n4")&"cell10.sr_B"->"cell10._y"-
"cell10._y"->"cell10.y"-
~("cell10._y")->"cell10.y"+
~"cell3.p1"&~"cell3.c1"->"cell3.y"+
"cell3.c1"&"cell3.n1"->"cell3.y"-
~"cell29.c1"&~"cell29.c2"&~"cell29.c3"&~"cell29.c4"|~"cell29.pr_B"->"cell29.y"+
"cell29.c1"&"cell29.c2"&"cell29.c3"&"cell29.c4"&"cell29.sr_B"->"cell29.y"-
~"cell25.c1"&~"cell25.c2"&~"cell25.c3"->"cell25.y"+
"cell25.c1"&"cell25.c2"&"cell25.c3"->"cell25.y"-
~"cell5.p1"&~"cell5.c1"->"cell5.y"+
"cell5.c1"->"cell5.y"-
~"cell4.p1"&~"cell4.c1"->"cell4._y"-
"cell4.c1"->"cell4._y"+
"cell4._y"->"cell4.y"-
~("cell4._y")->"cell4.y"+
~"cell31.p1"&~"cell31.p2"&~"cell31.p3"&~"cell31.p4"->"cell31.y"+
"cell31.n1"|"cell31.n2"->"cell31.y"-
~"cell27.c1"&~"cell27.c2"&~"cell27.c3"&~"cell27.c4"|~"cell27.pr_B"->"cell27._y"+
"cell27.c1"&"cell27.c2"&"cell27.c3"&"cell27.c4"&"cell27.sr_B"->"cell27._y"-
"cell27._y"->"cell27.y"-
~("cell27._y")->"cell27.y"+
~"cell20.c1"&~"cell20.c2"->"cell20.y"+
"cell20.c1"&"cell20.c2"->"cell20.y"-
~"cell9.p1"&~"cell9.p2"&~"cell9.p3"&~"cell9.c1"|~"cell9.p4"&~"cell9.p5"&~"cell9.c1"|~"cell9.pr_B"->"cell9.y"+
"cell9.c1"&"cell9.n1"&"cell9.n2"&"cell9.sr_B"->"cell9.y"-
~"cell6.p1"&~"cell6.p2"&~"cell6.c1"->"cell6.y"+
"cell6.c1"&"cell6.n1"->"cell6.y"-
~"cell2.p1"&~"cell2.c1"|~"cell2.pr_B"->"cell2.y"-
"cell2.c1"&"cell2.n1"&"cell2.n2"&"cell2.sr_B"->"cell2.y"+

60
test/unit_tests/async_instantiate/test.act
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@@ -1,60 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_async.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
open tmpl::dataflow_neuro;
A_1C1P2N_RB_X1 cell1;
A_1C1P2N_R_X1 cell2;
A_1C1P_1N_X1 cell3;
A_1C1P_B cell4;
A_1C1P cell5;
A_1C2P1N_X1 cell6;
A_1C2P_B_X1 cell7;
A_1C2P cell8;
A_1C3P2P2N_R_X1 cell9;
A_2C2N2N_RB_X1 cell10;
A_2C2N2N_RB_X2 cell11;
A_2C2N2N_RB_X4 cell12;
A_2C2N2N_R_X1 cell13;
A_2C2N_R_B_X2 cell14;
A_2C2N_R_B_X4 cell15;
A_2C2N_R_X1 cell16;
A_2C_B_X1 cell17;
A_2C_RB_X1 cell18;
A_2C_R_X1 cell19;
A_2C_X1 cell20;
A_3C_RB_X1 cell21;
A_3C_RB_X2 cell22;
A_3C_RB_X4 cell23;
A_3C_R_X1 cell24;
A_3C_X1 cell25;
A_4C_RB_X1 cell26;
A_4C_RB_X2 cell27;
A_4C_RB_X4 cell28;
A_4C_R_X1 cell29;
A_4P1N1N_B_X1 cell30;
A_4P1N1N_X1 cell31;

0
test/unit_tests/async_instantiate/test.prsim
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test/unit_tests/bd-fifo-register-fifo-bd/run/prsim.out
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test/unit_tests/bd-fifo-register-fifo-bd/run/prsim.pdf
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test/unit_tests/bd-fifo-register-fifo-bd/run/test.prs
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64
test/unit_tests/bd-fifo-register-fifo-bd/test.act
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@@ -1,64 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import "../../dataflow_neuro/interfaces.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc fifo_reg_fifo_3x5x8 (bd<3+5+1> in; Mx1of2<5> data[8]; bd<8> out; bool? dly_cfg[4]){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
bd2qdi<9,4> _bd2qdi(.in = in, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
fifo<9,5> fifo_pre(.in = _bd2qdi.out, .reset_B = _reset_B, .supply = supply);
// Make a register array with 3 bit address (-> 8 registers),
// each register holding 5 bits.
registerA_wr_array<3,5,8> reg(.in = fifo_pre.out, .data = data,
.reset_B = _reset_B, .supply = supply);
fifo<8,5> fifo_post(.in = reg.out, .reset_B = _reset_B, .supply = supply);
qdi2bd<8,4> _qdi2bd(.in = fifo_post.out, .out = out, .dly_cfg = dly_cfg, .reset_B = _reset_B, .supply = supply);
}
// fifo_decoder_neurons_encoder_fifo e;
fifo_reg_fifo_3x5x8 b;

202
test/unit_tests/bd-fifo-register-fifo-bd/test.prsim
View File

@@ -1,202 +0,0 @@
watchall
set-bd-channel-neutral "b.in" 9
# set b.in.r 0
set b.out.a 0
set b.dly_cfg[0] 1
set b.dly_cfg[1] 1
set b.dly_cfg[2] 1
set b.dly_cfg[3] 1
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
assert b.in.a 0
assert-bd-channel-neutral "b.out" 8
system "echo '[] Sending packet write 0s to reg0'"
set-bd-channel-valid "b.in" 9 256
cycle
assert b.in.a 1
# assert b.in.v 1
assert-var-int "b.data[0]" 5 0
system "echo '[] Removing input'"
set-bd-channel-neutral "b.in" 9
cycle
assert b.in.a 0
# assert b.in.v 0
assert-var-int "b.data[0]" 5 0
# system "echo '[] Sending packet write 0s to reg0'"
# set-qdi-channel-valid "b.in" 9 256
# cycle
# assert b.in.a 1
# assert b.in.v 1
# assert-var-int "b.data[0]" 5 0
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# assert-var-int "b.data[0]" 5 0
system "echo '[] Sending packet write 01100=12 to reg0'"
set-bd-channel-valid "b.in" 9 352
cycle
assert b.in.a 1
# assert b.in.v 1
assert-var-int "b.data[0]" 5 12
system "echo '[] Removing input'"
set-bd-channel-neutral "b.in" 9
cycle
assert b.in.a 0
# assert b.in.v 0
assert-var-int "b.data[0]" 5 12
# system "echo '[] Sending packet write 0s to reg1'"
# set-qdi-channel-valid "b.in" 9 257
# cycle
# assert b.in.a 1
# assert b.in.v 1
# assert-var-int "b.data[1]" 5 0
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# system "echo '[] Sending packet write 0s to reg2'"
# set-qdi-channel-valid "b.in" 9 258
# cycle
# assert b.in.a 1
# assert b.in.v 1
# assert-var-int "b.data[2]" 5 0
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# assert-var-int "b.data[2]" 5 0
# system "echo '[] Sending packet write 0s to reg3'"
# set-qdi-channel-valid "b.in" 9 259
# cycle
# assert b.in.a 1
# assert b.in.v 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# system "echo '[] Sending packet write 0s to reg4'"
# set-qdi-channel-valid "b.in" 9 260
# cycle
# assert b.in.a 1
# assert b.in.v 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# system "echo '[] Sending packet write 0s to reg5'"
# set-qdi-channel-valid "b.in" 9 261
# cycle
# assert b.in.a 1
# assert b.in.v 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# system "echo '[] Sending packet write 0s to reg6'"
# set-qdi-channel-valid "b.in" 9 262
# cycle
# assert b.in.a 1
# assert b.in.v 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# system "echo '[] Sending packet write 0s to reg7'"
# set-qdi-channel-valid "b.in" 9 263
# cycle
# assert b.in.a 1
# assert b.in.v 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert b.in.a 0
# assert b.in.v 0
# assert-var-int "b.data[2]" 5 0
# assert-var-int "b.data[3]" 5 0
# assert-var-int "b.data[4]" 5 0
# assert-var-int "b.data[5]" 5 0
# assert-var-int "b.data[6]" 5 0
# assert-var-int "b.data[7]" 5 0
system "echo '[] Reading register 0'"
set-bd-channel-valid "b.in" 9 0
cycle
assert-bd-channel-valid "b.out" 8 96
assert b.out.r 1
# assert b.in.v 1
assert b.in.a 1
set b.out.a 1
cycle
assert-bd-channel-neutral "b.out" 8
assert b.in.a 1
system "echo '[] Removing input'"
set-bd-channel-neutral "b.in" 9
cycle
assert b.in.a 0
set b.out.a 0
cycle
# system "echo '[] Reading register 1'"
# set-qdi-channel-valid "b.in" 9 1
# cycle
# assert-qdi-channel-valid "b.out" 8 1
# assert b.in.v 1
# assert b.in.a 1
# set b.out.a 1
# set b.out.v 1
# cycle
# assert b.in.a 1
# system "echo '[] Removing input'"
# set-qdi-channel-neutral "b.in" 9
# cycle
# assert-qdi-channel-neutral "b.out" 8
# set b.out.a 0
# set b.out.v 0
# cycle
# assert b.in.a 0
# assert b.in.v 0

615
test/unit_tests/bd2qdi_5/run/prsim.out
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@@ -1,615 +0,0 @@
b.b._out_a_BX_f[0] b.b.dly.dly[5].__y b.b.dly.mu2[0]._s b.b._inB[1] b.b.dly.dly[9].__y b.in.r b.b._inB[4] b.b.dly.dly[6].y b.in.d[1] b.b.dly.dly[3].a b.in.d[4] b.b.dly.dly[11].__y b.b._reqX b.b._en_X_f[0] b.b.dly.dly[13].y b.b.dly.dly[4]._y b.dly_cfg[3] b.in.d[2] b.b.dly.dly[11].y b.b.dly.dly[0].a b.b._en_X_t[0] b.b.dly.mu2[3].b b.dly_cfg[2] b.b._out_a_BX_t[0] b.b._reqXX[0] b.out.v b.b.dly.dly[7].___y b.b._out_a_B b.b._inB[2] b.b._inB[0] b.b.dly._a[1] b.dly_cfg[1] b.b.dly.dly[8].__y b.b.dly.dly[4].___y b.in.d[0] b.b.dly.dly[8]._y b.b.dly.dly[0].__y b.dly_cfg[0] b.b.dly.dly[7].a b.b.req_buf._y b.b.dly.dly[8].y b.b.en_buf_f.buf2._y b.b.dly.dly[10].y b.b.dly.dly[3].___y b.b.dly.mu2[1]._y b.b.dly.dly[5].y b.b.dly._a[2] b.b.dly.dly[6]._y b.b.dly.mu2[3]._s b.b.dly.dly[7].y b.b.en_buf_t.buf2._y b.b._en b.b.dly._a[3] b.b.dly.dly[1].___y b.out.a b.in.d[3] b.b.dly.dly[2]._y b.b.dly.dly[7].__y b.b._req b.b.dly.dly[12].___y b.b.dly.dly[12].y b.b.dly.dly[8].___y b.b.dly.dly[1].a b.b.dly.dly[9].___y b.b.dly.dly[3].y b.b.dly.dly[2].y b.b.dly.dly[14].___y b.b._inB[3] b.b.dly.mu2[0]._y b.b.dly.dly[6].___y b.b.dly.and2[0]._y b.b.dly.dly[3]._y b.b.dly.dly[10].__y b.b.out_a_B_buf_t.buf2._y b.b.dly.mu2[3]._y b.b.req_bufarray.buf2._y b.b.dly.dly[5]._y b.b.dly.mu2[1]._s b.b.dly.dly[4].y b.b.dly.dly[1]._y b.b.dly.and2[3]._y b.b.dly.dly[13].___y b.b.dly.dly[0]._y b.b.dly.dly[11]._y b.b.dly.dly[14].__y b.b.dly.dly[1].__y b.b.dly.mu2[2]._y b.b.dly.and2[1]._y b.b.out_a_B_buf_f.buf2._y b.b.dly.dly[9].y b.b.dly.dly[0].___y b.b.dly.dly[7]._y b.b.dly.dly[13]._y b.b.dly.dly[4].__y b.b.dly.and2[2]._y b.b.dly.dly[12].__y b.b.dly.dly[11].___y b.b.dly.dly[1].y b.b.dly.dly[12]._y b.b.dly.dly[2].__y b.b.dly.dly[14]._y b.b.dly.dly[5].___y b.b.dly.dly[2].___y b.b.dly.dly[0].y b.b.dly.dly[3].__y b.b.dly.mu2[2]._s b.b.dly.dly[13].__y b.b.dly.dly[10].___y b.b.dly.dly[9]._y b.b.dly.dly[6].__y b.b.dly.dly[10]._y
87848 b.out.a : 0
87848 Reset : 0
87848 b.in.r : 0
87848 b.dly_cfg[3] : 1
87848 b.dly_cfg[2] : 1
87848 b.in.d[4] : 0
87848 b.out.v : 0
87848 b.dly_cfg[1] : 1
87848 b.in.d[3] : 1
87848 b.in.d[2] : 0
87848 b.dly_cfg[0] : 1
87848 b.in.d[1] : 0
87848 b.in.d[0] : 1
87849 b.b.dly.mu2[1]._s : 0 [by b.dly_cfg[1]:=1]
87849 b.b._inB[3] : 0 [by b.in.d[3]:=1]
87851 b.b._inB[0] : 0 [by b.in.d[0]:=1]
88130 b.b.dly.mu2[0]._s : 0 [by b.dly_cfg[0]:=1]
88270 b.b._inB[4] : 1 [by b.in.d[4]:=0]
88616 b.b._inB[1] : 1 [by b.in.d[1]:=0]
101697 b.b.dly.and2[0]._y : 1 [by b.in.r:=0]
102191 b.b.dly.mu2[2]._s : 0 [by b.dly_cfg[2]:=1]
108053 b.b._inB[2] : 1 [by b.in.d[2]:=0]
112660 b.b.dly.mu2[3]._s : 0 [by b.dly_cfg[3]:=1]
117628 b._reset_B : 1 [by Reset:=0]
118179 b.b.reset_buf._y : 0 [by b._reset_B:=1]
119250 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
120204 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
121285 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
121303 b.b.f_buf_func[4]._y : X [by b.b._reset_BXX[0]:=1]
122267 b.b.f_buf_func[2]._y : X [by b.b._reset_BXX[0]:=1]
124138 b.b.dly.dly[0].a : 0 [by b.b.dly.and2[0]._y:=1]
125288 b.b.t_buf_func[3]._y : X [by b.b._reset_BXX[0]:=1]
125298 b.b.t_buf_func[0]._y : X [by b.b._reset_BXX[0]:=1]
125501 b.b.t_buf_func[0].y : X [by b.b.t_buf_func[0]._y:=X]
125790 b.b.t_buf_func[3].y : X [by b.b.t_buf_func[3]._y:=X]
128898 b.b.dly.dly[0]._y : 1 [by b.b.dly.dly[0].a:=0]
130752 b.b.dly.dly[0].__y : 0 [by b.b.dly.dly[0]._y:=1]
130891 b.b.dly.dly[0].___y : 1 [by b.b.dly.dly[0].__y:=0]
136562 b.b._en : 1 [by b.out.v:=0]
136573 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
136631 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
136835 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
139501 b.b._out_a_B : 1 [by b.out.a:=0]
139502 b.b.out_a_B_buf_f.buf2._y : 0 [by b.b._out_a_B:=1]
139516 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
139539 b.b._out_a_BX_t[0] : 1 [by b.b.out_a_B_buf_f.buf2._y:=0]
140255 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]
143851 b.b.f_buf_func[2].y : X [by b.b.f_buf_func[2]._y:=X]
166204 b.b.f_buf_func[4].y : X [by b.b.f_buf_func[4]._y:=X]
167237 b.b.dly.dly[0].y : 0 [by b.b.dly.dly[0].___y:=1]
167349 b.b.dly.mu2[0]._y : 1 [by b.b.dly.dly[0].y:=0]
175755 b.b.f_buf_func[1]._y : X [by b.b._reset_BXX[0]:=1]
175795 b.b.f_buf_func[1].y : X [by b.b.f_buf_func[1]._y:=X]
188359 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
214861 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
215118 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
215205 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
215499 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
215500 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
217306 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
219313 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
220522 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
221112 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
221290 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
222093 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
222257 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
224452 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
224474 b.b.dly.and2[2]._y : 1 [by b.b.dly._a[2]:=0]
225321 b.b.dly.dly[3].a : 0 [by b.b.dly.and2[2]._y:=1]
255449 b.b.dly.dly[3]._y : 1 [by b.b.dly.dly[3].a:=0]
255582 b.b.dly.dly[3].__y : 0 [by b.b.dly.dly[3]._y:=1]
271244 b.b.dly.dly[3].___y : 1 [by b.b.dly.dly[3].__y:=0]
271603 b.b.dly.dly[3].y : 0 [by b.b.dly.dly[3].___y:=1]
285719 b.b.dly.dly[4]._y : 1 [by b.b.dly.dly[3].y:=0]
285940 b.b.dly.dly[4].__y : 0 [by b.b.dly.dly[4]._y:=1]
285947 b.b.dly.dly[4].___y : 1 [by b.b.dly.dly[4].__y:=0]
285977 b.b.dly.dly[4].y : 0 [by b.b.dly.dly[4].___y:=1]
292690 b.b.dly.dly[5]._y : 1 [by b.b.dly.dly[4].y:=0]
350151 b.b.dly.dly[5].__y : 0 [by b.b.dly.dly[5]._y:=1]
350242 b.b.dly.dly[5].___y : 1 [by b.b.dly.dly[5].__y:=0]
352431 b.b.dly.dly[5].y : 0 [by b.b.dly.dly[5].___y:=1]
352438 b.b.dly.dly[6]._y : 1 [by b.b.dly.dly[5].y:=0]
355225 b.b.dly.dly[6].__y : 0 [by b.b.dly.dly[6]._y:=1]
355331 b.b.dly.dly[6].___y : 1 [by b.b.dly.dly[6].__y:=0]
355409 b.b.dly.dly[6].y : 0 [by b.b.dly.dly[6].___y:=1]
355684 b.b.dly.mu2[2]._y : 1 [by b.b.dly.dly[6].y:=0]
374680 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
375135 b.b.dly.and2[3]._y : 1 [by b.b.dly._a[3]:=0]
375147 b.b.dly.dly[7].a : 0 [by b.b.dly.and2[3]._y:=1]
375551 b.b.dly.dly[7]._y : 1 [by b.b.dly.dly[7].a:=0]
375563 b.b.dly.dly[7].__y : 0 [by b.b.dly.dly[7]._y:=1]
381479 b.b.dly.dly[7].___y : 1 [by b.b.dly.dly[7].__y:=0]
385755 b.b.dly.dly[7].y : 0 [by b.b.dly.dly[7].___y:=1]
388654 b.b.dly.dly[8]._y : 1 [by b.b.dly.dly[7].y:=0]
392949 b.b.dly.dly[8].__y : 0 [by b.b.dly.dly[8]._y:=1]
392951 b.b.dly.dly[8].___y : 1 [by b.b.dly.dly[8].__y:=0]
397486 b.b.dly.dly[8].y : 0 [by b.b.dly.dly[8].___y:=1]
398735 b.b.dly.dly[9]._y : 1 [by b.b.dly.dly[8].y:=0]
402234 b.b.dly.dly[9].__y : 0 [by b.b.dly.dly[9]._y:=1]
402400 b.b.dly.dly[9].___y : 1 [by b.b.dly.dly[9].__y:=0]
402475 b.b.dly.dly[9].y : 0 [by b.b.dly.dly[9].___y:=1]
402820 b.b.dly.dly[10]._y : 1 [by b.b.dly.dly[9].y:=0]
402958 b.b.dly.dly[10].__y : 0 [by b.b.dly.dly[10]._y:=1]
408221 b.b.dly.dly[10].___y : 1 [by b.b.dly.dly[10].__y:=0]
408223 b.b.dly.dly[10].y : 0 [by b.b.dly.dly[10].___y:=1]
452140 b.b.dly.dly[11]._y : 1 [by b.b.dly.dly[10].y:=0]
452141 b.b.dly.dly[11].__y : 0 [by b.b.dly.dly[11]._y:=1]
452689 b.b.dly.dly[11].___y : 1 [by b.b.dly.dly[11].__y:=0]
452700 b.b.dly.dly[11].y : 0 [by b.b.dly.dly[11].___y:=1]
453070 b.b.dly.dly[12]._y : 1 [by b.b.dly.dly[11].y:=0]
453137 b.b.dly.dly[12].__y : 0 [by b.b.dly.dly[12]._y:=1]
455778 b.b.dly.dly[12].___y : 1 [by b.b.dly.dly[12].__y:=0]
455794 b.b.dly.dly[12].y : 0 [by b.b.dly.dly[12].___y:=1]
460356 b.b.dly.dly[13]._y : 1 [by b.b.dly.dly[12].y:=0]
460884 b.b.dly.dly[13].__y : 0 [by b.b.dly.dly[13]._y:=1]
463319 b.b.dly.dly[13].___y : 1 [by b.b.dly.dly[13].__y:=0]
490199 b.b.dly.dly[13].y : 0 [by b.b.dly.dly[13].___y:=1]
514124 b.b.dly.dly[14]._y : 1 [by b.b.dly.dly[13].y:=0]
527165 b.b.dly.dly[14].__y : 0 [by b.b.dly.dly[14]._y:=1]
527167 b.b.dly.dly[14].___y : 1 [by b.b.dly.dly[14].__y:=0]
588125 b.b.dly.mu2[3].b : 0 [by b.b.dly.dly[14].___y:=1]
588128 b.b.dly.mu2[3]._y : 1 [by b.b.dly.mu2[3].b:=0]
588157 b.b._req : 0 [by b.b.dly.mu2[3]._y:=1]
588474 b.b.req_buf._y : 1 [by b.b._req:=0]
590075 b.b._reqX : 0 [by b.b.req_buf._y:=1]
590228 b.b.req_bufarray.buf2._y : 1 [by b.b._reqX:=0]
590272 b.b._reqXX[0] : 0 [by b.b.req_bufarray.buf2._y:=1]
[] set Reset 1
590272 Reset : 1
593033 b._reset_B : 0 [by Reset:=1]
606716 b.b.reset_buf._y : 1 [by b._reset_B:=0]
606717 b.b._reset_BX : 0 [by b.b.reset_buf._y:=1]
606934 b.b.reset_bufarray.buf2._y : 1 [by b.b._reset_BX:=0]
606956 b.b._reset_BXX[0] : 0 [by b.b.reset_bufarray.buf2._y:=1]
606957 b.b.f_buf_func[1]._y : 1 [by b.b._reset_BXX[0]:=0]
607115 b.b.t_buf_func[0]._y : 1 [by b.b._reset_BXX[0]:=0]
608244 b.b.f_buf_func[1].y : 0 [by b.b.f_buf_func[1]._y:=1]
608537 b.b.f_buf_func[2]._y : 1 [by b.b._reset_BXX[0]:=0]
608682 b.b.f_buf_func[2].y : 0 [by b.b.f_buf_func[2]._y:=1]
609347 b.b.t_buf_func[0].y : 0 [by b.b.t_buf_func[0]._y:=1]
616301 b.b.f_buf_func[4]._y : 1 [by b.b._reset_BXX[0]:=0]
619133 b.b.f_buf_func[4].y : 0 [by b.b.f_buf_func[4]._y:=1]
626632 b.b.t_buf_func[3]._y : 1 [by b.b._reset_BXX[0]:=0]
632986 b.b.t_buf_func[3].y : 0 [by b.b.t_buf_func[3]._y:=1]
[] set Reset 0
632986 Reset : 0
632987 b._reset_B : 1 [by Reset:=0]
672271 b.b.reset_buf._y : 0 [by b._reset_B:=1]
672433 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
679802 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
679816 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
[] Reset finished, setting data
679816 b.in.d[0] : 0
679816 b.in.d[4] : 1
679816 b.in.d[2] : 1
679816 b.in.d[1] : 1
679816 b.in.d[3] : 0
679817 b.b._inB[1] : 0 [by b.in.d[1]:=1]
679817 b.b._inB[3] : 1 [by b.in.d[3]:=0]
679823 b.b._inB[0] : 1 [by b.in.d[0]:=0]
679976 b.b._inB[4] : 0 [by b.in.d[4]:=1]
701373 b.b._inB[2] : 0 [by b.in.d[2]:=1]
[] Reset finished, setting req 1
701373 b.in.r : 1
701374 b.b.dly.and2[0]._y : 0 [by b.in.r:=1]
703617 b.b.dly.dly[0].a : 1 [by b.b.dly.and2[0]._y:=0]
703804 b.b.dly.dly[0]._y : 0 [by b.b.dly.dly[0].a:=1]
703805 b.b.dly.dly[0].__y : 1 [by b.b.dly.dly[0]._y:=0]
707987 b.b.dly.dly[0].___y : 0 [by b.b.dly.dly[0].__y:=1]
742769 b.b.dly.dly[0].y : 1 [by b.b.dly.dly[0].___y:=0]
742770 b.b.dly.mu2[0]._y : 0 [by b.b.dly.dly[0].y:=1]
743623 b.b.dly._a[1] : 1 [by b.b.dly.mu2[0]._y:=0]
743628 b.b.dly.and2[1]._y : 0 [by b.b.dly._a[1]:=1]
744519 b.b.dly.dly[1].a : 1 [by b.b.dly.and2[1]._y:=0]
744520 b.b.dly.dly[1]._y : 0 [by b.b.dly.dly[1].a:=1]
744537 b.b.dly.dly[1].__y : 1 [by b.b.dly.dly[1]._y:=0]
747110 b.b.dly.dly[1].___y : 0 [by b.b.dly.dly[1].__y:=1]
755471 b.b.dly.dly[1].y : 1 [by b.b.dly.dly[1].___y:=0]
755474 b.b.dly.dly[2]._y : 0 [by b.b.dly.dly[1].y:=1]
756415 b.b.dly.dly[2].__y : 1 [by b.b.dly.dly[2]._y:=0]
815377 b.b.dly.dly[2].___y : 0 [by b.b.dly.dly[2].__y:=1]
815378 b.b.dly.dly[2].y : 1 [by b.b.dly.dly[2].___y:=0]
815420 b.b.dly.mu2[1]._y : 0 [by b.b.dly.dly[2].y:=1]
818237 b.b.dly._a[2] : 1 [by b.b.dly.mu2[1]._y:=0]
831970 b.b.dly.and2[2]._y : 0 [by b.b.dly._a[2]:=1]
832065 b.b.dly.dly[3].a : 1 [by b.b.dly.and2[2]._y:=0]
832400 b.b.dly.dly[3]._y : 0 [by b.b.dly.dly[3].a:=1]
832408 b.b.dly.dly[3].__y : 1 [by b.b.dly.dly[3]._y:=0]
832442 b.b.dly.dly[3].___y : 0 [by b.b.dly.dly[3].__y:=1]
846329 b.b.dly.dly[3].y : 1 [by b.b.dly.dly[3].___y:=0]
847247 b.b.dly.dly[4]._y : 0 [by b.b.dly.dly[3].y:=1]
847251 b.b.dly.dly[4].__y : 1 [by b.b.dly.dly[4]._y:=0]
893629 b.b.dly.dly[4].___y : 0 [by b.b.dly.dly[4].__y:=1]
896027 b.b.dly.dly[4].y : 1 [by b.b.dly.dly[4].___y:=0]
899242 b.b.dly.dly[5]._y : 0 [by b.b.dly.dly[4].y:=1]
946361 b.b.dly.dly[5].__y : 1 [by b.b.dly.dly[5]._y:=0]
946409 b.b.dly.dly[5].___y : 0 [by b.b.dly.dly[5].__y:=1]
946412 b.b.dly.dly[5].y : 1 [by b.b.dly.dly[5].___y:=0]
946590 b.b.dly.dly[6]._y : 0 [by b.b.dly.dly[5].y:=1]
967567 b.b.dly.dly[6].__y : 1 [by b.b.dly.dly[6]._y:=0]
979466 b.b.dly.dly[6].___y : 0 [by b.b.dly.dly[6].__y:=1]
985417 b.b.dly.dly[6].y : 1 [by b.b.dly.dly[6].___y:=0]
1024902 b.b.dly.mu2[2]._y : 0 [by b.b.dly.dly[6].y:=1]
1025729 b.b.dly._a[3] : 1 [by b.b.dly.mu2[2]._y:=0]
1025902 b.b.dly.and2[3]._y : 0 [by b.b.dly._a[3]:=1]
1026086 b.b.dly.dly[7].a : 1 [by b.b.dly.and2[3]._y:=0]
1026087 b.b.dly.dly[7]._y : 0 [by b.b.dly.dly[7].a:=1]
1026160 b.b.dly.dly[7].__y : 1 [by b.b.dly.dly[7]._y:=0]
1026164 b.b.dly.dly[7].___y : 0 [by b.b.dly.dly[7].__y:=1]
1063452 b.b.dly.dly[7].y : 1 [by b.b.dly.dly[7].___y:=0]
1063548 b.b.dly.dly[8]._y : 0 [by b.b.dly.dly[7].y:=1]
1063684 b.b.dly.dly[8].__y : 1 [by b.b.dly.dly[8]._y:=0]
1063685 b.b.dly.dly[8].___y : 0 [by b.b.dly.dly[8].__y:=1]
1082731 b.b.dly.dly[8].y : 1 [by b.b.dly.dly[8].___y:=0]
1082972 b.b.dly.dly[9]._y : 0 [by b.b.dly.dly[8].y:=1]
1086931 b.b.dly.dly[9].__y : 1 [by b.b.dly.dly[9]._y:=0]
1086943 b.b.dly.dly[9].___y : 0 [by b.b.dly.dly[9].__y:=1]
1090843 b.b.dly.dly[9].y : 1 [by b.b.dly.dly[9].___y:=0]
1091872 b.b.dly.dly[10]._y : 0 [by b.b.dly.dly[9].y:=1]
1091873 b.b.dly.dly[10].__y : 1 [by b.b.dly.dly[10]._y:=0]
1091929 b.b.dly.dly[10].___y : 0 [by b.b.dly.dly[10].__y:=1]
1136935 b.b.dly.dly[10].y : 1 [by b.b.dly.dly[10].___y:=0]
1136936 b.b.dly.dly[11]._y : 0 [by b.b.dly.dly[10].y:=1]
1136973 b.b.dly.dly[11].__y : 1 [by b.b.dly.dly[11]._y:=0]
1160348 b.b.dly.dly[11].___y : 0 [by b.b.dly.dly[11].__y:=1]
1160349 b.b.dly.dly[11].y : 1 [by b.b.dly.dly[11].___y:=0]
1163913 b.b.dly.dly[12]._y : 0 [by b.b.dly.dly[11].y:=1]
1165605 b.b.dly.dly[12].__y : 1 [by b.b.dly.dly[12]._y:=0]
1165618 b.b.dly.dly[12].___y : 0 [by b.b.dly.dly[12].__y:=1]
1182602 b.b.dly.dly[12].y : 1 [by b.b.dly.dly[12].___y:=0]
1182959 b.b.dly.dly[13]._y : 0 [by b.b.dly.dly[12].y:=1]
1182984 b.b.dly.dly[13].__y : 1 [by b.b.dly.dly[13]._y:=0]
1183005 b.b.dly.dly[13].___y : 0 [by b.b.dly.dly[13].__y:=1]
1183006 b.b.dly.dly[13].y : 1 [by b.b.dly.dly[13].___y:=0]
1192654 b.b.dly.dly[14]._y : 0 [by b.b.dly.dly[13].y:=1]
1192655 b.b.dly.dly[14].__y : 1 [by b.b.dly.dly[14]._y:=0]
1192656 b.b.dly.dly[14].___y : 0 [by b.b.dly.dly[14].__y:=1]
1192817 b.b.dly.mu2[3].b : 1 [by b.b.dly.dly[14].___y:=0]
1193854 b.b.dly.mu2[3]._y : 0 [by b.b.dly.mu2[3].b:=1]
1193859 b.b._req : 1 [by b.b.dly.mu2[3]._y:=0]
1194440 b.b.req_buf._y : 0 [by b.b._req:=1]
1194848 b.b._reqX : 1 [by b.b.req_buf._y:=0]
1194859 b.b.req_bufarray.buf2._y : 0 [by b.b._reqX:=1]
1195906 b.b._reqXX[0] : 1 [by b.b.req_bufarray.buf2._y:=0]
1195910 b.b.t_buf_func[1]._y : 0 [by b.b._reqXX[0]:=1]
1195920 b.b.f_buf_func[0]._y : 0 [by b.b._reqXX[0]:=1]
1195924 b.b.f_buf_func[3]._y : 0 [by b.b._reqXX[0]:=1]
1196010 b.b.t_buf_func[2]._y : 0 [by b.b._reqXX[0]:=1]
1196152 b.b.f_buf_func[3].y : 1 [by b.b.f_buf_func[3]._y:=0]
1196853 b.b.t_buf_func[2].y : 1 [by b.b.t_buf_func[2]._y:=0]
1197114 b.b.t_buf_func[1].y : 1 [by b.b.t_buf_func[1]._y:=0]
1204375 b.b.f_buf_func[0].y : 1 [by b.b.f_buf_func[0]._y:=0]
1227350 b.b.t_buf_func[4]._y : 0 [by b.b._reqXX[0]:=1]
1228809 b.b.t_buf_func[4].y : 1 [by b.b.t_buf_func[4]._y:=0]
[] Receiving val out
1228809 b.out.v : 1
1228879 b.b.inack_ctl._y : 0 [by b.out.v:=1]
1279301 b.in.a : 1 [by b.b.inack_ctl._y:=0]
1279312 b.b._en : 0 [by b.in.a:=1]
1279315 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
1279366 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
1280463 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
1280527 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
[] Changing some input data
1280527 b.in.d[0] : 1
1289179 b.b._inB[0] : 0 [by b.in.d[0]:=1]
[] Removing req
[] Changing more data
1289179 b.in.r : 0
1289179 b.in.d[4] : 0
1289260 b.b.dly.and2[0]._y : 1 [by b.in.r:=0]
1300256 b.b._inB[4] : 1 [by b.in.d[4]:=0]
1307243 b.b.dly.dly[0].a : 0 [by b.b.dly.and2[0]._y:=1]
1307335 b.b.dly.dly[0]._y : 1 [by b.b.dly.dly[0].a:=0]
1315646 b.b.dly.dly[0].__y : 0 [by b.b.dly.dly[0]._y:=1]
1317390 b.b.dly.dly[0].___y : 1 [by b.b.dly.dly[0].__y:=0]
1318003 b.b.dly.dly[0].y : 0 [by b.b.dly.dly[0].___y:=1]
1332025 b.b.dly.mu2[0]._y : 1 [by b.b.dly.dly[0].y:=0]
1332070 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
1333067 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
1334716 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
1335241 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
1336141 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
1336193 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
1336200 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
1351812 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
1358279 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
1358281 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
1358635 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
1358768 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
1358769 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
1358773 b.b.dly.and2[2]._y : 1 [by b.b.dly._a[2]:=0]
1359319 b.b.dly.dly[3].a : 0 [by b.b.dly.and2[2]._y:=1]
1404882 b.b.dly.dly[3]._y : 1 [by b.b.dly.dly[3].a:=0]
1404883 b.b.dly.dly[3].__y : 0 [by b.b.dly.dly[3]._y:=1]
1417261 b.b.dly.dly[3].___y : 1 [by b.b.dly.dly[3].__y:=0]
1417340 b.b.dly.dly[3].y : 0 [by b.b.dly.dly[3].___y:=1]
1419773 b.b.dly.dly[4]._y : 1 [by b.b.dly.dly[3].y:=0]
1419861 b.b.dly.dly[4].__y : 0 [by b.b.dly.dly[4]._y:=1]
1427643 b.b.dly.dly[4].___y : 1 [by b.b.dly.dly[4].__y:=0]
1455970 b.b.dly.dly[4].y : 0 [by b.b.dly.dly[4].___y:=1]
1456029 b.b.dly.dly[5]._y : 1 [by b.b.dly.dly[4].y:=0]
1456059 b.b.dly.dly[5].__y : 0 [by b.b.dly.dly[5]._y:=1]
1457526 b.b.dly.dly[5].___y : 1 [by b.b.dly.dly[5].__y:=0]
1517030 b.b.dly.dly[5].y : 0 [by b.b.dly.dly[5].___y:=1]
1536414 b.b.dly.dly[6]._y : 1 [by b.b.dly.dly[5].y:=0]
1537099 b.b.dly.dly[6].__y : 0 [by b.b.dly.dly[6]._y:=1]
1553814 b.b.dly.dly[6].___y : 1 [by b.b.dly.dly[6].__y:=0]
1553941 b.b.dly.dly[6].y : 0 [by b.b.dly.dly[6].___y:=1]
1554110 b.b.dly.mu2[2]._y : 1 [by b.b.dly.dly[6].y:=0]
1554153 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
1554165 b.b.dly.and2[3]._y : 1 [by b.b.dly._a[3]:=0]
1555444 b.b.dly.dly[7].a : 0 [by b.b.dly.and2[3]._y:=1]
1555677 b.b.dly.dly[7]._y : 1 [by b.b.dly.dly[7].a:=0]
1555680 b.b.dly.dly[7].__y : 0 [by b.b.dly.dly[7]._y:=1]
1555718 b.b.dly.dly[7].___y : 1 [by b.b.dly.dly[7].__y:=0]
1555719 b.b.dly.dly[7].y : 0 [by b.b.dly.dly[7].___y:=1]
1568471 b.b.dly.dly[8]._y : 1 [by b.b.dly.dly[7].y:=0]
1568563 b.b.dly.dly[8].__y : 0 [by b.b.dly.dly[8]._y:=1]
1571290 b.b.dly.dly[8].___y : 1 [by b.b.dly.dly[8].__y:=0]
1571292 b.b.dly.dly[8].y : 0 [by b.b.dly.dly[8].___y:=1]
1571293 b.b.dly.dly[9]._y : 1 [by b.b.dly.dly[8].y:=0]
1572794 b.b.dly.dly[9].__y : 0 [by b.b.dly.dly[9]._y:=1]
1572796 b.b.dly.dly[9].___y : 1 [by b.b.dly.dly[9].__y:=0]
1572814 b.b.dly.dly[9].y : 0 [by b.b.dly.dly[9].___y:=1]
1572933 b.b.dly.dly[10]._y : 1 [by b.b.dly.dly[9].y:=0]
1578653 b.b.dly.dly[10].__y : 0 [by b.b.dly.dly[10]._y:=1]
1578661 b.b.dly.dly[10].___y : 1 [by b.b.dly.dly[10].__y:=0]
1578715 b.b.dly.dly[10].y : 0 [by b.b.dly.dly[10].___y:=1]
1629253 b.b.dly.dly[11]._y : 1 [by b.b.dly.dly[10].y:=0]
1629258 b.b.dly.dly[11].__y : 0 [by b.b.dly.dly[11]._y:=1]
1630325 b.b.dly.dly[11].___y : 1 [by b.b.dly.dly[11].__y:=0]
1630326 b.b.dly.dly[11].y : 0 [by b.b.dly.dly[11].___y:=1]
1630464 b.b.dly.dly[12]._y : 1 [by b.b.dly.dly[11].y:=0]
1630465 b.b.dly.dly[12].__y : 0 [by b.b.dly.dly[12]._y:=1]
1630529 b.b.dly.dly[12].___y : 1 [by b.b.dly.dly[12].__y:=0]
1630652 b.b.dly.dly[12].y : 0 [by b.b.dly.dly[12].___y:=1]
1630654 b.b.dly.dly[13]._y : 1 [by b.b.dly.dly[12].y:=0]
1630691 b.b.dly.dly[13].__y : 0 [by b.b.dly.dly[13]._y:=1]
1630834 b.b.dly.dly[13].___y : 1 [by b.b.dly.dly[13].__y:=0]
1630885 b.b.dly.dly[13].y : 0 [by b.b.dly.dly[13].___y:=1]
1631327 b.b.dly.dly[14]._y : 1 [by b.b.dly.dly[13].y:=0]
1631338 b.b.dly.dly[14].__y : 0 [by b.b.dly.dly[14]._y:=1]
1631339 b.b.dly.dly[14].___y : 1 [by b.b.dly.dly[14].__y:=0]
1631348 b.b.dly.mu2[3].b : 0 [by b.b.dly.dly[14].___y:=1]
1631373 b.b.dly.mu2[3]._y : 1 [by b.b.dly.mu2[3].b:=0]
1641626 b.b._req : 0 [by b.b.dly.mu2[3]._y:=1]
1645147 b.b.req_buf._y : 1 [by b.b._req:=0]
1645292 b.b._reqX : 0 [by b.b.req_buf._y:=1]
1661460 b.b.req_bufarray.buf2._y : 1 [by b.b._reqX:=0]
1661690 b.b._reqXX[0] : 0 [by b.b.req_bufarray.buf2._y:=1]
[] Receiving ack out
1661690 b.out.a : 1
1662381 b.b._out_a_B : 0 [by b.out.a:=1]
1662395 b.b.out_a_B_buf_t.buf2._y : 1 [by b.b._out_a_B:=0]
1663924 b.b.out_a_B_buf_f.buf2._y : 1 [by b.b._out_a_B:=0]
1664006 b.b._out_a_BX_f[0] : 0 [by b.b.out_a_B_buf_t.buf2._y:=1]
1664007 b.b.f_buf_func[3]._y : 1 [by b.b._out_a_BX_f[0]:=0]
1664008 b.b.f_buf_func[3].y : 0 [by b.b.f_buf_func[3]._y:=1]
1664017 b.b.f_buf_func[0]._y : 1 [by b.b._out_a_BX_f[0]:=0]
1670518 b.b.f_buf_func[0].y : 0 [by b.b.f_buf_func[0]._y:=1]
1681436 b.b._out_a_BX_t[0] : 0 [by b.b.out_a_B_buf_f.buf2._y:=1]
1681568 b.b.t_buf_func[4]._y : 1 [by b.b._out_a_BX_t[0]:=0]
1681569 b.b.t_buf_func[4].y : 0 [by b.b.t_buf_func[4]._y:=1]
1682075 b.b.t_buf_func[1]._y : 1 [by b.b._out_a_BX_t[0]:=0]
1682092 b.b.t_buf_func[1].y : 0 [by b.b.t_buf_func[1]._y:=1]
1683229 b.b.t_buf_func[2]._y : 1 [by b.b._out_a_BX_t[0]:=0]
1683381 b.b.t_buf_func[2].y : 0 [by b.b.t_buf_func[2]._y:=1]
1683381 b.out.v : 0
1686364 b.b.inack_ctl._y : 1 [by b.out.v:=0]
1686367 b.in.a : 0 [by b.b.inack_ctl._y:=1]
1686791 b.b._en : 1 [by b.in.a:=0]
1686797 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
1689258 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
1689379 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
1690209 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
[] Set ack out 0
1690209 b.out.a : 0
1713141 b.b._out_a_B : 1 [by b.out.a:=0]
1713143 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
1713335 b.b.out_a_B_buf_f.buf2._y : 0 [by b.b._out_a_B:=1]
1713473 b.b._out_a_BX_t[0] : 1 [by b.b.out_a_B_buf_f.buf2._y:=0]
1713746 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]
[] Again!!! setting data
1713746 b.in.d[0] : 0
1713746 b.in.d[2] : 0
1713746 b.in.d[1] : 0
1713763 b.b._inB[2] : 1 [by b.in.d[2]:=0]
1713763 b.b._inB[0] : 1 [by b.in.d[0]:=0]
1714172 b.b._inB[1] : 1 [by b.in.d[1]:=0]
[] Again!!! setting req 1
1714172 b.in.r : 1
1714173 b.b.dly.and2[0]._y : 0 [by b.in.r:=1]
1714174 b.b.dly.dly[0].a : 1 [by b.b.dly.and2[0]._y:=0]
1715200 b.b.dly.dly[0]._y : 0 [by b.b.dly.dly[0].a:=1]
1715201 b.b.dly.dly[0].__y : 1 [by b.b.dly.dly[0]._y:=0]
1715220 b.b.dly.dly[0].___y : 0 [by b.b.dly.dly[0].__y:=1]
1715388 b.b.dly.dly[0].y : 1 [by b.b.dly.dly[0].___y:=0]
1715927 b.b.dly.mu2[0]._y : 0 [by b.b.dly.dly[0].y:=1]
1716088 b.b.dly._a[1] : 1 [by b.b.dly.mu2[0]._y:=0]
1716261 b.b.dly.and2[1]._y : 0 [by b.b.dly._a[1]:=1]
1718808 b.b.dly.dly[1].a : 1 [by b.b.dly.and2[1]._y:=0]
1733869 b.b.dly.dly[1]._y : 0 [by b.b.dly.dly[1].a:=1]
1733870 b.b.dly.dly[1].__y : 1 [by b.b.dly.dly[1]._y:=0]
1733871 b.b.dly.dly[1].___y : 0 [by b.b.dly.dly[1].__y:=1]
1734261 b.b.dly.dly[1].y : 1 [by b.b.dly.dly[1].___y:=0]
1734468 b.b.dly.dly[2]._y : 0 [by b.b.dly.dly[1].y:=1]
1735301 b.b.dly.dly[2].__y : 1 [by b.b.dly.dly[2]._y:=0]
1735329 b.b.dly.dly[2].___y : 0 [by b.b.dly.dly[2].__y:=1]
1735336 b.b.dly.dly[2].y : 1 [by b.b.dly.dly[2].___y:=0]
1735750 b.b.dly.mu2[1]._y : 0 [by b.b.dly.dly[2].y:=1]
1735754 b.b.dly._a[2] : 1 [by b.b.dly.mu2[1]._y:=0]
1737533 b.b.dly.and2[2]._y : 0 [by b.b.dly._a[2]:=1]
1760407 b.b.dly.dly[3].a : 1 [by b.b.dly.and2[2]._y:=0]
1760573 b.b.dly.dly[3]._y : 0 [by b.b.dly.dly[3].a:=1]
1800443 b.b.dly.dly[3].__y : 1 [by b.b.dly.dly[3]._y:=0]
1809088 b.b.dly.dly[3].___y : 0 [by b.b.dly.dly[3].__y:=1]
1810021 b.b.dly.dly[3].y : 1 [by b.b.dly.dly[3].___y:=0]
1810877 b.b.dly.dly[4]._y : 0 [by b.b.dly.dly[3].y:=1]
1811016 b.b.dly.dly[4].__y : 1 [by b.b.dly.dly[4]._y:=0]
1837225 b.b.dly.dly[4].___y : 0 [by b.b.dly.dly[4].__y:=1]
1837420 b.b.dly.dly[4].y : 1 [by b.b.dly.dly[4].___y:=0]
1837422 b.b.dly.dly[5]._y : 0 [by b.b.dly.dly[4].y:=1]
1890871 b.b.dly.dly[5].__y : 1 [by b.b.dly.dly[5]._y:=0]
1890877 b.b.dly.dly[5].___y : 0 [by b.b.dly.dly[5].__y:=1]
1891131 b.b.dly.dly[5].y : 1 [by b.b.dly.dly[5].___y:=0]
1891139 b.b.dly.dly[6]._y : 0 [by b.b.dly.dly[5].y:=1]
1891140 b.b.dly.dly[6].__y : 1 [by b.b.dly.dly[6]._y:=0]
1891146 b.b.dly.dly[6].___y : 0 [by b.b.dly.dly[6].__y:=1]
1942182 b.b.dly.dly[6].y : 1 [by b.b.dly.dly[6].___y:=0]
1945272 b.b.dly.mu2[2]._y : 0 [by b.b.dly.dly[6].y:=1]
1945498 b.b.dly._a[3] : 1 [by b.b.dly.mu2[2]._y:=0]
1946317 b.b.dly.and2[3]._y : 0 [by b.b.dly._a[3]:=1]
1946318 b.b.dly.dly[7].a : 1 [by b.b.dly.and2[3]._y:=0]
1946324 b.b.dly.dly[7]._y : 0 [by b.b.dly.dly[7].a:=1]
1946326 b.b.dly.dly[7].__y : 1 [by b.b.dly.dly[7]._y:=0]
1949888 b.b.dly.dly[7].___y : 0 [by b.b.dly.dly[7].__y:=1]
1949903 b.b.dly.dly[7].y : 1 [by b.b.dly.dly[7].___y:=0]
1970704 b.b.dly.dly[8]._y : 0 [by b.b.dly.dly[7].y:=1]
1970811 b.b.dly.dly[8].__y : 1 [by b.b.dly.dly[8]._y:=0]
1970904 b.b.dly.dly[8].___y : 0 [by b.b.dly.dly[8].__y:=1]
1972556 b.b.dly.dly[8].y : 1 [by b.b.dly.dly[8].___y:=0]
1976495 b.b.dly.dly[9]._y : 0 [by b.b.dly.dly[8].y:=1]
1977253 b.b.dly.dly[9].__y : 1 [by b.b.dly.dly[9]._y:=0]
1979876 b.b.dly.dly[9].___y : 0 [by b.b.dly.dly[9].__y:=1]
1980592 b.b.dly.dly[9].y : 1 [by b.b.dly.dly[9].___y:=0]
1980593 b.b.dly.dly[10]._y : 0 [by b.b.dly.dly[9].y:=1]
1982333 b.b.dly.dly[10].__y : 1 [by b.b.dly.dly[10]._y:=0]
1982334 b.b.dly.dly[10].___y : 0 [by b.b.dly.dly[10].__y:=1]
1994486 b.b.dly.dly[10].y : 1 [by b.b.dly.dly[10].___y:=0]
2022685 b.b.dly.dly[11]._y : 0 [by b.b.dly.dly[10].y:=1]
2022686 b.b.dly.dly[11].__y : 1 [by b.b.dly.dly[11]._y:=0]
2022692 b.b.dly.dly[11].___y : 0 [by b.b.dly.dly[11].__y:=1]
2022693 b.b.dly.dly[11].y : 1 [by b.b.dly.dly[11].___y:=0]
2062182 b.b.dly.dly[12]._y : 0 [by b.b.dly.dly[11].y:=1]
2083781 b.b.dly.dly[12].__y : 1 [by b.b.dly.dly[12]._y:=0]
2083803 b.b.dly.dly[12].___y : 0 [by b.b.dly.dly[12].__y:=1]
2106311 b.b.dly.dly[12].y : 1 [by b.b.dly.dly[12].___y:=0]
2106318 b.b.dly.dly[13]._y : 0 [by b.b.dly.dly[12].y:=1]
2106383 b.b.dly.dly[13].__y : 1 [by b.b.dly.dly[13]._y:=0]
2106396 b.b.dly.dly[13].___y : 0 [by b.b.dly.dly[13].__y:=1]
2107520 b.b.dly.dly[13].y : 1 [by b.b.dly.dly[13].___y:=0]
2107624 b.b.dly.dly[14]._y : 0 [by b.b.dly.dly[13].y:=1]
2107665 b.b.dly.dly[14].__y : 1 [by b.b.dly.dly[14]._y:=0]
2107666 b.b.dly.dly[14].___y : 0 [by b.b.dly.dly[14].__y:=1]
2107667 b.b.dly.mu2[3].b : 1 [by b.b.dly.dly[14].___y:=0]
2172045 b.b.dly.mu2[3]._y : 0 [by b.b.dly.mu2[3].b:=1]
2185217 b.b._req : 1 [by b.b.dly.mu2[3]._y:=0]
2185218 b.b.req_buf._y : 0 [by b.b._req:=1]
2205043 b.b._reqX : 1 [by b.b.req_buf._y:=0]
2208179 b.b.req_bufarray.buf2._y : 0 [by b.b._reqX:=1]
2209005 b.b._reqXX[0] : 1 [by b.b.req_bufarray.buf2._y:=0]
2209063 b.b.f_buf_func[2]._y : 0 [by b.b._reqXX[0]:=1]
2210838 b.b.f_buf_func[0]._y : 0 [by b.b._reqXX[0]:=1]
2210852 b.b.f_buf_func[0].y : 1 [by b.b.f_buf_func[0]._y:=0]
2211448 b.b.f_buf_func[3]._y : 0 [by b.b._reqXX[0]:=1]
2211804 b.b.f_buf_func[3].y : 1 [by b.b.f_buf_func[3]._y:=0]
2225553 b.b.f_buf_func[1]._y : 0 [by b.b._reqXX[0]:=1]
2225778 b.b.f_buf_func[4]._y : 0 [by b.b._reqXX[0]:=1]
2225883 b.b.f_buf_func[4].y : 1 [by b.b.f_buf_func[4]._y:=0]
2246262 b.b.f_buf_func[2].y : 1 [by b.b.f_buf_func[2]._y:=0]
2261391 b.b.f_buf_func[1].y : 1 [by b.b.f_buf_func[1]._y:=0]
[] Receiving val out
2261391 b.out.v : 1
2261500 b.b.inack_ctl._y : 0 [by b.out.v:=1]
2261501 b.in.a : 1 [by b.b.inack_ctl._y:=0]
2261510 b.b._en : 0 [by b.in.a:=1]
2261511 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
2297905 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
2299463 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
2299464 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
[] Changing some input data
2299464 b.in.d[0] : 1
2299464 b.in.d[2] : 1
2299464 b.in.d[1] : 1
2300214 b.b._inB[1] : 0 [by b.in.d[1]:=1]
2302553 b.b._inB[0] : 0 [by b.in.d[0]:=1]
2348190 b.b._inB[2] : 0 [by b.in.d[2]:=1]
[] Removing req
[] Changing more data
2348190 b.in.r : 0
2354945 b.b.dly.and2[0]._y : 1 [by b.in.r:=0]
2354996 b.b.dly.dly[0].a : 0 [by b.b.dly.and2[0]._y:=1]
2355006 b.b.dly.dly[0]._y : 1 [by b.b.dly.dly[0].a:=0]
2355326 b.b.dly.dly[0].__y : 0 [by b.b.dly.dly[0]._y:=1]
2362908 b.b.dly.dly[0].___y : 1 [by b.b.dly.dly[0].__y:=0]
2362909 b.b.dly.dly[0].y : 0 [by b.b.dly.dly[0].___y:=1]
2362910 b.b.dly.mu2[0]._y : 1 [by b.b.dly.dly[0].y:=0]
2364640 b.b.dly._a[1] : 0 [by b.b.dly.mu2[0]._y:=1]
2366327 b.b.dly.and2[1]._y : 1 [by b.b.dly._a[1]:=0]
2366342 b.b.dly.dly[1].a : 0 [by b.b.dly.and2[1]._y:=1]
2390616 b.b.dly.dly[1]._y : 1 [by b.b.dly.dly[1].a:=0]
2391070 b.b.dly.dly[1].__y : 0 [by b.b.dly.dly[1]._y:=1]
2391386 b.b.dly.dly[1].___y : 1 [by b.b.dly.dly[1].__y:=0]
2391387 b.b.dly.dly[1].y : 0 [by b.b.dly.dly[1].___y:=1]
2391770 b.b.dly.dly[2]._y : 1 [by b.b.dly.dly[1].y:=0]
2399233 b.b.dly.dly[2].__y : 0 [by b.b.dly.dly[2]._y:=1]
2399253 b.b.dly.dly[2].___y : 1 [by b.b.dly.dly[2].__y:=0]
2400576 b.b.dly.dly[2].y : 0 [by b.b.dly.dly[2].___y:=1]
2400663 b.b.dly.mu2[1]._y : 1 [by b.b.dly.dly[2].y:=0]
2407385 b.b.dly._a[2] : 0 [by b.b.dly.mu2[1]._y:=1]
2407397 b.b.dly.and2[2]._y : 1 [by b.b.dly._a[2]:=0]
2407542 b.b.dly.dly[3].a : 0 [by b.b.dly.and2[2]._y:=1]
2408443 b.b.dly.dly[3]._y : 1 [by b.b.dly.dly[3].a:=0]
2409792 b.b.dly.dly[3].__y : 0 [by b.b.dly.dly[3]._y:=1]
2410011 b.b.dly.dly[3].___y : 1 [by b.b.dly.dly[3].__y:=0]
2418342 b.b.dly.dly[3].y : 0 [by b.b.dly.dly[3].___y:=1]
2449923 b.b.dly.dly[4]._y : 1 [by b.b.dly.dly[3].y:=0]
2449941 b.b.dly.dly[4].__y : 0 [by b.b.dly.dly[4]._y:=1]
2452135 b.b.dly.dly[4].___y : 1 [by b.b.dly.dly[4].__y:=0]
2490107 b.b.dly.dly[4].y : 0 [by b.b.dly.dly[4].___y:=1]
2490227 b.b.dly.dly[5]._y : 1 [by b.b.dly.dly[4].y:=0]
2496542 b.b.dly.dly[5].__y : 0 [by b.b.dly.dly[5]._y:=1]
2498606 b.b.dly.dly[5].___y : 1 [by b.b.dly.dly[5].__y:=0]
2499198 b.b.dly.dly[5].y : 0 [by b.b.dly.dly[5].___y:=1]
2499205 b.b.dly.dly[6]._y : 1 [by b.b.dly.dly[5].y:=0]
2499206 b.b.dly.dly[6].__y : 0 [by b.b.dly.dly[6]._y:=1]
2499330 b.b.dly.dly[6].___y : 1 [by b.b.dly.dly[6].__y:=0]
2505260 b.b.dly.dly[6].y : 0 [by b.b.dly.dly[6].___y:=1]
2506312 b.b.dly.mu2[2]._y : 1 [by b.b.dly.dly[6].y:=0]
2506672 b.b.dly._a[3] : 0 [by b.b.dly.mu2[2]._y:=1]
2516866 b.b.dly.and2[3]._y : 1 [by b.b.dly._a[3]:=0]
2517963 b.b.dly.dly[7].a : 0 [by b.b.dly.and2[3]._y:=1]
2537855 b.b.dly.dly[7]._y : 1 [by b.b.dly.dly[7].a:=0]
2537859 b.b.dly.dly[7].__y : 0 [by b.b.dly.dly[7]._y:=1]
2549523 b.b.dly.dly[7].___y : 1 [by b.b.dly.dly[7].__y:=0]
2587442 b.b.dly.dly[7].y : 0 [by b.b.dly.dly[7].___y:=1]
2605103 b.b.dly.dly[8]._y : 1 [by b.b.dly.dly[7].y:=0]
2608484 b.b.dly.dly[8].__y : 0 [by b.b.dly.dly[8]._y:=1]
2608740 b.b.dly.dly[8].___y : 1 [by b.b.dly.dly[8].__y:=0]
2623670 b.b.dly.dly[8].y : 0 [by b.b.dly.dly[8].___y:=1]
2623707 b.b.dly.dly[9]._y : 1 [by b.b.dly.dly[8].y:=0]
2623719 b.b.dly.dly[9].__y : 0 [by b.b.dly.dly[9]._y:=1]
2623728 b.b.dly.dly[9].___y : 1 [by b.b.dly.dly[9].__y:=0]
2624155 b.b.dly.dly[9].y : 0 [by b.b.dly.dly[9].___y:=1]
2624397 b.b.dly.dly[10]._y : 1 [by b.b.dly.dly[9].y:=0]
2625232 b.b.dly.dly[10].__y : 0 [by b.b.dly.dly[10]._y:=1]
2671968 b.b.dly.dly[10].___y : 1 [by b.b.dly.dly[10].__y:=0]
2673528 b.b.dly.dly[10].y : 0 [by b.b.dly.dly[10].___y:=1]
2710621 b.b.dly.dly[11]._y : 1 [by b.b.dly.dly[10].y:=0]
2710881 b.b.dly.dly[11].__y : 0 [by b.b.dly.dly[11]._y:=1]
2719869 b.b.dly.dly[11].___y : 1 [by b.b.dly.dly[11].__y:=0]
2719870 b.b.dly.dly[11].y : 0 [by b.b.dly.dly[11].___y:=1]
2755920 b.b.dly.dly[12]._y : 1 [by b.b.dly.dly[11].y:=0]
2756304 b.b.dly.dly[12].__y : 0 [by b.b.dly.dly[12]._y:=1]
2756323 b.b.dly.dly[12].___y : 1 [by b.b.dly.dly[12].__y:=0]
2756332 b.b.dly.dly[12].y : 0 [by b.b.dly.dly[12].___y:=1]
2778286 b.b.dly.dly[13]._y : 1 [by b.b.dly.dly[12].y:=0]
2778474 b.b.dly.dly[13].__y : 0 [by b.b.dly.dly[13]._y:=1]
2824250 b.b.dly.dly[13].___y : 1 [by b.b.dly.dly[13].__y:=0]
2827850 b.b.dly.dly[13].y : 0 [by b.b.dly.dly[13].___y:=1]
2827998 b.b.dly.dly[14]._y : 1 [by b.b.dly.dly[13].y:=0]
2846875 b.b.dly.dly[14].__y : 0 [by b.b.dly.dly[14]._y:=1]
2846890 b.b.dly.dly[14].___y : 1 [by b.b.dly.dly[14].__y:=0]
2857499 b.b.dly.mu2[3].b : 0 [by b.b.dly.dly[14].___y:=1]
2858386 b.b.dly.mu2[3]._y : 1 [by b.b.dly.mu2[3].b:=0]
2866368 b.b._req : 0 [by b.b.dly.mu2[3]._y:=1]
2866369 b.b.req_buf._y : 1 [by b.b._req:=0]
2873095 b.b._reqX : 0 [by b.b.req_buf._y:=1]
2873460 b.b.req_bufarray.buf2._y : 1 [by b.b._reqX:=0]
2882418 b.b._reqXX[0] : 0 [by b.b.req_bufarray.buf2._y:=1]
[] Receiving ack out
2882418 b.out.a : 1
2883802 b.b._out_a_B : 0 [by b.out.a:=1]
2883823 b.b.out_a_B_buf_t.buf2._y : 1 [by b.b._out_a_B:=0]
2883826 b.b._out_a_BX_f[0] : 0 [by b.b.out_a_B_buf_t.buf2._y:=1]
2883828 b.b.f_buf_func[3]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2883829 b.b.f_buf_func[4]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2883829 b.b.f_buf_func[3].y : 0 [by b.b.f_buf_func[3]._y:=1]
2883843 b.b.out_a_B_buf_f.buf2._y : 1 [by b.b._out_a_B:=0]
2884408 b.b.f_buf_func[2]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2885268 b.b.f_buf_func[2].y : 0 [by b.b.f_buf_func[2]._y:=1]
2885703 b.b.f_buf_func[0]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2885704 b.b.f_buf_func[0].y : 0 [by b.b.f_buf_func[0]._y:=1]
2887281 b.b.f_buf_func[4].y : 0 [by b.b.f_buf_func[4]._y:=1]
2890976 b.b._out_a_BX_t[0] : 0 [by b.b.out_a_B_buf_f.buf2._y:=1]
2893335 b.b.f_buf_func[1]._y : 1 [by b.b._out_a_BX_f[0]:=0]
2893410 b.b.f_buf_func[1].y : 0 [by b.b.f_buf_func[1]._y:=1]
2893410 b.out.v : 0
2921361 b.b.inack_ctl._y : 1 [by b.out.v:=0]
2921435 b.in.a : 0 [by b.b.inack_ctl._y:=1]
2923705 b.b._en : 1 [by b.in.a:=0]
2923803 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
2929476 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
2933329 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
2955531 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
[] Set ack out 0
2955531 b.out.a : 0
2961672 b.b._out_a_B : 1 [by b.out.a:=0]
2961676 b.b.out_a_B_buf_f.buf2._y : 0 [by b.b._out_a_B:=1]
2961681 b.b._out_a_BX_t[0] : 1 [by b.b.out_a_B_buf_f.buf2._y:=0]
2964032 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
2964323 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]

731
test/unit_tests/bd2qdi_5/run/test.prs
View File

@@ -1,731 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"b._reset_B"-
~("Reset")->"b._reset_B"+
"b.b.reset_bufarray.buf2.a"->"b.b.reset_bufarray.buf2._y"-
~("b.b.reset_bufarray.buf2.a")->"b.b.reset_bufarray.buf2._y"+
"b.b.reset_bufarray.buf2._y"->"b.b.reset_bufarray.buf2.y"-
~("b.b.reset_bufarray.buf2._y")->"b.b.reset_bufarray.buf2.y"+
= "b.b.reset_bufarray.supply.vdd" "b.b.reset_bufarray.buf2.vdd"
= "b.b.reset_bufarray.supply.vss" "b.b.reset_bufarray.buf2.vss"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[4]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[3]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[2]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[1]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.buf2.y"
= "b.b.reset_bufarray.in" "b.b.reset_bufarray.buf2.a"
~"b.b.inack_ctl.c1"&~"b.b.inack_ctl.c2"&~"b.b.inack_ctl.c3"|~"b.b.inack_ctl.pr_B"->"b.b.inack_ctl._y"+
"b.b.inack_ctl.c1"&"b.b.inack_ctl.c2"&"b.b.inack_ctl.c3"&"b.b.inack_ctl.sr_B"->"b.b.inack_ctl._y"-
"b.b.inack_ctl._y"->"b.b.inack_ctl.y"-
~("b.b.inack_ctl._y")->"b.b.inack_ctl.y"+
"b.b.dly.and2[0].a"&"b.b.dly.and2[0].b"->"b.b.dly.and2[0]._y"-
~("b.b.dly.and2[0].a"&"b.b.dly.and2[0].b")->"b.b.dly.and2[0]._y"+
"b.b.dly.and2[0]._y"->"b.b.dly.and2[0].y"-
~("b.b.dly.and2[0]._y")->"b.b.dly.and2[0].y"+
"b.b.dly.and2[1].a"&"b.b.dly.and2[1].b"->"b.b.dly.and2[1]._y"-
~("b.b.dly.and2[1].a"&"b.b.dly.and2[1].b")->"b.b.dly.and2[1]._y"+
"b.b.dly.and2[1]._y"->"b.b.dly.and2[1].y"-
~("b.b.dly.and2[1]._y")->"b.b.dly.and2[1].y"+
"b.b.dly.and2[2].a"&"b.b.dly.and2[2].b"->"b.b.dly.and2[2]._y"-
~("b.b.dly.and2[2].a"&"b.b.dly.and2[2].b")->"b.b.dly.and2[2]._y"+
"b.b.dly.and2[2]._y"->"b.b.dly.and2[2].y"-
~("b.b.dly.and2[2]._y")->"b.b.dly.and2[2].y"+
"b.b.dly.and2[3].a"&"b.b.dly.and2[3].b"->"b.b.dly.and2[3]._y"-
~("b.b.dly.and2[3].a"&"b.b.dly.and2[3].b")->"b.b.dly.and2[3]._y"+
"b.b.dly.and2[3]._y"->"b.b.dly.and2[3].y"-
~("b.b.dly.and2[3]._y")->"b.b.dly.and2[3].y"+
= "b.b.dly.s[0]" "b.b.dly.mu2[0].s"
= "b.b.dly.s[0]" "b.b.dly.and2[0].b"
= "b.b.dly.s[1]" "b.b.dly.mu2[1].s"
= "b.b.dly.s[1]" "b.b.dly.and2[1].b"
= "b.b.dly.s[2]" "b.b.dly.mu2[2].s"
= "b.b.dly.s[2]" "b.b.dly.and2[2].b"
= "b.b.dly.s[3]" "b.b.dly.mu2[3].s"
= "b.b.dly.s[3]" "b.b.dly.and2[3].b"
= "b.b.dly.supply.vdd" "b.b.dly.dly[14].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[13].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[12].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[11].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[10].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[9].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[8].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[7].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[6].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[5].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[4].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[3].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[2].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[1].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.dly[0].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[3].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[2].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[1].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.mu2[0].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[3].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[2].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[1].vdd"
= "b.b.dly.supply.vdd" "b.b.dly.and2[0].vdd"
= "b.b.dly.supply.vss" "b.b.dly.dly[14].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[13].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[12].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[11].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[10].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[9].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[8].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[7].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[6].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[5].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[4].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[3].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[2].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[1].vss"
= "b.b.dly.supply.vss" "b.b.dly.dly[0].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[3].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[2].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[1].vss"
= "b.b.dly.supply.vss" "b.b.dly.mu2[0].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[3].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[2].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[1].vss"
= "b.b.dly.supply.vss" "b.b.dly.and2[0].vss"
"b.b.dly.mu2[0].s"->"b.b.dly.mu2[0]._s"-
~("b.b.dly.mu2[0].s")->"b.b.dly.mu2[0]._s"+
~"b.b.dly.mu2[0].a"&~"b.b.dly.mu2[0].s"|~"b.b.dly.mu2[0].b"&~"b.b.dly.mu2[0]._s"->"b.b.dly.mu2[0]._y"+
"b.b.dly.mu2[0].a"&"b.b.dly.mu2[0]._s"|"b.b.dly.mu2[0].b"&"b.b.dly.mu2[0].s"->"b.b.dly.mu2[0]._y"-
"b.b.dly.mu2[0]._y"->"b.b.dly.mu2[0].y"-
~("b.b.dly.mu2[0]._y")->"b.b.dly.mu2[0].y"+
"b.b.dly.mu2[1].s"->"b.b.dly.mu2[1]._s"-
~("b.b.dly.mu2[1].s")->"b.b.dly.mu2[1]._s"+
~"b.b.dly.mu2[1].a"&~"b.b.dly.mu2[1].s"|~"b.b.dly.mu2[1].b"&~"b.b.dly.mu2[1]._s"->"b.b.dly.mu2[1]._y"+
"b.b.dly.mu2[1].a"&"b.b.dly.mu2[1]._s"|"b.b.dly.mu2[1].b"&"b.b.dly.mu2[1].s"->"b.b.dly.mu2[1]._y"-
"b.b.dly.mu2[1]._y"->"b.b.dly.mu2[1].y"-
~("b.b.dly.mu2[1]._y")->"b.b.dly.mu2[1].y"+
"b.b.dly.mu2[2].s"->"b.b.dly.mu2[2]._s"-
~("b.b.dly.mu2[2].s")->"b.b.dly.mu2[2]._s"+
~"b.b.dly.mu2[2].a"&~"b.b.dly.mu2[2].s"|~"b.b.dly.mu2[2].b"&~"b.b.dly.mu2[2]._s"->"b.b.dly.mu2[2]._y"+
"b.b.dly.mu2[2].a"&"b.b.dly.mu2[2]._s"|"b.b.dly.mu2[2].b"&"b.b.dly.mu2[2].s"->"b.b.dly.mu2[2]._y"-
"b.b.dly.mu2[2]._y"->"b.b.dly.mu2[2].y"-
~("b.b.dly.mu2[2]._y")->"b.b.dly.mu2[2].y"+
"b.b.dly.mu2[3].s"->"b.b.dly.mu2[3]._s"-
~("b.b.dly.mu2[3].s")->"b.b.dly.mu2[3]._s"+
~"b.b.dly.mu2[3].a"&~"b.b.dly.mu2[3].s"|~"b.b.dly.mu2[3].b"&~"b.b.dly.mu2[3]._s"->"b.b.dly.mu2[3]._y"+
"b.b.dly.mu2[3].a"&"b.b.dly.mu2[3]._s"|"b.b.dly.mu2[3].b"&"b.b.dly.mu2[3].s"->"b.b.dly.mu2[3]._y"-
"b.b.dly.mu2[3]._y"->"b.b.dly.mu2[3].y"-
~("b.b.dly.mu2[3]._y")->"b.b.dly.mu2[3].y"+
"b.b.dly.dly[0].a"->"b.b.dly.dly[0]._y"-
~("b.b.dly.dly[0].a")->"b.b.dly.dly[0]._y"+
"b.b.dly.dly[0]._y"->"b.b.dly.dly[0].__y"-
~("b.b.dly.dly[0]._y")->"b.b.dly.dly[0].__y"+
"b.b.dly.dly[0].__y"->"b.b.dly.dly[0].___y"-
~("b.b.dly.dly[0].__y")->"b.b.dly.dly[0].___y"+
"b.b.dly.dly[0].___y"->"b.b.dly.dly[0].y"-
~("b.b.dly.dly[0].___y")->"b.b.dly.dly[0].y"+
"b.b.dly.dly[1].a"->"b.b.dly.dly[1]._y"-
~("b.b.dly.dly[1].a")->"b.b.dly.dly[1]._y"+
"b.b.dly.dly[1]._y"->"b.b.dly.dly[1].__y"-
~("b.b.dly.dly[1]._y")->"b.b.dly.dly[1].__y"+
"b.b.dly.dly[1].__y"->"b.b.dly.dly[1].___y"-
~("b.b.dly.dly[1].__y")->"b.b.dly.dly[1].___y"+
"b.b.dly.dly[1].___y"->"b.b.dly.dly[1].y"-
~("b.b.dly.dly[1].___y")->"b.b.dly.dly[1].y"+
"b.b.dly.dly[2].a"->"b.b.dly.dly[2]._y"-
~("b.b.dly.dly[2].a")->"b.b.dly.dly[2]._y"+
"b.b.dly.dly[2]._y"->"b.b.dly.dly[2].__y"-
~("b.b.dly.dly[2]._y")->"b.b.dly.dly[2].__y"+
"b.b.dly.dly[2].__y"->"b.b.dly.dly[2].___y"-
~("b.b.dly.dly[2].__y")->"b.b.dly.dly[2].___y"+
"b.b.dly.dly[2].___y"->"b.b.dly.dly[2].y"-
~("b.b.dly.dly[2].___y")->"b.b.dly.dly[2].y"+
"b.b.dly.dly[3].a"->"b.b.dly.dly[3]._y"-
~("b.b.dly.dly[3].a")->"b.b.dly.dly[3]._y"+
"b.b.dly.dly[3]._y"->"b.b.dly.dly[3].__y"-
~("b.b.dly.dly[3]._y")->"b.b.dly.dly[3].__y"+
"b.b.dly.dly[3].__y"->"b.b.dly.dly[3].___y"-
~("b.b.dly.dly[3].__y")->"b.b.dly.dly[3].___y"+
"b.b.dly.dly[3].___y"->"b.b.dly.dly[3].y"-
~("b.b.dly.dly[3].___y")->"b.b.dly.dly[3].y"+
"b.b.dly.dly[4].a"->"b.b.dly.dly[4]._y"-
~("b.b.dly.dly[4].a")->"b.b.dly.dly[4]._y"+
"b.b.dly.dly[4]._y"->"b.b.dly.dly[4].__y"-
~("b.b.dly.dly[4]._y")->"b.b.dly.dly[4].__y"+
"b.b.dly.dly[4].__y"->"b.b.dly.dly[4].___y"-
~("b.b.dly.dly[4].__y")->"b.b.dly.dly[4].___y"+
"b.b.dly.dly[4].___y"->"b.b.dly.dly[4].y"-
~("b.b.dly.dly[4].___y")->"b.b.dly.dly[4].y"+
"b.b.dly.dly[5].a"->"b.b.dly.dly[5]._y"-
~("b.b.dly.dly[5].a")->"b.b.dly.dly[5]._y"+
"b.b.dly.dly[5]._y"->"b.b.dly.dly[5].__y"-
~("b.b.dly.dly[5]._y")->"b.b.dly.dly[5].__y"+
"b.b.dly.dly[5].__y"->"b.b.dly.dly[5].___y"-
~("b.b.dly.dly[5].__y")->"b.b.dly.dly[5].___y"+
"b.b.dly.dly[5].___y"->"b.b.dly.dly[5].y"-
~("b.b.dly.dly[5].___y")->"b.b.dly.dly[5].y"+
"b.b.dly.dly[6].a"->"b.b.dly.dly[6]._y"-
~("b.b.dly.dly[6].a")->"b.b.dly.dly[6]._y"+
"b.b.dly.dly[6]._y"->"b.b.dly.dly[6].__y"-
~("b.b.dly.dly[6]._y")->"b.b.dly.dly[6].__y"+
"b.b.dly.dly[6].__y"->"b.b.dly.dly[6].___y"-
~("b.b.dly.dly[6].__y")->"b.b.dly.dly[6].___y"+
"b.b.dly.dly[6].___y"->"b.b.dly.dly[6].y"-
~("b.b.dly.dly[6].___y")->"b.b.dly.dly[6].y"+
"b.b.dly.dly[7].a"->"b.b.dly.dly[7]._y"-
~("b.b.dly.dly[7].a")->"b.b.dly.dly[7]._y"+
"b.b.dly.dly[7]._y"->"b.b.dly.dly[7].__y"-
~("b.b.dly.dly[7]._y")->"b.b.dly.dly[7].__y"+
"b.b.dly.dly[7].__y"->"b.b.dly.dly[7].___y"-
~("b.b.dly.dly[7].__y")->"b.b.dly.dly[7].___y"+
"b.b.dly.dly[7].___y"->"b.b.dly.dly[7].y"-
~("b.b.dly.dly[7].___y")->"b.b.dly.dly[7].y"+
"b.b.dly.dly[8].a"->"b.b.dly.dly[8]._y"-
~("b.b.dly.dly[8].a")->"b.b.dly.dly[8]._y"+
"b.b.dly.dly[8]._y"->"b.b.dly.dly[8].__y"-
~("b.b.dly.dly[8]._y")->"b.b.dly.dly[8].__y"+
"b.b.dly.dly[8].__y"->"b.b.dly.dly[8].___y"-
~("b.b.dly.dly[8].__y")->"b.b.dly.dly[8].___y"+
"b.b.dly.dly[8].___y"->"b.b.dly.dly[8].y"-
~("b.b.dly.dly[8].___y")->"b.b.dly.dly[8].y"+
"b.b.dly.dly[9].a"->"b.b.dly.dly[9]._y"-
~("b.b.dly.dly[9].a")->"b.b.dly.dly[9]._y"+
"b.b.dly.dly[9]._y"->"b.b.dly.dly[9].__y"-
~("b.b.dly.dly[9]._y")->"b.b.dly.dly[9].__y"+
"b.b.dly.dly[9].__y"->"b.b.dly.dly[9].___y"-
~("b.b.dly.dly[9].__y")->"b.b.dly.dly[9].___y"+
"b.b.dly.dly[9].___y"->"b.b.dly.dly[9].y"-
~("b.b.dly.dly[9].___y")->"b.b.dly.dly[9].y"+
"b.b.dly.dly[10].a"->"b.b.dly.dly[10]._y"-
~("b.b.dly.dly[10].a")->"b.b.dly.dly[10]._y"+
"b.b.dly.dly[10]._y"->"b.b.dly.dly[10].__y"-
~("b.b.dly.dly[10]._y")->"b.b.dly.dly[10].__y"+
"b.b.dly.dly[10].__y"->"b.b.dly.dly[10].___y"-
~("b.b.dly.dly[10].__y")->"b.b.dly.dly[10].___y"+
"b.b.dly.dly[10].___y"->"b.b.dly.dly[10].y"-
~("b.b.dly.dly[10].___y")->"b.b.dly.dly[10].y"+
"b.b.dly.dly[11].a"->"b.b.dly.dly[11]._y"-
~("b.b.dly.dly[11].a")->"b.b.dly.dly[11]._y"+
"b.b.dly.dly[11]._y"->"b.b.dly.dly[11].__y"-
~("b.b.dly.dly[11]._y")->"b.b.dly.dly[11].__y"+
"b.b.dly.dly[11].__y"->"b.b.dly.dly[11].___y"-
~("b.b.dly.dly[11].__y")->"b.b.dly.dly[11].___y"+
"b.b.dly.dly[11].___y"->"b.b.dly.dly[11].y"-
~("b.b.dly.dly[11].___y")->"b.b.dly.dly[11].y"+
"b.b.dly.dly[12].a"->"b.b.dly.dly[12]._y"-
~("b.b.dly.dly[12].a")->"b.b.dly.dly[12]._y"+
"b.b.dly.dly[12]._y"->"b.b.dly.dly[12].__y"-
~("b.b.dly.dly[12]._y")->"b.b.dly.dly[12].__y"+
"b.b.dly.dly[12].__y"->"b.b.dly.dly[12].___y"-
~("b.b.dly.dly[12].__y")->"b.b.dly.dly[12].___y"+
"b.b.dly.dly[12].___y"->"b.b.dly.dly[12].y"-
~("b.b.dly.dly[12].___y")->"b.b.dly.dly[12].y"+
"b.b.dly.dly[13].a"->"b.b.dly.dly[13]._y"-
~("b.b.dly.dly[13].a")->"b.b.dly.dly[13]._y"+
"b.b.dly.dly[13]._y"->"b.b.dly.dly[13].__y"-
~("b.b.dly.dly[13]._y")->"b.b.dly.dly[13].__y"+
"b.b.dly.dly[13].__y"->"b.b.dly.dly[13].___y"-
~("b.b.dly.dly[13].__y")->"b.b.dly.dly[13].___y"+
"b.b.dly.dly[13].___y"->"b.b.dly.dly[13].y"-
~("b.b.dly.dly[13].___y")->"b.b.dly.dly[13].y"+
"b.b.dly.dly[14].a"->"b.b.dly.dly[14]._y"-
~("b.b.dly.dly[14].a")->"b.b.dly.dly[14]._y"+
"b.b.dly.dly[14]._y"->"b.b.dly.dly[14].__y"-
~("b.b.dly.dly[14]._y")->"b.b.dly.dly[14].__y"+
"b.b.dly.dly[14].__y"->"b.b.dly.dly[14].___y"-
~("b.b.dly.dly[14].__y")->"b.b.dly.dly[14].___y"+
"b.b.dly.dly[14].___y"->"b.b.dly.dly[14].y"-
~("b.b.dly.dly[14].___y")->"b.b.dly.dly[14].y"+
= "b.b.dly.dly[14].y" "b.b.dly.mu2[3].b"
= "b.b.dly.dly[14].a" "b.b.dly.dly[13].y"
= "b.b.dly.dly[13].a" "b.b.dly.dly[12].y"
= "b.b.dly.dly[12].a" "b.b.dly.dly[11].y"
= "b.b.dly.dly[11].a" "b.b.dly.dly[10].y"
= "b.b.dly.dly[10].a" "b.b.dly.dly[9].y"
= "b.b.dly.dly[9].a" "b.b.dly.dly[8].y"
= "b.b.dly.dly[8].a" "b.b.dly.dly[7].y"
= "b.b.dly.dly[7].a" "b.b.dly.and2[3].y"
= "b.b.dly.dly[6].y" "b.b.dly.mu2[2].b"
= "b.b.dly.dly[6].a" "b.b.dly.dly[5].y"
= "b.b.dly.dly[5].a" "b.b.dly.dly[4].y"
= "b.b.dly.dly[4].a" "b.b.dly.dly[3].y"
= "b.b.dly.dly[3].a" "b.b.dly.and2[2].y"
= "b.b.dly.dly[2].y" "b.b.dly.mu2[1].b"
= "b.b.dly.dly[2].a" "b.b.dly.dly[1].y"
= "b.b.dly.dly[1].a" "b.b.dly.and2[1].y"
= "b.b.dly.dly[0].y" "b.b.dly.mu2[0].b"
= "b.b.dly.dly[0].a" "b.b.dly.and2[0].y"
= "b.b.dly._a[1]" "b.b.dly.mu2[1].a"
= "b.b.dly._a[1]" "b.b.dly.and2[1].a"
= "b.b.dly._a[1]" "b.b.dly.mu2[0].y"
= "b.b.dly._a[2]" "b.b.dly.mu2[2].a"
= "b.b.dly._a[2]" "b.b.dly.and2[2].a"
= "b.b.dly._a[2]" "b.b.dly.mu2[1].y"
= "b.b.dly._a[3]" "b.b.dly.mu2[3].a"
= "b.b.dly._a[3]" "b.b.dly.and2[3].a"
= "b.b.dly._a[3]" "b.b.dly.mu2[2].y"
= "b.b.dly.out" "b.b.dly.mu2[3].y"
= "b.b.dly.out" "b.b.dly._a[4]"
= "b.b.dly.in" "b.b.dly.mu2[0].a"
= "b.b.dly.in" "b.b.dly.and2[0].a"
= "b.b.dly.in" "b.b.dly._a[0]"
= "b.b._out_a_BX_f[0]" "b.b.out_a_B_buf_t.out[0]"
= "b.b._out_a_BX_f[1]" "b.b.out_a_B_buf_t.out[1]"
= "b.b._out_a_BX_f[2]" "b.b.out_a_B_buf_t.out[2]"
= "b.b._out_a_BX_f[3]" "b.b.out_a_B_buf_t.out[3]"
= "b.b._out_a_BX_f[4]" "b.b.out_a_B_buf_t.out[4]"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[4].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[3].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[2].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[1].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[0].c2"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[4]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[3]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[2]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[1]"
"b.b.out_a_inv.a"->"b.b.out_a_inv.y"-
~("b.b.out_a_inv.a")->"b.b.out_a_inv.y"+
= "b.b._en" "b.b.en_buf_f.in"
= "b.b._en" "b.b.en_buf_t.in"
= "b.b._en" "b.b.en_ctl.y"
= "b.b._en" "b.b.inack_ctl.c1"
timing("b.b.in.a"-,"b.b.in.d[0]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[1]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[2]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[3]","b.b.in.r"+)
timing("b.b.in.a"-,"b.b.in.d[4]","b.b.in.r"+)
= "b.b.in.r" "b.b.dly.in"
= "b.b.in.a" "b.b.en_ctl.c1"
= "b.b.in.a" "b.b.inack_ctl.y"
= "b.b.in.d[0]" "b.b.t_buf_func[0].n1"
= "b.b.in.d[0]" "b.b.input_invs[0].a"
= "b.b.in.d[1]" "b.b.t_buf_func[1].n1"
= "b.b.in.d[1]" "b.b.input_invs[1].a"
= "b.b.in.d[2]" "b.b.t_buf_func[2].n1"
= "b.b.in.d[2]" "b.b.input_invs[2].a"
= "b.b.in.d[3]" "b.b.t_buf_func[3].n1"
= "b.b.in.d[3]" "b.b.input_invs[3].a"
= "b.b.in.d[4]" "b.b.t_buf_func[4].n1"
= "b.b.in.d[4]" "b.b.input_invs[4].a"
= "b.b._inB[0]" "b.b.f_buf_func[0].n1"
= "b.b._inB[0]" "b.b.input_invs[0].y"
= "b.b._inB[1]" "b.b.f_buf_func[1].n1"
= "b.b._inB[1]" "b.b.input_invs[1].y"
= "b.b._inB[2]" "b.b.f_buf_func[2].n1"
= "b.b._inB[2]" "b.b.input_invs[2].y"
= "b.b._inB[3]" "b.b.f_buf_func[3].n1"
= "b.b._inB[3]" "b.b.input_invs[3].y"
= "b.b._inB[4]" "b.b.f_buf_func[4].n1"
= "b.b._inB[4]" "b.b.input_invs[4].y"
"b.b.reset_buf.a"->"b.b.reset_buf._y"-
~("b.b.reset_buf.a")->"b.b.reset_buf._y"+
"b.b.reset_buf._y"->"b.b.reset_buf.y"-
~("b.b.reset_buf._y")->"b.b.reset_buf.y"+
= "b.b._reset_BX" "b.b.inack_ctl.sr_B"
= "b.b._reset_BX" "b.b.inack_ctl.pr_B"
= "b.b._reset_BX" "b.b.reset_bufarray.in"
= "b.b._reset_BX" "b.b.reset_buf.y"
= "b.b.reset_B" "b.b.reset_buf.a"
= "b.b._out_a_BX_t[0]" "b.b.out_a_B_buf_f.out[0]"
= "b.b._out_a_BX_t[1]" "b.b.out_a_B_buf_f.out[1]"
= "b.b._out_a_BX_t[2]" "b.b.out_a_B_buf_f.out[2]"
= "b.b._out_a_BX_t[3]" "b.b.out_a_B_buf_f.out[3]"
= "b.b._out_a_BX_t[4]" "b.b.out_a_B_buf_f.out[4]"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[4].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[3].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[2].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[1].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[0].c2"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[4]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[3]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[2]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[1]"
= "b.b._reset_BXX[0]" "b.b.reset_bufarray.out[0]"
= "b.b._reset_BXX[1]" "b.b.reset_bufarray.out[1]"
= "b.b._reset_BXX[2]" "b.b.reset_bufarray.out[2]"
= "b.b._reset_BXX[3]" "b.b.reset_bufarray.out[3]"
= "b.b._reset_BXX[4]" "b.b.reset_bufarray.out[4]"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[4]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[3]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[2]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[1]"
"b.b.en_buf_f.buf2.a"->"b.b.en_buf_f.buf2._y"-
~("b.b.en_buf_f.buf2.a")->"b.b.en_buf_f.buf2._y"+
"b.b.en_buf_f.buf2._y"->"b.b.en_buf_f.buf2.y"-
~("b.b.en_buf_f.buf2._y")->"b.b.en_buf_f.buf2.y"+
= "b.b.en_buf_f.supply.vdd" "b.b.en_buf_f.buf2.vdd"
= "b.b.en_buf_f.supply.vss" "b.b.en_buf_f.buf2.vss"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[4]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[3]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[2]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[1]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.buf2.y"
= "b.b.en_buf_f.in" "b.b.en_buf_f.buf2.a"
"b.b.input_invs[0].a"->"b.b.input_invs[0].y"-
~("b.b.input_invs[0].a")->"b.b.input_invs[0].y"+
"b.b.input_invs[1].a"->"b.b.input_invs[1].y"-
~("b.b.input_invs[1].a")->"b.b.input_invs[1].y"+
"b.b.input_invs[2].a"->"b.b.input_invs[2].y"-
~("b.b.input_invs[2].a")->"b.b.input_invs[2].y"+
"b.b.input_invs[3].a"->"b.b.input_invs[3].y"-
~("b.b.input_invs[3].a")->"b.b.input_invs[3].y"+
"b.b.input_invs[4].a"->"b.b.input_invs[4].y"-
~("b.b.input_invs[4].a")->"b.b.input_invs[4].y"+
"b.b.out_a_B_buf_t.buf2.a"->"b.b.out_a_B_buf_t.buf2._y"-
~("b.b.out_a_B_buf_t.buf2.a")->"b.b.out_a_B_buf_t.buf2._y"+
"b.b.out_a_B_buf_t.buf2._y"->"b.b.out_a_B_buf_t.buf2.y"-
~("b.b.out_a_B_buf_t.buf2._y")->"b.b.out_a_B_buf_t.buf2.y"+
= "b.b.out_a_B_buf_t.supply.vdd" "b.b.out_a_B_buf_t.buf2.vdd"
= "b.b.out_a_B_buf_t.supply.vss" "b.b.out_a_B_buf_t.buf2.vss"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[4]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[3]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[2]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[1]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.buf2.y"
= "b.b.out_a_B_buf_t.in" "b.b.out_a_B_buf_t.buf2.a"
= "b.b._en_X_f[0]" "b.b.en_buf_f.out[0]"
= "b.b._en_X_f[1]" "b.b.en_buf_f.out[1]"
= "b.b._en_X_f[2]" "b.b.en_buf_f.out[2]"
= "b.b._en_X_f[3]" "b.b.en_buf_f.out[3]"
= "b.b._en_X_f[4]" "b.b.en_buf_f.out[4]"
= "b.b._en_X_f[0]" "b.b.f_buf_func[4].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[3].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[2].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[1].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[0].c1"
= "b.b._en_X_f[0]" "b.b._en_X_f[4]"
= "b.b._en_X_f[0]" "b.b._en_X_f[3]"
= "b.b._en_X_f[0]" "b.b._en_X_f[2]"
= "b.b._en_X_f[0]" "b.b._en_X_f[1]"
= "b.b.dly_cfg[0]" "b.b.dly.s[0]"
= "b.b.dly_cfg[1]" "b.b.dly.s[1]"
= "b.b.dly_cfg[2]" "b.b.dly.s[2]"
= "b.b.dly_cfg[3]" "b.b.dly.s[3]"
= "b.b.supply.vss" "b.b.out_a_B_buf_t.supply.vss"
= "b.b.supply.vdd" "b.b.out_a_B_buf_t.supply.vdd"
= "b.b.supply.vss" "b.b.out_a_B_buf_f.supply.vss"
= "b.b.supply.vdd" "b.b.out_a_B_buf_f.supply.vdd"
= "b.b.supply.vss" "b.b.en_buf_f.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_f.supply.vdd"
= "b.b.supply.vss" "b.b.en_buf_t.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_t.supply.vdd"
= "b.b.supply.vss" "b.b.req_bufarray.supply.vss"
= "b.b.supply.vdd" "b.b.req_bufarray.supply.vdd"
= "b.b.supply.vss" "b.b.reset_bufarray.supply.vss"
= "b.b.supply.vdd" "b.b.reset_bufarray.supply.vdd"
= "b.b.supply.vss" "b.b.dly.supply.vss"
= "b.b.supply.vdd" "b.b.dly.supply.vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.out_a_inv.vdd"
= "b.b.supply.vdd" "b.b.en_ctl.vdd"
= "b.b.supply.vdd" "b.b.inack_ctl.vdd"
= "b.b.supply.vdd" "b.b.input_invs[4].vdd"
= "b.b.supply.vdd" "b.b.input_invs[3].vdd"
= "b.b.supply.vdd" "b.b.input_invs[2].vdd"
= "b.b.supply.vdd" "b.b.input_invs[1].vdd"
= "b.b.supply.vdd" "b.b.input_invs[0].vdd"
= "b.b.supply.vdd" "b.b.req_buf.vdd"
= "b.b.supply.vdd" "b.b.reset_buf.vdd"
= "b.b.supply.vss" "b.b.t_buf_func[4].vss"
= "b.b.supply.vss" "b.b.f_buf_func[4].vss"
= "b.b.supply.vss" "b.b.t_buf_func[3].vss"
= "b.b.supply.vss" "b.b.f_buf_func[3].vss"
= "b.b.supply.vss" "b.b.t_buf_func[2].vss"
= "b.b.supply.vss" "b.b.f_buf_func[2].vss"
= "b.b.supply.vss" "b.b.t_buf_func[1].vss"
= "b.b.supply.vss" "b.b.f_buf_func[1].vss"
= "b.b.supply.vss" "b.b.t_buf_func[0].vss"
= "b.b.supply.vss" "b.b.f_buf_func[0].vss"
= "b.b.supply.vss" "b.b.out_a_inv.vss"
= "b.b.supply.vss" "b.b.en_ctl.vss"
= "b.b.supply.vss" "b.b.inack_ctl.vss"
= "b.b.supply.vss" "b.b.input_invs[4].vss"
= "b.b.supply.vss" "b.b.input_invs[3].vss"
= "b.b.supply.vss" "b.b.input_invs[2].vss"
= "b.b.supply.vss" "b.b.input_invs[1].vss"
= "b.b.supply.vss" "b.b.input_invs[0].vss"
= "b.b.supply.vss" "b.b.req_buf.vss"
= "b.b.supply.vss" "b.b.reset_buf.vss"
~"b.b.en_ctl.p1"&~"b.b.en_ctl.c1"->"b.b.en_ctl.y"+
"b.b.en_ctl.c1"->"b.b.en_ctl.y"-
"b.b.out_a_B_buf_f.buf2.a"->"b.b.out_a_B_buf_f.buf2._y"-
~("b.b.out_a_B_buf_f.buf2.a")->"b.b.out_a_B_buf_f.buf2._y"+
"b.b.out_a_B_buf_f.buf2._y"->"b.b.out_a_B_buf_f.buf2.y"-
~("b.b.out_a_B_buf_f.buf2._y")->"b.b.out_a_B_buf_f.buf2.y"+
= "b.b.out_a_B_buf_f.supply.vdd" "b.b.out_a_B_buf_f.buf2.vdd"
= "b.b.out_a_B_buf_f.supply.vss" "b.b.out_a_B_buf_f.buf2.vss"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[4]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[3]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[2]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[1]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.buf2.y"
= "b.b.out_a_B_buf_f.in" "b.b.out_a_B_buf_f.buf2.a"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.a" "b.b.out_a_inv.a"
= "b.b.out.v" "b.b.en_ctl.p1"
= "b.b.out.v" "b.b.inack_ctl.c3"
= "b.b.out.d.d[4].d[0]" "b.b.f_buf_func[4].y"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.t_buf_func[4].y"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.f_buf_func[3].y"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.t_buf_func[3].y"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.f_buf_func[2].y"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.t_buf_func[2].y"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.f_buf_func[1].y"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.t_buf_func[1].y"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.f_buf_func[0].y"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.t_buf_func[0].y"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b._reqXX[0]" "b.b.req_bufarray.out[0]"
= "b.b._reqXX[1]" "b.b.req_bufarray.out[1]"
= "b.b._reqXX[2]" "b.b.req_bufarray.out[2]"
= "b.b._reqXX[3]" "b.b.req_bufarray.out[3]"
= "b.b._reqXX[4]" "b.b.req_bufarray.out[4]"
= "b.b._reqXX[0]" "b.b.t_buf_func[4].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[4].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[3].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[3].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[2].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[2].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[1].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[1].n2"
= "b.b._reqXX[0]" "b.b.t_buf_func[0].n2"
= "b.b._reqXX[0]" "b.b.f_buf_func[0].n2"
= "b.b._reqXX[0]" "b.b._reqXX[4]"
= "b.b._reqXX[0]" "b.b._reqXX[3]"
= "b.b._reqXX[0]" "b.b._reqXX[2]"
= "b.b._reqXX[0]" "b.b._reqXX[1]"
= "b.b._req" "b.b.req_buf.a"
= "b.b._req" "b.b.dly.out"
"b.b.req_bufarray.buf2.a"->"b.b.req_bufarray.buf2._y"-
~("b.b.req_bufarray.buf2.a")->"b.b.req_bufarray.buf2._y"+
"b.b.req_bufarray.buf2._y"->"b.b.req_bufarray.buf2.y"-
~("b.b.req_bufarray.buf2._y")->"b.b.req_bufarray.buf2.y"+
= "b.b.req_bufarray.supply.vdd" "b.b.req_bufarray.buf2.vdd"
= "b.b.req_bufarray.supply.vss" "b.b.req_bufarray.buf2.vss"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[4]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[3]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[2]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.out[1]"
= "b.b.req_bufarray.out[0]" "b.b.req_bufarray.buf2.y"
= "b.b.req_bufarray.in" "b.b.req_bufarray.buf2.a"
= "b.b._reqX" "b.b.inack_ctl.c2"
= "b.b._reqX" "b.b.req_bufarray.in"
= "b.b._reqX" "b.b.req_buf.y"
= "b.b._out_a_B" "b.b.out_a_B_buf_t.in"
= "b.b._out_a_B" "b.b.out_a_B_buf_f.in"
= "b.b._out_a_B" "b.b.out_a_inv.y"
"b.b.en_buf_t.buf2.a"->"b.b.en_buf_t.buf2._y"-
~("b.b.en_buf_t.buf2.a")->"b.b.en_buf_t.buf2._y"+
"b.b.en_buf_t.buf2._y"->"b.b.en_buf_t.buf2.y"-
~("b.b.en_buf_t.buf2._y")->"b.b.en_buf_t.buf2.y"+
= "b.b.en_buf_t.supply.vdd" "b.b.en_buf_t.buf2.vdd"
= "b.b.en_buf_t.supply.vss" "b.b.en_buf_t.buf2.vss"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[4]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[3]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[2]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[1]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.buf2.y"
= "b.b.en_buf_t.in" "b.b.en_buf_t.buf2.a"
"b.b.req_buf.a"->"b.b.req_buf._y"-
~("b.b.req_buf.a")->"b.b.req_buf._y"+
"b.b.req_buf._y"->"b.b.req_buf.y"-
~("b.b.req_buf._y")->"b.b.req_buf.y"+
= "b.b._en_X_t[0]" "b.b.en_buf_t.out[0]"
= "b.b._en_X_t[1]" "b.b.en_buf_t.out[1]"
= "b.b._en_X_t[2]" "b.b.en_buf_t.out[2]"
= "b.b._en_X_t[3]" "b.b.en_buf_t.out[3]"
= "b.b._en_X_t[4]" "b.b.en_buf_t.out[4]"
= "b.b._en_X_t[0]" "b.b.t_buf_func[4].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[3].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[2].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[1].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[0].c1"
= "b.b._en_X_t[0]" "b.b._en_X_t[4]"
= "b.b._en_X_t[0]" "b.b._en_X_t[3]"
= "b.b._en_X_t[0]" "b.b._en_X_t[2]"
= "b.b._en_X_t[0]" "b.b._en_X_t[1]"
~"b.b.f_buf_func[0].c1"&~"b.b.f_buf_func[0].c2"|~"b.b.f_buf_func[0].pr_B"->"b.b.f_buf_func[0]._y"+
"b.b.f_buf_func[0].c1"&"b.b.f_buf_func[0].c2"&"b.b.f_buf_func[0].n1"&"b.b.f_buf_func[0].n2"&"b.b.f_buf_func[0].sr_B"->"b.b.f_buf_func[0]._y"-
"b.b.f_buf_func[0]._y"->"b.b.f_buf_func[0].y"-
~("b.b.f_buf_func[0]._y")->"b.b.f_buf_func[0].y"+
~"b.b.f_buf_func[1].c1"&~"b.b.f_buf_func[1].c2"|~"b.b.f_buf_func[1].pr_B"->"b.b.f_buf_func[1]._y"+
"b.b.f_buf_func[1].c1"&"b.b.f_buf_func[1].c2"&"b.b.f_buf_func[1].n1"&"b.b.f_buf_func[1].n2"&"b.b.f_buf_func[1].sr_B"->"b.b.f_buf_func[1]._y"-
"b.b.f_buf_func[1]._y"->"b.b.f_buf_func[1].y"-
~("b.b.f_buf_func[1]._y")->"b.b.f_buf_func[1].y"+
~"b.b.f_buf_func[2].c1"&~"b.b.f_buf_func[2].c2"|~"b.b.f_buf_func[2].pr_B"->"b.b.f_buf_func[2]._y"+
"b.b.f_buf_func[2].c1"&"b.b.f_buf_func[2].c2"&"b.b.f_buf_func[2].n1"&"b.b.f_buf_func[2].n2"&"b.b.f_buf_func[2].sr_B"->"b.b.f_buf_func[2]._y"-
"b.b.f_buf_func[2]._y"->"b.b.f_buf_func[2].y"-
~("b.b.f_buf_func[2]._y")->"b.b.f_buf_func[2].y"+
~"b.b.f_buf_func[3].c1"&~"b.b.f_buf_func[3].c2"|~"b.b.f_buf_func[3].pr_B"->"b.b.f_buf_func[3]._y"+
"b.b.f_buf_func[3].c1"&"b.b.f_buf_func[3].c2"&"b.b.f_buf_func[3].n1"&"b.b.f_buf_func[3].n2"&"b.b.f_buf_func[3].sr_B"->"b.b.f_buf_func[3]._y"-
"b.b.f_buf_func[3]._y"->"b.b.f_buf_func[3].y"-
~("b.b.f_buf_func[3]._y")->"b.b.f_buf_func[3].y"+
~"b.b.f_buf_func[4].c1"&~"b.b.f_buf_func[4].c2"|~"b.b.f_buf_func[4].pr_B"->"b.b.f_buf_func[4]._y"+
"b.b.f_buf_func[4].c1"&"b.b.f_buf_func[4].c2"&"b.b.f_buf_func[4].n1"&"b.b.f_buf_func[4].n2"&"b.b.f_buf_func[4].sr_B"->"b.b.f_buf_func[4]._y"-
"b.b.f_buf_func[4]._y"->"b.b.f_buf_func[4].y"-
~("b.b.f_buf_func[4]._y")->"b.b.f_buf_func[4].y"+
~"b.b.t_buf_func[0].c1"&~"b.b.t_buf_func[0].c2"|~"b.b.t_buf_func[0].pr_B"->"b.b.t_buf_func[0]._y"+
"b.b.t_buf_func[0].c1"&"b.b.t_buf_func[0].c2"&"b.b.t_buf_func[0].n1"&"b.b.t_buf_func[0].n2"&"b.b.t_buf_func[0].sr_B"->"b.b.t_buf_func[0]._y"-
"b.b.t_buf_func[0]._y"->"b.b.t_buf_func[0].y"-
~("b.b.t_buf_func[0]._y")->"b.b.t_buf_func[0].y"+
~"b.b.t_buf_func[1].c1"&~"b.b.t_buf_func[1].c2"|~"b.b.t_buf_func[1].pr_B"->"b.b.t_buf_func[1]._y"+
"b.b.t_buf_func[1].c1"&"b.b.t_buf_func[1].c2"&"b.b.t_buf_func[1].n1"&"b.b.t_buf_func[1].n2"&"b.b.t_buf_func[1].sr_B"->"b.b.t_buf_func[1]._y"-
"b.b.t_buf_func[1]._y"->"b.b.t_buf_func[1].y"-
~("b.b.t_buf_func[1]._y")->"b.b.t_buf_func[1].y"+
~"b.b.t_buf_func[2].c1"&~"b.b.t_buf_func[2].c2"|~"b.b.t_buf_func[2].pr_B"->"b.b.t_buf_func[2]._y"+
"b.b.t_buf_func[2].c1"&"b.b.t_buf_func[2].c2"&"b.b.t_buf_func[2].n1"&"b.b.t_buf_func[2].n2"&"b.b.t_buf_func[2].sr_B"->"b.b.t_buf_func[2]._y"-
"b.b.t_buf_func[2]._y"->"b.b.t_buf_func[2].y"-
~("b.b.t_buf_func[2]._y")->"b.b.t_buf_func[2].y"+
~"b.b.t_buf_func[3].c1"&~"b.b.t_buf_func[3].c2"|~"b.b.t_buf_func[3].pr_B"->"b.b.t_buf_func[3]._y"+
"b.b.t_buf_func[3].c1"&"b.b.t_buf_func[3].c2"&"b.b.t_buf_func[3].n1"&"b.b.t_buf_func[3].n2"&"b.b.t_buf_func[3].sr_B"->"b.b.t_buf_func[3]._y"-
"b.b.t_buf_func[3]._y"->"b.b.t_buf_func[3].y"-
~("b.b.t_buf_func[3]._y")->"b.b.t_buf_func[3].y"+
~"b.b.t_buf_func[4].c1"&~"b.b.t_buf_func[4].c2"|~"b.b.t_buf_func[4].pr_B"->"b.b.t_buf_func[4]._y"+
"b.b.t_buf_func[4].c1"&"b.b.t_buf_func[4].c2"&"b.b.t_buf_func[4].n1"&"b.b.t_buf_func[4].n2"&"b.b.t_buf_func[4].sr_B"->"b.b.t_buf_func[4]._y"-
"b.b.t_buf_func[4]._y"->"b.b.t_buf_func[4].y"-
~("b.b.t_buf_func[4]._y")->"b.b.t_buf_func[4].y"+
= "Vdd" "b.b.supply.vdd"
= "GND" "b.b.supply.vss"
= "b._reset_B" "b.b.reset_B"
= "b.dly_cfg[0]" "b.b.dly_cfg[0]"
= "b.dly_cfg[1]" "b.b.dly_cfg[1]"
= "b.dly_cfg[2]" "b.b.dly_cfg[2]"
= "b.dly_cfg[3]" "b.b.dly_cfg[3]"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.v" "b.b.out.v"
= "b.out.a" "b.b.out.a"
= "b.out.d.d[0].f" "b.b.out.d.d[0].f"
= "b.out.d.d[0].t" "b.b.out.d.d[0].t"
= "b.out.d.d[0].d[0]" "b.b.out.d.d[0].d[0]"
= "b.out.d.d[0].d[1]" "b.b.out.d.d[0].d[1]"
= "b.out.d.d[1].f" "b.b.out.d.d[1].f"
= "b.out.d.d[1].t" "b.b.out.d.d[1].t"
= "b.out.d.d[1].d[0]" "b.b.out.d.d[1].d[0]"
= "b.out.d.d[1].d[1]" "b.b.out.d.d[1].d[1]"
= "b.out.d.d[2].f" "b.b.out.d.d[2].f"
= "b.out.d.d[2].t" "b.b.out.d.d[2].t"
= "b.out.d.d[2].d[0]" "b.b.out.d.d[2].d[0]"
= "b.out.d.d[2].d[1]" "b.b.out.d.d[2].d[1]"
= "b.out.d.d[3].f" "b.b.out.d.d[3].f"
= "b.out.d.d[3].t" "b.b.out.d.d[3].t"
= "b.out.d.d[3].d[0]" "b.b.out.d.d[3].d[0]"
= "b.out.d.d[3].d[1]" "b.b.out.d.d[3].d[1]"
= "b.out.d.d[4].f" "b.b.out.d.d[4].f"
= "b.out.d.d[4].t" "b.b.out.d.d[4].t"
= "b.out.d.d[4].d[0]" "b.b.out.d.d[4].d[0]"
= "b.out.d.d[4].d[1]" "b.b.out.d.d[4].d[1]"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
timing("b.in.a"-,"b.in.d[0]","b.in.r"+)
timing("b.in.a"-,"b.in.d[1]","b.in.r"+)
timing("b.in.a"-,"b.in.d[2]","b.in.r"+)
timing("b.in.a"-,"b.in.d[3]","b.in.r"+)
timing("b.in.a"-,"b.in.d[4]","b.in.r"+)
= "b.in.a" "b.b.in.a"
= "b.in.r" "b.b.in.r"
= "b.in.d[0]" "b.b.in.d[0]"
= "b.in.d[1]" "b.b.in.d[1]"
= "b.in.d[2]" "b.b.in.d[2]"
= "b.in.d[3]" "b.b.in.d[3]"
= "b.in.d[4]" "b.b.in.d[4]"

45
test/unit_tests/bd2qdi_5/test.act
View File

@@ -1,45 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/interfaces.act";
import globals;
open tmpl::dataflow_neuro;
defproc bd2qdi_5(bd<5> in; avMx1of2<5> out; bool? dly_cfg[4])
{
bool _reset_B;
prs {
Reset => _reset_B-
}
bd2qdi<5,4> b(.in = in, .out = out, .reset_B = _reset_B, .dly_cfg = dly_cfg);
b.supply.vdd = Vdd;
b.supply.vss = GND;
}
bd2qdi_5 b;

137
test/unit_tests/bd2qdi_5/test.prsim
View File

@@ -1,137 +0,0 @@
watchall
set b.out.a 0
set b.out.v 0
set b.in.r 0
set b.dly_cfg[0] 1
set b.dly_cfg[1] 1
set b.dly_cfg[2] 1
set b.dly_cfg[3] 1
set b.in.d[0] 1
set b.in.d[1] 0
set b.in.d[2] 0
set b.in.d[3] 1
set b.in.d[4] 0
set Reset 0
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
status X
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0
system "echo '[] Reset finished, setting data'"
set b.in.d[0] 0
set b.in.d[1] 1
set b.in.d[2] 1
set b.in.d[3] 0
set b.in.d[4] 1
cycle
system "echo '[] Reset finished, setting req 1'"
set b.in.r 1
cycle
assert-qdi-channel-valid "b.out" 5 22
system "echo '[] Receiving val out'"
set b.out.v 1
# set b.out.a 1
cycle
assert-qdi-channel-valid "b.out" 5 22
assert b.in.a 1
system "echo '[] Changing some input data'"
set b.in.d[0] 1
set b.in.d[1] 1
set b.in.d[2] 1
cycle
system "echo '[] Removing req'"
set b.in.r 0
system "echo '[] Changing more data'"
set b.in.d[3] 0
set b.in.d[4] 0
cycle
assert-qdi-channel-valid "b.out" 5 22
system "echo '[] Receiving ack out'"
set b.out.a 1
cycle
assert-qdi-channel-neutral "b.out" 5
set b.out.v 0
cycle
assert b.in.a 0
system "echo '[] Set ack out 0'"
set b.out.a 0
cycle
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0
system "echo '[] Again!!! setting data'"
set b.in.d[0] 0
set b.in.d[1] 0
set b.in.d[2] 0
set b.in.d[3] 0
set b.in.d[4] 0
cycle
system "echo '[] Again!!! setting req 1'"
set b.in.r 1
cycle
assert-qdi-channel-valid "b.out" 5 0
system "echo '[] Receiving val out'"
set b.out.v 1
# set b.out.a 1
cycle
assert-qdi-channel-valid "b.out" 5 0
assert b.in.a 1
system "echo '[] Changing some input data'"
set b.in.d[0] 1
set b.in.d[1] 1
set b.in.d[2] 1
cycle
system "echo '[] Removing req'"
set b.in.r 0
system "echo '[] Changing more data'"
set b.in.d[3] 0
set b.in.d[4] 0
cycle
assert-qdi-channel-valid "b.out" 5 0
system "echo '[] Receiving ack out'"
set b.out.a 1
cycle
assert-qdi-channel-neutral "b.out" 5
set b.out.v 0
cycle
assert b.in.a 0
system "echo '[] Set ack out 0'"
set b.out.a 0
cycle
assert-qdi-channel-neutral "b.out" 5
assert b.in.a 0

685
test/unit_tests/buf_15.v
View File

@@ -1,685 +0,0 @@
//
// Verilog module for: BUF_X6<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
input in;
output \out[0] ;
// -- signals ---
wire in;
reg \out[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6 (.y(\out[0] ), .a(in));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
output y;
input c1;
input c2;
input c3;
input pr_B;
input sr_B;
// -- signals ---
wire sr_B;
wire pr_B;
wire c3;
wire c1;
reg _y;
reg y;
wire c2;
// --- instances
endmodule
//
// Verilog module for: BUF_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
output y;
input a;
// -- signals ---
reg _y;
wire a;
reg y;
// --- instances
endmodule
//
// Verilog module for: INV_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_2C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
output y;
input c1;
input c2;
// -- signals ---
reg y;
reg _y;
wire c2;
wire c1;
// --- instances
endmodule
//
// Verilog module for: A_3C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
output y;
input c1;
input c2;
input c3;
// -- signals ---
reg _y;
reg y;
wire c3;
wire c1;
wire c2;
// --- instances
endmodule
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[4] ;
wire \in[11] ;
wire \in[12] ;
reg \tmp[21] ;
wire \in[3] ;
reg out;
reg \tmp[23] ;
wire \in[6] ;
wire \in[0] ;
reg \tmp[18] ;
wire \in[10] ;
reg \tmp[15] ;
reg \tmp[16] ;
wire \in[13] ;
wire \in[1] ;
wire \in[9] ;
wire \in[2] ;
wire \in[5] ;
reg \tmp[24] ;
wire \in[14] ;
reg \tmp[19] ;
wire \in[7] ;
reg \tmp[22] ;
reg \tmp[20] ;
wire \in[8] ;
reg \tmp[17] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
endmodule
//
// Verilog module for: OR2_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
output y;
input a;
input b;
// -- signals ---
reg y;
wire a;
reg _y;
wire b;
// --- instances
endmodule
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
reg \ct.in[14] ;
reg \ct.in[13] ;
wire \in.d[7].d[0] ;
wire \in.d[1].d[0] ;
wire \in.d[0].d[0] ;
reg \ct.in[4] ;
reg out;
wire \in.d[10].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[3] ;
wire \in.d[9].d[1] ;
wire \in.d[1].d[1] ;
wire \in.d[2].d[0] ;
wire \in.d[10].d[1] ;
reg \ct.in[8] ;
wire \in.d[12].d[0] ;
wire \in.d[5].d[0] ;
wire \in.d[4].d[0] ;
reg \ct.in[10] ;
reg \ct.in[0] ;
wire \in.d[11].d[0] ;
wire \in.d[7].d[1] ;
wire \in.d[3].d[1] ;
reg \ct.in[11] ;
reg \ct.in[2] ;
reg \ct.in[9] ;
wire \in.d[13].d[0] ;
wire \in.d[14].d[1] ;
wire \in.d[11].d[1] ;
wire \in.d[13].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[1] ;
wire \in.d[14].d[0] ;
wire \in.d[12].d[1] ;
wire \in.d[9].d[0] ;
wire \in.d[2].d[1] ;
reg \ct.in[5] ;
wire \in.d[5].d[1] ;
reg \ct.in[12] ;
reg \ct.in[6] ;
wire \in.d[3].d[0] ;
wire \in.d[8].d[0] ;
wire \in.d[8].d[1] ;
reg \ct.in[7] ;
wire \in.d[6].d[0] ;
wire \in.d[6].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
output y;
input c1;
input p1;
// -- signals ---
reg y;
wire c1;
wire p1;
// --- instances
endmodule
//
// Verilog module for: BUF_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_2C1N_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
output y;
input c1;
input c2;
input n1;
input pr_B;
input sr_B;
// -- signals ---
reg y;
wire pr_B;
wire c2;
wire n1;
wire c1;
reg _y;
wire sr_B;
// --- instances
endmodule
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
reg \out.d.d[8].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[1] ;
reg \_en_X_f[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[7].d[0] ;
reg _reset_BX;
reg \_reset_BXX[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[2].d[0] ;
wire \out.a ;
reg \out.d.d[0].d[0] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[7].d[1] ;
wire \in.d.d[3].d[1] ;
reg _in_v;
reg \in.v ;
reg _out_a_B;
wire \in.d.d[9].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[1].d[0] ;
reg \_out_a_BX_f[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[0].d[1] ;
reg \out.d.d[2].d[1] ;
reg \out.d.d[4].d[1] ;
wire reset_B;
wire \in.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[0] ;
reg \out.d.d[7].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[13].d[1] ;
wire \out.v ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[3].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
reg _en;
reg \out.d.d[13].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[6].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[1].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[0].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf (.y(\in.v ), .a(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv (.y(_out_a_B), .a(\out.a ));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf (.y(_reset_BX), .a(reset_B));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[1] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[13].d[0] ;
reg \out.d.d[13].d[0] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[2].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg _reset_B;
wire \out.v ;
wire \out.a ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[7].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[1].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[8].d[0] ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[5].d[1] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[14].d[1] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[6].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[7].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[1].d[1] ;
reg \in.v ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[3].d[1] ;
wire \in.d.d[6].d[0] ;
reg \out.d.d[11].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[9].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
endmodule

5
test/unit_tests/buf_15/run/prsim.out
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@@ -1,5 +0,0 @@
t.buffer_test._en t.buffer_test._out_a_BX_f[0] t.buffer_test._out_a_BX_t[0] t.buffer_test.f_buf_func[0].n1 t.buffer_test.t_buf_func[7].n1 t.buffer_test.t_buf_func[12].n1 t.buffer_test.f_buf_func[8].n1 t.buffer_test.t_buf_func[10].n1 t.buffer_test._en_X_t[0] t.buffer_test.t_buf_func[3].n1 t.buffer_test.f_buf_func[5].n1 t.out.a t.buffer_test.t_buf_func[11].n1 t.buffer_test.vc.tmp[8] t.buffer_test.f_buf_func[4].n1 t.buffer_test.vc.tmp[0] t.buffer_test.vc.tmp[22] t.buffer_test.f_buf_func[6].n1 t.buffer_test.t_buf_func[2].n1 t.buffer_test.t_buf_func[9].n1 t.buffer_test.f_buf_func[13].n1 t.buffer_test.vc.tmp[18] t.buffer_test.t_buf_func[14].n1 t.buffer_test.vc.tmp[5] t.buffer_test.f_buf_func[7].n1 t.buffer_test.f_buf_func[12].n1 t.buffer_test.t_buf_func[4].n1 t.buffer_test._en_X_f[0] t.buffer_test.vc.tmp[10] t.buffer_test.f_buf_func[14].n1 t.buffer_test.out_a_B_buf_t.buf6._y t.buffer_test.vc.tmp[19] t.buffer_test.t_buf_func[8].n1 t.buffer_test.f_buf_func[9].n1 t.buffer_test.f_buf_func[2].n1 t.buffer_test.vc.tmp[16] t.buffer_test.t_buf_func[1].n1 t.buffer_test.f_buf_func[10].n1 t.buffer_test.vc.tmp[2] t.buffer_test.vc.tmp[14] t.buffer_test.vc.tmp[12] t.buffer_test.vc.tmp[1] t.buffer_test._out_a_B t.buffer_test.f_buf_func[1].n1 t.buffer_test.vc.tmp[4] t.buffer_test.out_a_B_buf_f.buf6._y t.buffer_test.vc.tmp[15] t.buffer_test.vc.tmp[11] t.buffer_test.vc.tmp[13] t.in.v t.buffer_test.vc.OR2_tf[0]._y t.buffer_test.vc.tmp[6] t.buffer_test.vc.tmp[9] t.buffer_test.vc.tmp[24] t.buffer_test.vc.tmp[23] t.buffer_test.vc.OR2_tf[14]._y t.buffer_test._in_v t.buffer_test.t_buf_func[0].n1 t.buffer_test.vc.OR2_tf[4]._y t.buffer_test.t_buf_func[5].n1 t.buffer_test.t_buf_func[6].n1 t.buffer_test.t_buf_func[13].n1 t.buffer_test.f_buf_func[3].n1 t.buffer_test.vc.tmp[7] t.buffer_test.vc.C2Els[0]._y t.buffer_test.vc.OR2_tf[5]._y t.buffer_test.vc.tmp[20] t.buffer_test.en_buf_f.buf6._y t.out.v t.buffer_test.vc.OR2_tf[10]._y t.buffer_test.vc.OR2_tf[8]._y t.buffer_test.vc.OR2_tf[3]._y t.buffer_test.vc.C2Els[7]._y t.buffer_test.vc.C2Els[1]._y t.buffer_test.vc.OR2_tf[6]._y t.buffer_test.vc.C3Els[0]._y t.buffer_test.vc.C2Els[3]._y t.buffer_test.f_buf_func[11].n1 t.buffer_test.vc.tmp[21] t.buffer_test.vc.OR2_tf[11]._y t.buffer_test.in_v_buf._y t.buffer_test.vc.OR2_tf[12]._y t.buffer_test.vc.C2Els[2]._y t.buffer_test.vc.tmp[17] t.buffer_test.vc.tmp[3] t.buffer_test.vc.OR2_tf[2]._y t.buffer_test.vc.OR2_tf[7]._y t.buffer_test.vc.OR2_tf[1]._y t.buffer_test.vc.C3Els[1]._y t.buffer_test.vc.C2Els[4]._y t.buffer_test.vc.OR2_tf[13]._y t.buffer_test.vc.C2Els[6]._y t.buffer_test.vc.OR2_tf[9]._y t.buffer_test.en_buf_t.buf6._y t.buffer_test.vc.C3Els[2]._y t.buffer_test.vc.C2Els[5]._y
yo man
reset completed
Finished

1666
test/unit_tests/buf_15/run/test.prs
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File diff suppressed because it is too large Load Diff

48
test/unit_tests/buf_15/test.act
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@@ -1,48 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc buffer_15 (avMx1of2<15> in; avMx1of2<15> out){
buffer<15> buffer_test(.in=in, .out=out);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
buffer_test.supply.vss = GND;
buffer_test.supply.vdd = Vdd;
buffer_test.reset_B = _reset_B;
}
buffer_15 t;

29
test/unit_tests/buf_15/test.prsim
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@@ -1,29 +0,0 @@
set-qdi-channel-neutral "t.in" 15
set t.out.a 0
set t.out.v 0
cycle
system "echo 'yo man'"
set Reset 0
cycle
system "echo 'reset completed'"
status X
mode run
assert-qdi-channel-neutral "t.out" 15
cycle
set-qdi-channel-valid "t.in" 15 5
cycle
assert t.in.v 1
assert t.in.a 0
assert-qdi-channel-valid "t.out" 15 5
set t.out.v 1
cycle
assert t.in.a 1
set-qdi-channel-neutral "t.in" 15
cycle
set t.out.a 1
system "echo 'Finished'"

571
test/unit_tests/buf_15_friendly2.v
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@@ -1,571 +0,0 @@
//
// Verilog module for: BUF_X6<>
//
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] , vdd, vss);
input vdd;
input vss;
input in;
output \out[0] ;
// -- signals ---
wire in;
reg \out[0] ;
// --- instances
BUF_X6 \buf6 (.y(\out[0] ), .a(in), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
//
// Verilog module for: BUF_X4<>
//
//
// Verilog module for: INV_X1<>
//
//
// Verilog module for: A_2C_B_X1<>
//
//
// Verilog module for: A_3C_B_X1<>
//
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out, vdd, vss);
input vdd;
input vss;
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[4] ;
wire \in[11] ;
wire \in[12] ;
reg \tmp[21] ;
wire \in[3] ;
reg out;
reg \tmp[23] ;
wire \in[6] ;
wire \in[0] ;
reg \tmp[18] ;
wire \in[10] ;
reg \tmp[15] ;
reg \tmp[16] ;
wire \in[13] ;
wire \in[1] ;
wire \in[9] ;
wire \in[2] ;
wire \in[5] ;
reg \tmp[24] ;
wire \in[14] ;
reg \tmp[19] ;
wire \in[7] ;
reg \tmp[22] ;
reg \tmp[20] ;
wire \in[8] ;
reg \tmp[17] ;
// --- instances
A_2C_B_X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ), .vdd(vdd), .vss(vss));
A_2C_B_X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ), .vdd(vdd), .vss(vss));
A_3C_B_X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: OR2_X1<>
//
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out, vdd, vss);
input vdd;
input vss;
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
reg \ct.in[14] ;
reg \ct.in[13] ;
wire \in.d[7].d[0] ;
wire \in.d[1].d[0] ;
wire \in.d[0].d[0] ;
reg \ct.in[4] ;
reg out;
wire \in.d[10].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[3] ;
wire \in.d[9].d[1] ;
wire \in.d[1].d[1] ;
wire \in.d[2].d[0] ;
wire \in.d[10].d[1] ;
reg \ct.in[8] ;
wire \in.d[12].d[0] ;
wire \in.d[5].d[0] ;
wire \in.d[4].d[0] ;
reg \ct.in[10] ;
reg \ct.in[0] ;
wire \in.d[11].d[0] ;
wire \in.d[7].d[1] ;
wire \in.d[3].d[1] ;
reg \ct.in[11] ;
reg \ct.in[2] ;
reg \ct.in[9] ;
wire \in.d[13].d[0] ;
wire \in.d[14].d[1] ;
wire \in.d[11].d[1] ;
wire \in.d[13].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[1] ;
wire \in.d[14].d[0] ;
wire \in.d[12].d[1] ;
wire \in.d[9].d[0] ;
wire \in.d[2].d[1] ;
reg \ct.in[5] ;
wire \in.d[5].d[1] ;
reg \ct.in[12] ;
reg \ct.in[6] ;
wire \in.d[3].d[0] ;
wire \in.d[8].d[0] ;
wire \in.d[8].d[1] ;
reg \ct.in[7] ;
wire \in.d[6].d[0] ;
wire \in.d[6].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ), .vdd(vdd), .vss(vss));
OR2_X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
//
// Verilog module for: BUF_X1<>
//
//
// Verilog module for: A_2C1N_RB_X4<>
//
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B, vdd, vss);
input vdd;
input vss;
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
reg \out.d.d[8].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[1] ;
reg \_en_X_f[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[7].d[0] ;
reg _reset_BX;
reg \_reset_BXX[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[2].d[0] ;
wire \out.a ;
reg \out.d.d[0].d[0] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[7].d[1] ;
wire \in.d.d[3].d[1] ;
reg _in_v;
reg \in.v ;
reg _out_a_B;
wire \in.d.d[9].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[1].d[0] ;
reg \_out_a_BX_f[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[0].d[1] ;
reg \out.d.d[2].d[1] ;
reg \out.d.d[4].d[1] ;
wire reset_B;
wire \in.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[0] ;
reg \out.d.d[7].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[13].d[1] ;
wire \out.v ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[3].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
reg _en;
reg \out.d.d[13].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[6].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[1].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[0].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ), .vdd(vdd), .vss(vss));
A_3C_RB_X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
BUF_X4 \in_v_buf (.y(\in.v ), .a(_in_v), .vdd(vdd), .vss(vss));
INV_X1 \out_a_inv (.y(_out_a_B), .a(\out.a ), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ), .vdd(vdd), .vss(vss));
A_1C1P_X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ), .vdd(vdd), .vss(vss));
BUF_X1 \reset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ), .vdd(vdd), .vss(vss));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
A_2C1N_RB_X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ), .vdd(vdd), .vss(vss));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , vdd, vss);
input vdd;
input vss;
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[1] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[13].d[0] ;
reg \out.d.d[13].d[0] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[2].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg _reset_B;
wire \out.v ;
wire \out.a ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[7].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[1].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[8].d[0] ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[5].d[1] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[14].d[1] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[6].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[7].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[1].d[1] ;
reg \in.v ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[3].d[1] ;
wire \in.d.d[6].d[0] ;
reg \out.d.d[11].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[9].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B), .vdd(vdd), .vss(vss));
endmodule

173
test/unit_tests/buf_s_5/run/prsim.out
View File

@@ -1,173 +0,0 @@
b.b.vc.OR2_tf[2].y b.b.f_buf_func[3].n1 b.b._out_a_BX_f[0] b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[0].y b.b.vc.OR2_tf[1]._y b.b.vc.OR2_tf[1].y b.in.v b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b._en_X_f[0] b.b._en_X_t[0] b.b._out_a_BX_t[0] b.b._in_vX[0] b.out.v b.b.vc.OR2_tf[4].y b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b._out_a_B b.b.t_buf_func[2].n1 b.b.vc.OR2_tf[0]._y b.b.t_buf_func[0].n1 b.b.vc.myctree.tmp[5] b.b.vc.OR2_tf[3].y b.b.in_v_bufN.buf2._y b.b.f_buf_func[4].n1 b.b.vc.myctree.C3Els[0]._y b.b.vc.OR2_tf[2]._y b.b.vc.myctree.tmp[6] b.b.en_buf_f.buf2._y b.b._in_v b.b.vc.myctree.C2Els[0]._y b.b.en_buf_t.buf2._y b.b._en b.b.vc.OR2_tf[4]._y b.out.a b.b.out_a_B_buf_t.buf2._y b.b.in_v_buf4._y b.b.out_a_B_buf_f.buf2._y b.b.vc.myctree.C2Els[1]._y b.b.vc.OR2_tf[3]._y
84120 b.b.f_buf_func[0].n1 : 0
84120 b.b.f_buf_func[4].y : 1
84120 b.b.t_buf_func[4].y : 1
84120 b.b.f_buf_func[1].n1 : 0
84120 b.b.f_buf_func[3].n1 : 0
84120 b.b.f_buf_func[3].y : 1
84120 b.b.t_buf_func[3].y : 1
84120 b.b.f_buf_func[0].y : 1
84120 b.b.t_buf_func[0].y : 1
84120 b.b.t_buf_func[2].n1 : 0
84120 Reset : 0
84120 b.b.f_buf_func[2].y : 1
84120 b.out.v : 0
84120 b.b.t_buf_func[0].n1 : 0
84120 b.b.f_buf_func[2].n1 : 0
84120 b.out.a : 0
84120 b.b.t_buf_func[4].n1 : 0
84120 b.b.t_buf_func[1].n1 : 0
84120 b.b.f_buf_func[4].n1 : 0
84120 b.b.t_buf_func[2].y : 1
84120 b.b.t_buf_func[3].n1 : 0
84120 b.b.f_buf_func[1].y : 1
84120 b.b.t_buf_func[1].y : 1
84121 b.b.f_buf_func[2].y : 0
84121 b.b._en : 1 [by b.out.v:=0]
84123 b.b.vc.OR2_tf[1]._y : 1 [by b.b.t_buf_func[1].n1:=0]
84141 b.b.vc.OR2_tf[1].y : 0 [by b.b.vc.OR2_tf[1]._y:=1]
84402 b.b.vc.OR2_tf[2]._y : 1 [by b.b.f_buf_func[2].n1:=0]
84542 b.b.t_buf_func[0].y : 0
84671 b.b.t_buf_func[2].y : 0
84888 b.b._out_a_B : 1 [by b.out.a:=0]
85074 b.b.f_buf_func[1].y : 0
85103 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
85191 b.b.vc.OR2_tf[3]._y : 1 [by b.b.t_buf_func[3].n1:=0]
85201 b.b.t_buf_func[1].y : 0
88415 b.b.vc.OR2_tf[2].y : 0 [by b.b.vc.OR2_tf[2]._y:=1]
88891 b.b.out_a_B_buf_t.buf2._y : 0 [by b.b._out_a_B:=1]
89393 b.b._out_a_BX_f[0] : 1 [by b.b.out_a_B_buf_t.buf2._y:=0]
89951 b.b.vc.OR2_tf[3].y : 0 [by b.b.vc.OR2_tf[3]._y:=1]
97969 b.b.f_buf_func[3].y : 0
98463 b.b.f_buf_func[0].y : 0
104325 b.b.vc.OR2_tf[0]._y : 1 [by b.b.t_buf_func[0].n1:=0]
104528 b.b.vc.OR2_tf[0].y : 0 [by b.b.vc.OR2_tf[0]._y:=1]
106382 b.b.vc.myctree.C2Els[0]._y : 1 [by b.b.vc.OR2_tf[0].y:=0]
106521 b.b.vc.myctree.tmp[5] : 0 [by b.b.vc.myctree.C2Els[0]._y:=1]
106561 b.b.vc.OR2_tf[4]._y : 1 [by b.b.f_buf_func[4].n1:=0]
106687 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
108932 b.b.t_buf_func[3].y : 0
113900 b.b.t_buf_func[4].y : 0
129789 b.b.out_a_B_buf_f.buf2._y : 0 [by b.b._out_a_B:=1]
129858 b.b._out_a_BX_t[0] : 1 [by b.b.out_a_B_buf_f.buf2._y:=0]
132834 b._reset_B : 1 [by Reset:=0]
132845 b.b.reset_buf._y : 0 [by b._reset_B:=1]
135773 b.b.f_buf_func[4].y : 0
138591 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
138795 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
142907 b.b.vc.OR2_tf[4].y : 0 [by b.b.vc.OR2_tf[4]._y:=1]
142922 b.b.vc.myctree.C3Els[0]._y : 1 [by b.b.vc.OR2_tf[4].y:=0]
142923 b.b.vc.myctree.tmp[6] : 0 [by b.b.vc.myctree.C3Els[0]._y:=1]
142960 b.b.vc.myctree.C2Els[1]._y : 1 [by b.b.vc.myctree.tmp[6]:=0]
143699 b.b._in_v : 0 [by b.b.vc.myctree.C2Els[1]._y:=1]
143811 b.b.in_v_buf4._y : 1 [by b.b._in_v:=0]
184631 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
184671 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
184928 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
191323 b.in.v : 0 [by b.b.in_v_buf4._y:=1]
191410 b.b.in_v_bufN.buf2._y : 1 [by b.in.v:=0]
191704 b.b._in_vX[0] : 0 [by b.b.in_v_bufN.buf2._y:=1]
[] set Reset 1
191704 Reset : 1
191705 b._reset_B : 0 [by Reset:=1]
193511 b.b.reset_buf._y : 1 [by b._reset_B:=0]
195518 b.b._reset_BX : 0 [by b.b.reset_buf._y:=1]
196727 b.b.reset_bufarray.buf2._y : 1 [by b.b._reset_BX:=0]
197317 b.b._reset_BXX[0] : 0 [by b.b.reset_bufarray.buf2._y:=1]
[] set Reset 0
197317 Reset : 0
197495 b._reset_B : 1 [by Reset:=0]
198298 b.b.reset_buf._y : 0 [by b._reset_B:=1]
198462 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
200657 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
200679 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
[] Reset finished, setting some inputs.
200679 b.b.t_buf_func[0].n1 : 1
200679 b.b.f_buf_func[3].n1 : 1
200679 b.b.f_buf_func[2].n1 : 1
200679 b.b.t_buf_func[1].n1 : 1
200812 b.b.vc.OR2_tf[2]._y : 0 [by b.b.f_buf_func[2].n1:=1]
201171 b.b.vc.OR2_tf[2].y : 1 [by b.b.vc.OR2_tf[2]._y:=0]
201526 b.b.vc.OR2_tf[0]._y : 0 [by b.b.t_buf_func[0].n1:=1]
215642 b.b.vc.OR2_tf[0].y : 1 [by b.b.vc.OR2_tf[0]._y:=0]
216341 b.b.vc.OR2_tf[1]._y : 0 [by b.b.t_buf_func[1].n1:=1]
216562 b.b.vc.OR2_tf[1].y : 1 [by b.b.vc.OR2_tf[1]._y:=0]
216569 b.b.vc.myctree.C2Els[0]._y : 0 [by b.b.vc.OR2_tf[1].y:=1]
216599 b.b.vc.myctree.tmp[5] : 1 [by b.b.vc.myctree.C2Els[0]._y:=0]
230807 b.b.vc.OR2_tf[3]._y : 0 [by b.b.f_buf_func[3].n1:=1]
237520 b.b.vc.OR2_tf[3].y : 1 [by b.b.vc.OR2_tf[3]._y:=0]
[] Setting final input
237520 b.b.t_buf_func[4].n1 : 1
294981 b.b.vc.OR2_tf[4]._y : 0 [by b.b.t_buf_func[4].n1:=1]
295072 b.b.vc.OR2_tf[4].y : 1 [by b.b.vc.OR2_tf[4]._y:=0]
297261 b.b.vc.myctree.C3Els[0]._y : 0 [by b.b.vc.OR2_tf[4].y:=1]
297268 b.b.vc.myctree.tmp[6] : 1 [by b.b.vc.myctree.C3Els[0]._y:=0]
300055 b.b.vc.myctree.C2Els[1]._y : 0 [by b.b.vc.myctree.tmp[6]:=1]
300161 b.b._in_v : 1 [by b.b.vc.myctree.C2Els[1]._y:=0]
300239 b.b.in_v_buf4._y : 0 [by b.b._in_v:=1]
300514 b.in.v : 1 [by b.b.in_v_buf4._y:=0]
319510 b.b.in_v_bufN.buf2._y : 0 [by b.in.v:=1]
319965 b.b._in_vX[0] : 1 [by b.b.in_v_bufN.buf2._y:=0]
319977 b.b.t_buf_func[0]._y : 0 [by b.b._in_vX[0]:=1]
319977 b.b.t_buf_func[4]._y : 0 [by b.b._in_vX[0]:=1]
320369 b.b.t_buf_func[1]._y : 0 [by b.b._in_vX[0]:=1]
320371 b.b.t_buf_func[1].y : 1 [by b.b.t_buf_func[1]._y:=0]
322876 b.b.t_buf_func[0].y : 1 [by b.b.t_buf_func[0]._y:=0]
324241 b.b.f_buf_func[3]._y : 0 [by b.b._in_vX[0]:=1]
324272 b.b.t_buf_func[4].y : 1 [by b.b.t_buf_func[4]._y:=0]
325881 b.b.f_buf_func[2]._y : 0 [by b.b._in_vX[0]:=1]
327130 b.b.f_buf_func[2].y : 1 [by b.b.f_buf_func[2]._y:=0]
328776 b.b.f_buf_func[3].y : 1 [by b.b.f_buf_func[3]._y:=0]
[] Receiving out val
328776 b.out.v : 1
332275 b.b.inack_ctl._y : 0 [by b.out.v:=1]
332441 b.in.a : 1 [by b.b.inack_ctl._y:=0]
332516 b.b._en : 0 [by b.in.a:=1]
332654 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
332861 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
332863 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
337917 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
[] Removing input
337917 b.b.t_buf_func[0].n1 : 0
337917 b.b.t_buf_func[4].n1 : 0
337917 b.b.f_buf_func[2].n1 : 0
337917 b.b.t_buf_func[1].n1 : 0
337917 b.b.f_buf_func[3].n1 : 0
337918 b.b.vc.OR2_tf[4]._y : 1 [by b.b.t_buf_func[4].n1:=0]
337928 b.b.vc.OR2_tf[1]._y : 1 [by b.b.t_buf_func[1].n1:=0]
337985 b.b.vc.OR2_tf[4].y : 0 [by b.b.vc.OR2_tf[4]._y:=1]
338287 b.b.vc.OR2_tf[3]._y : 1 [by b.b.f_buf_func[3].n1:=0]
338303 b.b.vc.OR2_tf[3].y : 0 [by b.b.vc.OR2_tf[3]._y:=1]
338465 b.b.vc.OR2_tf[2]._y : 1 [by b.b.f_buf_func[2].n1:=0]
340569 b.b.vc.OR2_tf[1].y : 0 [by b.b.vc.OR2_tf[1]._y:=1]
343027 b.b.vc.OR2_tf[2].y : 0 [by b.b.vc.OR2_tf[2]._y:=1]
343555 b.b.vc.myctree.C3Els[0]._y : 1 [by b.b.vc.OR2_tf[2].y:=0]
345990 b.b.vc.myctree.tmp[6] : 0 [by b.b.vc.myctree.C3Els[0]._y:=1]
381834 b.b.vc.OR2_tf[0]._y : 1 [by b.b.t_buf_func[0].n1:=0]
408714 b.b.vc.OR2_tf[0].y : 0 [by b.b.vc.OR2_tf[0]._y:=1]
432639 b.b.vc.myctree.C2Els[0]._y : 1 [by b.b.vc.OR2_tf[0].y:=0]
445680 b.b.vc.myctree.tmp[5] : 0 [by b.b.vc.myctree.C2Els[0]._y:=1]
445682 b.b.vc.myctree.C2Els[1]._y : 1 [by b.b.vc.myctree.tmp[5]:=0]
506640 b.b._in_v : 0 [by b.b.vc.myctree.C2Els[1]._y:=1]
506643 b.b.in_v_buf4._y : 1 [by b.b._in_v:=0]
506672 b.in.v : 0 [by b.b.in_v_buf4._y:=1]
506989 b.b.in_v_bufN.buf2._y : 1 [by b.in.v:=0]
508590 b.b._in_vX[0] : 0 [by b.b.in_v_bufN.buf2._y:=1]
[] Receiving out ack
508590 b.out.a : 1
508743 b.b._out_a_B : 0 [by b.out.a:=1]
508787 b.b.out_a_B_buf_t.buf2._y : 1 [by b.b._out_a_B:=0]
511504 b.b.out_a_B_buf_f.buf2._y : 1 [by b.b._out_a_B:=0]
511505 b.b._out_a_BX_t[0] : 0 [by b.b.out_a_B_buf_f.buf2._y:=1]
511506 b.b.t_buf_func[4]._y : 1 [by b.b._out_a_BX_t[0]:=0]
511527 b.b.t_buf_func[1]._y : 1 [by b.b._out_a_BX_t[0]:=0]
511722 b.b.t_buf_func[0]._y : 1 [by b.b._out_a_BX_t[0]:=0]
511881 b.b.t_buf_func[0].y : 0 [by b.b.t_buf_func[0]._y:=1]
513087 b.b.t_buf_func[4].y : 0 [by b.b.t_buf_func[4]._y:=1]
520872 b.b.t_buf_func[1].y : 0 [by b.b.t_buf_func[1]._y:=1]
522470 b.b._out_a_BX_f[0] : 0 [by b.b.out_a_B_buf_t.buf2._y:=1]
523757 b.b.f_buf_func[3]._y : 1 [by b.b._out_a_BX_f[0]:=0]
525989 b.b.f_buf_func[3].y : 0 [by b.b.f_buf_func[3]._y:=1]
542146 b.b.f_buf_func[2]._y : 1 [by b.b._out_a_BX_f[0]:=0]
542291 b.b.f_buf_func[2].y : 0 [by b.b.f_buf_func[2]._y:=1]

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test/unit_tests/buf_s_5/run/prsim.pdf
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654
test/unit_tests/buf_s_5/run/test.prs
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@@ -1,654 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"b._reset_B"-
~("Reset")->"b._reset_B"+
"b.b.out_a_B_buf_t.buf2.a"->"b.b.out_a_B_buf_t.buf2._y"-
~("b.b.out_a_B_buf_t.buf2.a")->"b.b.out_a_B_buf_t.buf2._y"+
"b.b.out_a_B_buf_t.buf2._y"->"b.b.out_a_B_buf_t.buf2.y"-
~("b.b.out_a_B_buf_t.buf2._y")->"b.b.out_a_B_buf_t.buf2.y"+
= "b.b.out_a_B_buf_t.supply.vdd" "b.b.out_a_B_buf_t.buf2.vdd"
= "b.b.out_a_B_buf_t.supply.vss" "b.b.out_a_B_buf_t.buf2.vss"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[4]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[3]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[2]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.out[1]"
= "b.b.out_a_B_buf_t.out[0]" "b.b.out_a_B_buf_t.buf2.y"
= "b.b.out_a_B_buf_t.in" "b.b.out_a_B_buf_t.buf2.a"
= "b.b._en_X_f[0]" "b.b.en_buf_f.out[0]"
= "b.b._en_X_f[1]" "b.b.en_buf_f.out[1]"
= "b.b._en_X_f[2]" "b.b.en_buf_f.out[2]"
= "b.b._en_X_f[3]" "b.b.en_buf_f.out[3]"
= "b.b._en_X_f[4]" "b.b.en_buf_f.out[4]"
= "b.b._en_X_f[0]" "b.b.f_buf_func[4].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[3].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[2].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[1].c1"
= "b.b._en_X_f[0]" "b.b.f_buf_func[0].c1"
= "b.b._en_X_f[0]" "b.b._en_X_f[4]"
= "b.b._en_X_f[0]" "b.b._en_X_f[3]"
= "b.b._en_X_f[0]" "b.b._en_X_f[2]"
= "b.b._en_X_f[0]" "b.b._en_X_f[1]"
~"b.b.inack_ctl.c1"&~"b.b.inack_ctl.c2"&~"b.b.inack_ctl.c3"|~"b.b.inack_ctl.pr_B"->"b.b.inack_ctl._y"+
"b.b.inack_ctl.c1"&"b.b.inack_ctl.c2"&"b.b.inack_ctl.c3"&"b.b.inack_ctl.sr_B"->"b.b.inack_ctl._y"-
"b.b.inack_ctl._y"->"b.b.inack_ctl.y"-
~("b.b.inack_ctl._y")->"b.b.inack_ctl.y"+
"b.b.reset_bufarray.buf2.a"->"b.b.reset_bufarray.buf2._y"-
~("b.b.reset_bufarray.buf2.a")->"b.b.reset_bufarray.buf2._y"+
"b.b.reset_bufarray.buf2._y"->"b.b.reset_bufarray.buf2.y"-
~("b.b.reset_bufarray.buf2._y")->"b.b.reset_bufarray.buf2.y"+
= "b.b.reset_bufarray.supply.vdd" "b.b.reset_bufarray.buf2.vdd"
= "b.b.reset_bufarray.supply.vss" "b.b.reset_bufarray.buf2.vss"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[4]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[3]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[2]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[1]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.buf2.y"
= "b.b.reset_bufarray.in" "b.b.reset_bufarray.buf2.a"
"b.b.in_v_buf4.a"->"b.b.in_v_buf4._y"-
~("b.b.in_v_buf4.a")->"b.b.in_v_buf4._y"+
"b.b.in_v_buf4._y"->"b.b.in_v_buf4.y"-
~("b.b.in_v_buf4._y")->"b.b.in_v_buf4.y"+
"b.b.out_a_inv.a"->"b.b.out_a_inv.y"-
~("b.b.out_a_inv.a")->"b.b.out_a_inv.y"+
= "b.b._out_a_BX_f[0]" "b.b.out_a_B_buf_t.out[0]"
= "b.b._out_a_BX_f[1]" "b.b.out_a_B_buf_t.out[1]"
= "b.b._out_a_BX_f[2]" "b.b.out_a_B_buf_t.out[2]"
= "b.b._out_a_BX_f[3]" "b.b.out_a_B_buf_t.out[3]"
= "b.b._out_a_BX_f[4]" "b.b.out_a_B_buf_t.out[4]"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[4].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[3].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[2].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[1].c2"
= "b.b._out_a_BX_f[0]" "b.b.f_buf_func[0].c2"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[4]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[3]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[2]"
= "b.b._out_a_BX_f[0]" "b.b._out_a_BX_f[1]"
= "b.b.supply.vss" "b.b.en_buf_f.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_f.supply.vdd"
= "b.b.supply.vss" "b.b.en_buf_t.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_t.supply.vdd"
= "b.b.supply.vss" "b.b.in_v_bufN.supply.vss"
= "b.b.supply.vdd" "b.b.in_v_bufN.supply.vdd"
= "b.b.supply.vss" "b.b.vc.supply.vss"
= "b.b.supply.vdd" "b.b.vc.supply.vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.in_v_buf4.vdd"
= "b.b.supply.vdd" "b.b.reset_buf.vdd"
= "b.b.supply.vdd" "b.b.en_ctl.vdd"
= "b.b.supply.vdd" "b.b.inack_ctl.vdd"
= "b.b.supply.vss" "b.b.t_buf_func[4].vss"
= "b.b.supply.vss" "b.b.f_buf_func[4].vss"
= "b.b.supply.vss" "b.b.t_buf_func[3].vss"
= "b.b.supply.vss" "b.b.f_buf_func[3].vss"
= "b.b.supply.vss" "b.b.t_buf_func[2].vss"
= "b.b.supply.vss" "b.b.f_buf_func[2].vss"
= "b.b.supply.vss" "b.b.t_buf_func[1].vss"
= "b.b.supply.vss" "b.b.f_buf_func[1].vss"
= "b.b.supply.vss" "b.b.t_buf_func[0].vss"
= "b.b.supply.vss" "b.b.f_buf_func[0].vss"
= "b.b.supply.vss" "b.b.in_v_buf4.vss"
= "b.b.supply.vss" "b.b.reset_buf.vss"
= "b.b.supply.vss" "b.b.en_ctl.vss"
= "b.b.supply.vss" "b.b.inack_ctl.vss"
~"b.b.vc.myctree.C2Els[0].c1"&~"b.b.vc.myctree.C2Els[0].c2"->"b.b.vc.myctree.C2Els[0]._y"+
"b.b.vc.myctree.C2Els[0].c1"&"b.b.vc.myctree.C2Els[0].c2"->"b.b.vc.myctree.C2Els[0]._y"-
"b.b.vc.myctree.C2Els[0]._y"->"b.b.vc.myctree.C2Els[0].y"-
~("b.b.vc.myctree.C2Els[0]._y")->"b.b.vc.myctree.C2Els[0].y"+
~"b.b.vc.myctree.C2Els[1].c1"&~"b.b.vc.myctree.C2Els[1].c2"->"b.b.vc.myctree.C2Els[1]._y"+
"b.b.vc.myctree.C2Els[1].c1"&"b.b.vc.myctree.C2Els[1].c2"->"b.b.vc.myctree.C2Els[1]._y"-
"b.b.vc.myctree.C2Els[1]._y"->"b.b.vc.myctree.C2Els[1].y"-
~("b.b.vc.myctree.C2Els[1]._y")->"b.b.vc.myctree.C2Els[1].y"+
~"b.b.vc.myctree.C3Els[0].c1"&~"b.b.vc.myctree.C3Els[0].c2"&~"b.b.vc.myctree.C3Els[0].c3"->"b.b.vc.myctree.C3Els[0]._y"+
"b.b.vc.myctree.C3Els[0].c1"&"b.b.vc.myctree.C3Els[0].c2"&"b.b.vc.myctree.C3Els[0].c3"->"b.b.vc.myctree.C3Els[0]._y"-
"b.b.vc.myctree.C3Els[0]._y"->"b.b.vc.myctree.C3Els[0].y"-
~("b.b.vc.myctree.C3Els[0]._y")->"b.b.vc.myctree.C3Els[0].y"+
= "b.b.vc.myctree.tmp[5]" "b.b.vc.myctree.C2Els[1].c1"
= "b.b.vc.myctree.tmp[5]" "b.b.vc.myctree.C2Els[0].y"
= "b.b.vc.myctree.tmp[6]" "b.b.vc.myctree.C2Els[1].c2"
= "b.b.vc.myctree.tmp[6]" "b.b.vc.myctree.C3Els[0].y"
= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C3Els[0].vdd"
= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C2Els[1].vdd"
= "b.b.vc.myctree.supply.vdd" "b.b.vc.myctree.C2Els[0].vdd"
= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C3Els[0].vss"
= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C2Els[1].vss"
= "b.b.vc.myctree.supply.vss" "b.b.vc.myctree.C2Els[0].vss"
= "b.b.vc.myctree.in[0]" "b.b.vc.myctree.C2Els[0].c1"
= "b.b.vc.myctree.in[0]" "b.b.vc.myctree.tmp[0]"
= "b.b.vc.myctree.in[1]" "b.b.vc.myctree.C2Els[0].c2"
= "b.b.vc.myctree.in[1]" "b.b.vc.myctree.tmp[1]"
= "b.b.vc.myctree.in[2]" "b.b.vc.myctree.C3Els[0].c1"
= "b.b.vc.myctree.in[2]" "b.b.vc.myctree.tmp[2]"
= "b.b.vc.myctree.in[3]" "b.b.vc.myctree.C3Els[0].c2"
= "b.b.vc.myctree.in[3]" "b.b.vc.myctree.tmp[3]"
= "b.b.vc.myctree.in[4]" "b.b.vc.myctree.C3Els[0].c3"
= "b.b.vc.myctree.in[4]" "b.b.vc.myctree.tmp[4]"
= "b.b.vc.myctree.out" "b.b.vc.myctree.C2Els[1].y"
= "b.b.vc.myctree.out" "b.b.vc.myctree.tmp[7]"
"b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b"->"b.b.vc.OR2_tf[0]._y"-
~("b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b")->"b.b.vc.OR2_tf[0]._y"+
"b.b.vc.OR2_tf[0]._y"->"b.b.vc.OR2_tf[0].y"-
~("b.b.vc.OR2_tf[0]._y")->"b.b.vc.OR2_tf[0].y"+
"b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b"->"b.b.vc.OR2_tf[1]._y"-
~("b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b")->"b.b.vc.OR2_tf[1]._y"+
"b.b.vc.OR2_tf[1]._y"->"b.b.vc.OR2_tf[1].y"-
~("b.b.vc.OR2_tf[1]._y")->"b.b.vc.OR2_tf[1].y"+
"b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b"->"b.b.vc.OR2_tf[2]._y"-
~("b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b")->"b.b.vc.OR2_tf[2]._y"+
"b.b.vc.OR2_tf[2]._y"->"b.b.vc.OR2_tf[2].y"-
~("b.b.vc.OR2_tf[2]._y")->"b.b.vc.OR2_tf[2].y"+
"b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b"->"b.b.vc.OR2_tf[3]._y"-
~("b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b")->"b.b.vc.OR2_tf[3]._y"+
"b.b.vc.OR2_tf[3]._y"->"b.b.vc.OR2_tf[3].y"-
~("b.b.vc.OR2_tf[3]._y")->"b.b.vc.OR2_tf[3].y"+
"b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b"->"b.b.vc.OR2_tf[4]._y"-
~("b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b")->"b.b.vc.OR2_tf[4]._y"+
"b.b.vc.OR2_tf[4]._y"->"b.b.vc.OR2_tf[4].y"-
~("b.b.vc.OR2_tf[4]._y")->"b.b.vc.OR2_tf[4].y"+
= "b.b.vc.OR2_tf[4].y" "b.b.vc.myctree.in[4]"
= "b.b.vc.OR2_tf[3].y" "b.b.vc.myctree.in[3]"
= "b.b.vc.OR2_tf[2].y" "b.b.vc.myctree.in[2]"
= "b.b.vc.OR2_tf[1].y" "b.b.vc.myctree.in[1]"
= "b.b.vc.OR2_tf[0].y" "b.b.vc.myctree.in[0]"
= "b.b.vc.supply.vss" "b.b.vc.myctree.supply.vss"
= "b.b.vc.supply.vdd" "b.b.vc.myctree.supply.vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[4].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[3].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[2].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[1].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[0].vdd"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[4].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[3].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[2].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[1].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[0].vss"
= "b.b.vc.out" "b.b.vc.myctree.out"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.OR2_tf[4].b"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.OR2_tf[4].a"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.OR2_tf[3].b"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.OR2_tf[3].a"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.OR2_tf[2].b"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.OR2_tf[2].a"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.OR2_tf[1].b"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.OR2_tf[1].a"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.OR2_tf[0].b"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.OR2_tf[0].a"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
"b.b.out_a_B_buf_f.buf2.a"->"b.b.out_a_B_buf_f.buf2._y"-
~("b.b.out_a_B_buf_f.buf2.a")->"b.b.out_a_B_buf_f.buf2._y"+
"b.b.out_a_B_buf_f.buf2._y"->"b.b.out_a_B_buf_f.buf2.y"-
~("b.b.out_a_B_buf_f.buf2._y")->"b.b.out_a_B_buf_f.buf2.y"+
= "b.b.out_a_B_buf_f.supply.vdd" "b.b.out_a_B_buf_f.buf2.vdd"
= "b.b.out_a_B_buf_f.supply.vss" "b.b.out_a_B_buf_f.buf2.vss"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[4]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[3]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[2]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.out[1]"
= "b.b.out_a_B_buf_f.out[0]" "b.b.out_a_B_buf_f.buf2.y"
= "b.b.out_a_B_buf_f.in" "b.b.out_a_B_buf_f.buf2.a"
= "b.b._en" "b.b.en_buf_f.in"
= "b.b._en" "b.b.en_buf_t.in"
= "b.b._en" "b.b.en_ctl.y"
= "b.b._en" "b.b.inack_ctl.c1"
~"b.b.en_ctl.p1"&~"b.b.en_ctl.c1"->"b.b.en_ctl.y"+
"b.b.en_ctl.c1"->"b.b.en_ctl.y"-
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.out.a" "b.b.out_a_inv.a"
= "b.b.out.v" "b.b.en_ctl.p1"
= "b.b.out.v" "b.b.inack_ctl.c3"
= "b.b.out.d.d[4].d[0]" "b.b.f_buf_func[4].y"
= "b.b.out.d.d[4].d[0]" "b.b.out.d.d[4].f"
= "b.b.out.d.d[4].d[1]" "b.b.t_buf_func[4].y"
= "b.b.out.d.d[4].d[1]" "b.b.out.d.d[4].t"
= "b.b.out.d.d[3].d[0]" "b.b.f_buf_func[3].y"
= "b.b.out.d.d[3].d[0]" "b.b.out.d.d[3].f"
= "b.b.out.d.d[3].d[1]" "b.b.t_buf_func[3].y"
= "b.b.out.d.d[3].d[1]" "b.b.out.d.d[3].t"
= "b.b.out.d.d[2].d[0]" "b.b.f_buf_func[2].y"
= "b.b.out.d.d[2].d[0]" "b.b.out.d.d[2].f"
= "b.b.out.d.d[2].d[1]" "b.b.t_buf_func[2].y"
= "b.b.out.d.d[2].d[1]" "b.b.out.d.d[2].t"
= "b.b.out.d.d[1].d[0]" "b.b.f_buf_func[1].y"
= "b.b.out.d.d[1].d[0]" "b.b.out.d.d[1].f"
= "b.b.out.d.d[1].d[1]" "b.b.t_buf_func[1].y"
= "b.b.out.d.d[1].d[1]" "b.b.out.d.d[1].t"
= "b.b.out.d.d[0].d[0]" "b.b.f_buf_func[0].y"
= "b.b.out.d.d[0].d[0]" "b.b.out.d.d[0].f"
= "b.b.out.d.d[0].d[1]" "b.b.t_buf_func[0].y"
= "b.b.out.d.d[0].d[1]" "b.b.out.d.d[0].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[0].f" "b.b.vc.in.d[0].f"
= "b.b.in.d.d[0].t" "b.b.vc.in.d[0].t"
= "b.b.in.d.d[0].d[0]" "b.b.vc.in.d[0].d[0]"
= "b.b.in.d.d[0].d[1]" "b.b.vc.in.d[0].d[1]"
= "b.b.in.d.d[1].f" "b.b.vc.in.d[1].f"
= "b.b.in.d.d[1].t" "b.b.vc.in.d[1].t"
= "b.b.in.d.d[1].d[0]" "b.b.vc.in.d[1].d[0]"
= "b.b.in.d.d[1].d[1]" "b.b.vc.in.d[1].d[1]"
= "b.b.in.d.d[2].f" "b.b.vc.in.d[2].f"
= "b.b.in.d.d[2].t" "b.b.vc.in.d[2].t"
= "b.b.in.d.d[2].d[0]" "b.b.vc.in.d[2].d[0]"
= "b.b.in.d.d[2].d[1]" "b.b.vc.in.d[2].d[1]"
= "b.b.in.d.d[3].f" "b.b.vc.in.d[3].f"
= "b.b.in.d.d[3].t" "b.b.vc.in.d[3].t"
= "b.b.in.d.d[3].d[0]" "b.b.vc.in.d[3].d[0]"
= "b.b.in.d.d[3].d[1]" "b.b.vc.in.d[3].d[1]"
= "b.b.in.d.d[4].f" "b.b.vc.in.d[4].f"
= "b.b.in.d.d[4].t" "b.b.vc.in.d[4].t"
= "b.b.in.d.d[4].d[0]" "b.b.vc.in.d[4].d[0]"
= "b.b.in.d.d[4].d[1]" "b.b.vc.in.d[4].d[1]"
= "b.b.in.a" "b.b.en_ctl.c1"
= "b.b.in.a" "b.b.inack_ctl.y"
= "b.b.in.v" "b.b.in_v_bufN.in"
= "b.b.in.v" "b.b.in_v_buf4.y"
= "b.b.in.v" "b.b.inack_ctl.c2"
= "b.b.in.d.d[4].d[0]" "b.b.f_buf_func[4].n1"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.t_buf_func[4].n1"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.f_buf_func[3].n1"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.t_buf_func[3].n1"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.f_buf_func[2].n1"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.t_buf_func[2].n1"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.f_buf_func[1].n1"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.t_buf_func[1].n1"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.f_buf_func[0].n1"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.t_buf_func[0].n1"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
"b.b.reset_buf.a"->"b.b.reset_buf._y"-
~("b.b.reset_buf.a")->"b.b.reset_buf._y"+
"b.b.reset_buf._y"->"b.b.reset_buf.y"-
~("b.b.reset_buf._y")->"b.b.reset_buf.y"+
= "b.b._in_v" "b.b.in_v_buf4.a"
= "b.b._in_v" "b.b.vc.out"
= "b.b._out_a_BX_t[0]" "b.b.out_a_B_buf_f.out[0]"
= "b.b._out_a_BX_t[1]" "b.b.out_a_B_buf_f.out[1]"
= "b.b._out_a_BX_t[2]" "b.b.out_a_B_buf_f.out[2]"
= "b.b._out_a_BX_t[3]" "b.b.out_a_B_buf_f.out[3]"
= "b.b._out_a_BX_t[4]" "b.b.out_a_B_buf_f.out[4]"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[4].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[3].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[2].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[1].c2"
= "b.b._out_a_BX_t[0]" "b.b.t_buf_func[0].c2"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[4]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[3]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[2]"
= "b.b._out_a_BX_t[0]" "b.b._out_a_BX_t[1]"
= "b.b._reset_BX" "b.b.reset_bufarray.in"
= "b.b._reset_BX" "b.b.reset_buf.y"
= "b.b._reset_BX" "b.b.inack_ctl.sr_B"
= "b.b._reset_BX" "b.b.inack_ctl.pr_B"
= "b.b.reset_B" "b.b.reset_buf.a"
"b.b.en_buf_f.buf2.a"->"b.b.en_buf_f.buf2._y"-
~("b.b.en_buf_f.buf2.a")->"b.b.en_buf_f.buf2._y"+
"b.b.en_buf_f.buf2._y"->"b.b.en_buf_f.buf2.y"-
~("b.b.en_buf_f.buf2._y")->"b.b.en_buf_f.buf2.y"+
= "b.b.en_buf_f.supply.vdd" "b.b.en_buf_f.buf2.vdd"
= "b.b.en_buf_f.supply.vss" "b.b.en_buf_f.buf2.vss"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[4]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[3]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[2]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[1]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.buf2.y"
= "b.b.en_buf_f.in" "b.b.en_buf_f.buf2.a"
"b.b.en_buf_t.buf2.a"->"b.b.en_buf_t.buf2._y"-
~("b.b.en_buf_t.buf2.a")->"b.b.en_buf_t.buf2._y"+
"b.b.en_buf_t.buf2._y"->"b.b.en_buf_t.buf2.y"-
~("b.b.en_buf_t.buf2._y")->"b.b.en_buf_t.buf2.y"+
= "b.b.en_buf_t.supply.vdd" "b.b.en_buf_t.buf2.vdd"
= "b.b.en_buf_t.supply.vss" "b.b.en_buf_t.buf2.vss"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[4]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[3]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[2]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[1]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.buf2.y"
= "b.b.en_buf_t.in" "b.b.en_buf_t.buf2.a"
= "b.b._out_a_B" "b.b.out_a_B_buf_t.in"
= "b.b._out_a_B" "b.b.out_a_B_buf_f.in"
= "b.b._out_a_B" "b.b.out_a_inv.y"
= "b.b._reset_BXX[0]" "b.b.reset_bufarray.out[0]"
= "b.b._reset_BXX[1]" "b.b.reset_bufarray.out[1]"
= "b.b._reset_BXX[2]" "b.b.reset_bufarray.out[2]"
= "b.b._reset_BXX[3]" "b.b.reset_bufarray.out[3]"
= "b.b._reset_BXX[4]" "b.b.reset_bufarray.out[4]"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.t_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[4]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[3]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[2]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[1]"
= "b.b._in_vX[0]" "b.b.in_v_bufN.out[0]"
= "b.b._in_vX[1]" "b.b.in_v_bufN.out[1]"
= "b.b._in_vX[2]" "b.b.in_v_bufN.out[2]"
= "b.b._in_vX[3]" "b.b.in_v_bufN.out[3]"
= "b.b._in_vX[4]" "b.b.in_v_bufN.out[4]"
= "b.b._in_vX[0]" "b.b.t_buf_func[4].n2"
= "b.b._in_vX[0]" "b.b.f_buf_func[4].n2"
= "b.b._in_vX[0]" "b.b.t_buf_func[3].n2"
= "b.b._in_vX[0]" "b.b.f_buf_func[3].n2"
= "b.b._in_vX[0]" "b.b.t_buf_func[2].n2"
= "b.b._in_vX[0]" "b.b.f_buf_func[2].n2"
= "b.b._in_vX[0]" "b.b.t_buf_func[1].n2"
= "b.b._in_vX[0]" "b.b.f_buf_func[1].n2"
= "b.b._in_vX[0]" "b.b.t_buf_func[0].n2"
= "b.b._in_vX[0]" "b.b.f_buf_func[0].n2"
= "b.b._in_vX[0]" "b.b._in_vX[4]"
= "b.b._in_vX[0]" "b.b._in_vX[3]"
= "b.b._in_vX[0]" "b.b._in_vX[2]"
= "b.b._in_vX[0]" "b.b._in_vX[1]"
"b.b.in_v_bufN.buf2.a"->"b.b.in_v_bufN.buf2._y"-
~("b.b.in_v_bufN.buf2.a")->"b.b.in_v_bufN.buf2._y"+
"b.b.in_v_bufN.buf2._y"->"b.b.in_v_bufN.buf2.y"-
~("b.b.in_v_bufN.buf2._y")->"b.b.in_v_bufN.buf2.y"+
= "b.b.in_v_bufN.supply.vdd" "b.b.in_v_bufN.buf2.vdd"
= "b.b.in_v_bufN.supply.vss" "b.b.in_v_bufN.buf2.vss"
= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[4]"
= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[3]"
= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[2]"
= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.out[1]"
= "b.b.in_v_bufN.out[0]" "b.b.in_v_bufN.buf2.y"
= "b.b.in_v_bufN.in" "b.b.in_v_bufN.buf2.a"
~"b.b.t_buf_func[0].c1"&~"b.b.t_buf_func[0].c2"|~"b.b.t_buf_func[0].pr_B"->"b.b.t_buf_func[0]._y"+
"b.b.t_buf_func[0].c1"&"b.b.t_buf_func[0].c2"&"b.b.t_buf_func[0].n1"&"b.b.t_buf_func[0].n2"&"b.b.t_buf_func[0].sr_B"->"b.b.t_buf_func[0]._y"-
"b.b.t_buf_func[0]._y"->"b.b.t_buf_func[0].y"-
~("b.b.t_buf_func[0]._y")->"b.b.t_buf_func[0].y"+
~"b.b.t_buf_func[1].c1"&~"b.b.t_buf_func[1].c2"|~"b.b.t_buf_func[1].pr_B"->"b.b.t_buf_func[1]._y"+
"b.b.t_buf_func[1].c1"&"b.b.t_buf_func[1].c2"&"b.b.t_buf_func[1].n1"&"b.b.t_buf_func[1].n2"&"b.b.t_buf_func[1].sr_B"->"b.b.t_buf_func[1]._y"-
"b.b.t_buf_func[1]._y"->"b.b.t_buf_func[1].y"-
~("b.b.t_buf_func[1]._y")->"b.b.t_buf_func[1].y"+
~"b.b.t_buf_func[2].c1"&~"b.b.t_buf_func[2].c2"|~"b.b.t_buf_func[2].pr_B"->"b.b.t_buf_func[2]._y"+
"b.b.t_buf_func[2].c1"&"b.b.t_buf_func[2].c2"&"b.b.t_buf_func[2].n1"&"b.b.t_buf_func[2].n2"&"b.b.t_buf_func[2].sr_B"->"b.b.t_buf_func[2]._y"-
"b.b.t_buf_func[2]._y"->"b.b.t_buf_func[2].y"-
~("b.b.t_buf_func[2]._y")->"b.b.t_buf_func[2].y"+
~"b.b.t_buf_func[3].c1"&~"b.b.t_buf_func[3].c2"|~"b.b.t_buf_func[3].pr_B"->"b.b.t_buf_func[3]._y"+
"b.b.t_buf_func[3].c1"&"b.b.t_buf_func[3].c2"&"b.b.t_buf_func[3].n1"&"b.b.t_buf_func[3].n2"&"b.b.t_buf_func[3].sr_B"->"b.b.t_buf_func[3]._y"-
"b.b.t_buf_func[3]._y"->"b.b.t_buf_func[3].y"-
~("b.b.t_buf_func[3]._y")->"b.b.t_buf_func[3].y"+
~"b.b.t_buf_func[4].c1"&~"b.b.t_buf_func[4].c2"|~"b.b.t_buf_func[4].pr_B"->"b.b.t_buf_func[4]._y"+
"b.b.t_buf_func[4].c1"&"b.b.t_buf_func[4].c2"&"b.b.t_buf_func[4].n1"&"b.b.t_buf_func[4].n2"&"b.b.t_buf_func[4].sr_B"->"b.b.t_buf_func[4]._y"-
"b.b.t_buf_func[4]._y"->"b.b.t_buf_func[4].y"-
~("b.b.t_buf_func[4]._y")->"b.b.t_buf_func[4].y"+
~"b.b.f_buf_func[0].c1"&~"b.b.f_buf_func[0].c2"|~"b.b.f_buf_func[0].pr_B"->"b.b.f_buf_func[0]._y"+
"b.b.f_buf_func[0].c1"&"b.b.f_buf_func[0].c2"&"b.b.f_buf_func[0].n1"&"b.b.f_buf_func[0].n2"&"b.b.f_buf_func[0].sr_B"->"b.b.f_buf_func[0]._y"-
"b.b.f_buf_func[0]._y"->"b.b.f_buf_func[0].y"-
~("b.b.f_buf_func[0]._y")->"b.b.f_buf_func[0].y"+
~"b.b.f_buf_func[1].c1"&~"b.b.f_buf_func[1].c2"|~"b.b.f_buf_func[1].pr_B"->"b.b.f_buf_func[1]._y"+
"b.b.f_buf_func[1].c1"&"b.b.f_buf_func[1].c2"&"b.b.f_buf_func[1].n1"&"b.b.f_buf_func[1].n2"&"b.b.f_buf_func[1].sr_B"->"b.b.f_buf_func[1]._y"-
"b.b.f_buf_func[1]._y"->"b.b.f_buf_func[1].y"-
~("b.b.f_buf_func[1]._y")->"b.b.f_buf_func[1].y"+
~"b.b.f_buf_func[2].c1"&~"b.b.f_buf_func[2].c2"|~"b.b.f_buf_func[2].pr_B"->"b.b.f_buf_func[2]._y"+
"b.b.f_buf_func[2].c1"&"b.b.f_buf_func[2].c2"&"b.b.f_buf_func[2].n1"&"b.b.f_buf_func[2].n2"&"b.b.f_buf_func[2].sr_B"->"b.b.f_buf_func[2]._y"-
"b.b.f_buf_func[2]._y"->"b.b.f_buf_func[2].y"-
~("b.b.f_buf_func[2]._y")->"b.b.f_buf_func[2].y"+
~"b.b.f_buf_func[3].c1"&~"b.b.f_buf_func[3].c2"|~"b.b.f_buf_func[3].pr_B"->"b.b.f_buf_func[3]._y"+
"b.b.f_buf_func[3].c1"&"b.b.f_buf_func[3].c2"&"b.b.f_buf_func[3].n1"&"b.b.f_buf_func[3].n2"&"b.b.f_buf_func[3].sr_B"->"b.b.f_buf_func[3]._y"-
"b.b.f_buf_func[3]._y"->"b.b.f_buf_func[3].y"-
~("b.b.f_buf_func[3]._y")->"b.b.f_buf_func[3].y"+
~"b.b.f_buf_func[4].c1"&~"b.b.f_buf_func[4].c2"|~"b.b.f_buf_func[4].pr_B"->"b.b.f_buf_func[4]._y"+
"b.b.f_buf_func[4].c1"&"b.b.f_buf_func[4].c2"&"b.b.f_buf_func[4].n1"&"b.b.f_buf_func[4].n2"&"b.b.f_buf_func[4].sr_B"->"b.b.f_buf_func[4]._y"-
"b.b.f_buf_func[4]._y"->"b.b.f_buf_func[4].y"-
~("b.b.f_buf_func[4]._y")->"b.b.f_buf_func[4].y"+
= "b.b._en_X_t[0]" "b.b.en_buf_t.out[0]"
= "b.b._en_X_t[1]" "b.b.en_buf_t.out[1]"
= "b.b._en_X_t[2]" "b.b.en_buf_t.out[2]"
= "b.b._en_X_t[3]" "b.b.en_buf_t.out[3]"
= "b.b._en_X_t[4]" "b.b.en_buf_t.out[4]"
= "b.b._en_X_t[0]" "b.b.t_buf_func[4].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[3].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[2].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[1].c1"
= "b.b._en_X_t[0]" "b.b.t_buf_func[0].c1"
= "b.b._en_X_t[0]" "b.b._en_X_t[4]"
= "b.b._en_X_t[0]" "b.b._en_X_t[3]"
= "b.b._en_X_t[0]" "b.b._en_X_t[2]"
= "b.b._en_X_t[0]" "b.b._en_X_t[1]"
= "Vdd" "b.b.supply.vdd"
= "GND" "b.b.supply.vss"
= "b._reset_B" "b.b.reset_B"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.out.v" "b.b.out.v"
= "b.out.a" "b.b.out.a"
= "b.out.d.d[0].f" "b.b.out.d.d[0].f"
= "b.out.d.d[0].t" "b.b.out.d.d[0].t"
= "b.out.d.d[0].d[0]" "b.b.out.d.d[0].d[0]"
= "b.out.d.d[0].d[1]" "b.b.out.d.d[0].d[1]"
= "b.out.d.d[1].f" "b.b.out.d.d[1].f"
= "b.out.d.d[1].t" "b.b.out.d.d[1].t"
= "b.out.d.d[1].d[0]" "b.b.out.d.d[1].d[0]"
= "b.out.d.d[1].d[1]" "b.b.out.d.d[1].d[1]"
= "b.out.d.d[2].f" "b.b.out.d.d[2].f"
= "b.out.d.d[2].t" "b.b.out.d.d[2].t"
= "b.out.d.d[2].d[0]" "b.b.out.d.d[2].d[0]"
= "b.out.d.d[2].d[1]" "b.b.out.d.d[2].d[1]"
= "b.out.d.d[3].f" "b.b.out.d.d[3].f"
= "b.out.d.d[3].t" "b.b.out.d.d[3].t"
= "b.out.d.d[3].d[0]" "b.b.out.d.d[3].d[0]"
= "b.out.d.d[3].d[1]" "b.b.out.d.d[3].d[1]"
= "b.out.d.d[4].f" "b.b.out.d.d[4].f"
= "b.out.d.d[4].t" "b.b.out.d.d[4].t"
= "b.out.d.d[4].d[0]" "b.b.out.d.d[4].d[0]"
= "b.out.d.d[4].d[1]" "b.b.out.d.d[4].d[1]"
= "b.out.d.d[4].d[0]" "b.out.d.d[4].f"
= "b.out.d.d[4].d[1]" "b.out.d.d[4].t"
= "b.out.d.d[3].d[0]" "b.out.d.d[3].f"
= "b.out.d.d[3].d[1]" "b.out.d.d[3].t"
= "b.out.d.d[2].d[0]" "b.out.d.d[2].f"
= "b.out.d.d[2].d[1]" "b.out.d.d[2].t"
= "b.out.d.d[1].d[0]" "b.out.d.d[1].f"
= "b.out.d.d[1].d[1]" "b.out.d.d[1].t"
= "b.out.d.d[0].d[0]" "b.out.d.d[0].f"
= "b.out.d.d[0].d[1]" "b.out.d.d[0].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.v" "b.b.in.v"
= "b.in.a" "b.b.in.a"
= "b.in.d.d[0].f" "b.b.in.d.d[0].f"
= "b.in.d.d[0].t" "b.b.in.d.d[0].t"
= "b.in.d.d[0].d[0]" "b.b.in.d.d[0].d[0]"
= "b.in.d.d[0].d[1]" "b.b.in.d.d[0].d[1]"
= "b.in.d.d[1].f" "b.b.in.d.d[1].f"
= "b.in.d.d[1].t" "b.b.in.d.d[1].t"
= "b.in.d.d[1].d[0]" "b.b.in.d.d[1].d[0]"
= "b.in.d.d[1].d[1]" "b.b.in.d.d[1].d[1]"
= "b.in.d.d[2].f" "b.b.in.d.d[2].f"
= "b.in.d.d[2].t" "b.b.in.d.d[2].t"
= "b.in.d.d[2].d[0]" "b.b.in.d.d[2].d[0]"
= "b.in.d.d[2].d[1]" "b.b.in.d.d[2].d[1]"
= "b.in.d.d[3].f" "b.b.in.d.d[3].f"
= "b.in.d.d[3].t" "b.b.in.d.d[3].t"
= "b.in.d.d[3].d[0]" "b.b.in.d.d[3].d[0]"
= "b.in.d.d[3].d[1]" "b.b.in.d.d[3].d[1]"
= "b.in.d.d[4].f" "b.b.in.d.d[4].f"
= "b.in.d.d[4].t" "b.b.in.d.d[4].t"
= "b.in.d.d[4].d[0]" "b.b.in.d.d[4].d[0]"
= "b.in.d.d[4].d[1]" "b.b.in.d.d[4].d[1]"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"

47
test/unit_tests/buf_s_5/test.act
View File

@@ -1,47 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc buffer_s_5(avMx1of2<5> in; avMx1of2<5> out)
{
bool _reset_B;
prs {
Reset => _reset_B-
}
buffer_s<5> b(.in = in, .out = out);
b.supply.vdd = Vdd;
b.supply.vss = GND;
b.reset_B = _reset_B;
}
buffer_s_5 b;

66
test/unit_tests/buf_s_5/test.prsim
View File

@@ -1,66 +0,0 @@
watchall
set-qdi-channel-neutral "b.in" 5
set b.out.a 0
set b.out.v 0
# set b.in.a 1
# set b.in.v 1
set Reset 0
# Set output channel variables to all active (incorrect)
set b.out.d.d[0].t 1
set b.out.d.d[0].f 1
set b.out.d.d[1].t 1
set b.out.d.d[1].f 1
set b.out.d.d[2].t 1
set b.out.d.d[2].f 1
set b.out.d.d[3].t 1
set b.out.d.d[3].f 1
set b.out.d.d[4].t 1
set b.out.d.d[4].f 1
cycle
system "echo '[] set Reset 1'"
set Reset 1
cycle
system "echo '[] set Reset 0'"
set Reset 0
mode run
cycle
assert-qdi-channel-neutral "b.out" 5
system "echo '[] Reset finished, setting some inputs.'"
status X
set b.in.d.d[0].t 1
set b.in.d.d[1].t 1
set b.in.d.d[2].f 1
set b.in.d.d[3].f 1
cycle
system "echo '[] Setting final input'"
set b.in.d.d[4].t 1
cycle
system "echo '[] Receiving out val'"
set b.out.v 1
cycle
assert b.in.a 1
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 5
cycle
system "echo '[] Receiving out ack'"
set b.out.a 1
cycle
assert-qdi-channel-neutral "b.out" 5

685
test/unit_tests/buff.v
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@@ -1,685 +0,0 @@
//
// Verilog module for: BUF_X6<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
output y;
input a;
// -- signals ---
wire a;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
input in;
output \out[0] ;
// -- signals ---
reg \out[0] ;
wire in;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6 (.y(\out[0] ), .a(in));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
output y;
input c1;
input c2;
input c3;
input pr_B;
input sr_B;
// -- signals ---
wire pr_B;
wire c3;
wire c1;
wire sr_B;
wire c2;
reg _y;
reg y;
// --- instances
endmodule
//
// Verilog module for: BUF_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: INV_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_2C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
output y;
input c1;
input c2;
// -- signals ---
wire c2;
wire c1;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_3C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
output y;
input c1;
input c2;
input c3;
// -- signals ---
wire c1;
reg y;
reg _y;
wire c3;
wire c2;
// --- instances
endmodule
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[9] ;
wire \in[11] ;
reg \tmp[18] ;
reg \tmp[16] ;
reg \tmp[24] ;
wire \in[0] ;
reg \tmp[22] ;
reg out;
wire \in[7] ;
reg \tmp[23] ;
wire \in[4] ;
wire \in[3] ;
wire \in[12] ;
reg \tmp[20] ;
wire \in[2] ;
reg \tmp[19] ;
wire \in[14] ;
wire \in[6] ;
wire \in[10] ;
wire \in[5] ;
wire \in[8] ;
wire \in[13] ;
wire \in[1] ;
reg \tmp[21] ;
reg \tmp[17] ;
reg \tmp[15] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
endmodule
//
// Verilog module for: OR2_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
output y;
input a;
input b;
// -- signals ---
wire a;
wire b;
reg y;
reg _y;
// --- instances
endmodule
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
wire \in.d[2].d[1] ;
wire \in.d[14].d[1] ;
reg \ct.in[8] ;
wire \in.d[10].d[1] ;
wire \in.d[7].d[1] ;
reg \ct.in[14] ;
wire \in.d[3].d[0] ;
reg \ct.in[0] ;
wire \in.d[8].d[1] ;
wire \in.d[6].d[1] ;
reg out;
wire \in.d[14].d[0] ;
wire \in.d[6].d[0] ;
wire \in.d[10].d[0] ;
wire \in.d[5].d[1] ;
wire \in.d[7].d[0] ;
wire \in.d[3].d[1] ;
wire \in.d[2].d[0] ;
reg \ct.in[6] ;
reg \ct.in[4] ;
wire \in.d[5].d[0] ;
wire \in.d[1].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[5] ;
reg \ct.in[1] ;
wire \in.d[9].d[0] ;
wire \in.d[0].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[12] ;
wire \in.d[12].d[1] ;
wire \in.d[8].d[0] ;
reg \ct.in[2] ;
wire \in.d[13].d[0] ;
wire \in.d[4].d[0] ;
wire \in.d[12].d[0] ;
wire \in.d[11].d[0] ;
wire \in.d[13].d[1] ;
reg \ct.in[9] ;
reg \ct.in[3] ;
reg \ct.in[11] ;
wire \in.d[1].d[0] ;
reg \ct.in[7] ;
wire \in.d[11].d[1] ;
wire \in.d[9].d[1] ;
reg \ct.in[10] ;
reg \ct.in[13] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
output y;
input c1;
input p1;
// -- signals ---
wire c1;
wire p1;
reg y;
// --- instances
endmodule
//
// Verilog module for: BUF_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_2C1N_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
output y;
input c1;
input c2;
input n1;
input pr_B;
input sr_B;
// -- signals ---
reg y;
wire n1;
wire sr_B;
wire pr_B;
wire c2;
wire c1;
reg _y;
// --- instances
endmodule
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
wire \in.d.d[9].d[0] ;
reg _out_a_B;
reg \out.d.d[1].d[0] ;
wire \in.d.d[4].d[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[10].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[2].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[5].d[0] ;
wire \out.v ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[1].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
reg _reset_BX;
reg \in.v ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
reg \out.d.d[5].d[0] ;
reg \out.d.d[10].d[1] ;
reg \out.d.d[9].d[1] ;
reg \out.d.d[7].d[1] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[5].d[1] ;
reg _en;
reg \_out_a_BX_f[0] ;
reg \out.d.d[9].d[0] ;
wire \in.d.d[13].d[1] ;
reg \out.d.d[11].d[0] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[1].d[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[4].d[1] ;
reg _in_v;
reg \out.d.d[13].d[0] ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[2].d[1] ;
reg \in.a ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[3].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[11].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[10].d[0] ;
wire \out.a ;
reg \out.d.d[12].d[1] ;
wire reset_B;
wire \in.d.d[7].d[1] ;
wire \in.d.d[6].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
reg \_reset_BXX[0] ;
reg \out.d.d[4].d[0] ;
reg \out.d.d[13].d[1] ;
reg \_en_X_f[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf (.y(\in.v ), .a(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv (.y(_out_a_B), .a(\out.a ));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf (.y(_reset_BX), .a(reset_B));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[4].d[0] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[8].d[1] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[1].d[0] ;
reg _reset_B;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[2].d[1] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[5].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[10].d[0] ;
wire \in.d.d[3].d[1] ;
wire \in.d.d[11].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[2].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[2].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[4].d[1] ;
wire \in.d.d[1].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[1].d[1] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[0].d[1] ;
wire \out.v ;
wire \in.d.d[12].d[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[7].d[1] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[7].d[1] ;
wire \out.a ;
reg \in.a ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[10].d[1] ;
reg \out.d.d[12].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[1] ;
reg \in.v ;
wire \in.d.d[14].d[0] ;
reg \out.d.d[13].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[8].d[0] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[9].d[0] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[0].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
endmodule

417
test/unit_tests/buffer_register_7/run/prsim.out
View File

@@ -1,417 +0,0 @@
b.b.f_buf_func[3].n1 b.b.t_buf_func[1].n1 b.b.vc.OR2_tf[1]._y b.b.f_buf_func[5].n1 b.b.vc.ct.in[6] b.in.v b.b._flushB b.b.f_buf_func[1].n1 b.b.t_buf_func[3].n1 b.b.f_buf_func[6].n1 b.b.vc.OR2_tf[6]._y b.b.vc.ct.in[1] b.out_v b.b.f_buf_func[0].n1 b.b.f_buf_func[2].n1 b.b.t_buf_func[4].n1 b.b.vc.ct.C3Els[1]._y b.b.t_buf_func[2].n1 b.b.t_buf_func[6].n1 b.b.vc.OR2_tf[0]._y b.b.vc.ct.in[3] b.b.t_buf_func[0].n1 b.flush b.b._in_v b.b.vc.ct.in[4] b.b.f_buf_func[4].n1 b.b.vc.ct.in[5] b.b.vc.OR2_tf[2]._y b.b.vc.ct.tmp[8] b.b.vc.ct.tmp[9] b.b.vc.ct.C2Els[0]._y b.b.t_buf_func[5].n1 b.b.vc.OR2_tf[4]._y b.b.vc.ct.in[2] b.b.vc.ct.tmp[7] b.b.vc.OR2_tf[5]._y b.b.vc.ct.in[0] b.b.vc.OR2_tf[3]._y b.b.in_v_buf._y b.b.vc.ct.C3Els[0]._y b.b.vc.ct.C2Els[1]._y
74426 b.out_v : 0
74426 b.b.t_buf_func[6].n1 : 0
74426 b.b.f_buf_func[6].n1 : 0
74426 b.b.t_buf_func[5].n1 : 0
74426 b.b.f_buf_func[0].n1 : 0
74426 b.b.f_buf_func[5].n1 : 0
74426 b.b.t_buf_func[4].n1 : 0
74426 b.b.f_buf_func[2].n1 : 0
74426 b.b.f_buf_func[4].n1 : 0
74426 b.b.t_buf_func[3].n1 : 0
74426 b.b.t_buf_func[1].n1 : 0
74426 b.b.f_buf_func[3].n1 : 0
74426 b.b.t_buf_func[2].n1 : 0
74426 b.flush : 0
74426 b.b.f_buf_func[1].n1 : 0
74426 b.b.t_buf_func[0].n1 : 0
74444 b.b.vc.OR2_tf[0]._y : 1 [by b.b.t_buf_func[0].n1:=0]
74977 b.b.vc.OR2_tf[5]._y : 1 [by b.b.f_buf_func[5].n1:=0]
75380 b.b.vc.OR2_tf[3]._y : 1 [by b.b.f_buf_func[3].n1:=0]
75408 b.b.vc.OR2_tf[1]._y : 1 [by b.b.f_buf_func[1].n1:=0]
75497 b.b.vc.OR2_tf[4]._y : 1 [by b.b.f_buf_func[4].n1:=0]
75507 b.b.vc.OR2_tf[2]._y : 1 [by b.b.t_buf_func[2].n1:=0]
76009 b.b.vc.ct.in[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
78457 b.b.vc.ct.in[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
78980 b.b.vc.ct.in[5] : 0 [by b.b.vc.OR2_tf[5]._y:=1]
80257 b.b.vc.ct.in[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
96867 b.b.vc.OR2_tf[6]._y : 1 [by b.b.f_buf_func[6].n1:=0]
96992 b.b.vc.ct.in[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
97070 b.b.vc.ct.in[6] : 0 [by b.b.vc.OR2_tf[6]._y:=1]
97209 b.b.vc.ct.C3Els[0]._y : 1 [by b.b.vc.ct.in[6]:=0]
98846 b.b.vc.ct.C2Els[0]._y : 1 [by b.b.vc.ct.in[1]:=0]
98915 b.b.vc.ct.tmp[7] : 0 [by b.b.vc.ct.C2Els[0]._y:=1]
120281 b.b.vc.ct.in[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
120292 b.b.vc.ct.C2Els[1]._y : 1 [by b.b.vc.ct.in[3]:=0]
128896 b.b._flushB : 1 [by b.flush:=0]
133555 b.b.vc.ct.tmp[9] : 0 [by b.b.vc.ct.C3Els[0]._y:=1]
172078 b.b.vc.ct.tmp[8] : 0 [by b.b.vc.ct.C2Els[1]._y:=1]
172282 b.b.vc.ct.C3Els[1]._y : 1 [by b.b.vc.ct.tmp[8]:=0]
172297 b.b._in_v : 0 [by b.b.vc.ct.C3Els[1]._y:=1]
172298 b.b.in_v_buf._y : 1 [by b.b._in_v:=0]
172335 b.in.v : 0 [by b.b.in_v_buf._y:=1]
[] Set reset 0
172335 Reset : 0
173074 b._reset_B : 1 [by Reset:=0]
173186 b.b.reset_buf._y : 0 [by b._reset_B:=1]
173226 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
173483 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
173570 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]
220586 b.b._reset : 0 [by b._reset_B:=1]
[] Flushing data
220586 b.flush : 1
220880 b.b._flushB : 0 [by b.flush:=1]
220881 b.b.t_buf_func[0]._y : 1 [by b.b._flushB:=0]
221045 b.out.d[0].t : 0 [by b.b.t_buf_func[0]._y:=1]
221058 b.b.t_buf_func[5]._y : 1 [by b.b._flushB:=0]
221470 b.b.t_buf_func[4]._y : 1 [by b.b._flushB:=0]
221492 b.out.d[4].t : 0 [by b.b.t_buf_func[4]._y:=1]
221683 b.b.t_buf_func[6]._y : 1 [by b.b._flushB:=0]
222089 b.b.t_buf_func[3]._y : 1 [by b.b._flushB:=0]
222530 b.out.d[6].t : 0 [by b.b.t_buf_func[6]._y:=1]
222686 b.b.t_buf_func[1]._y : 1 [by b.b._flushB:=0]
222819 b.out.d[1].t : 0 [by b.b.t_buf_func[1]._y:=1]
222887 b.b.t_buf_func[2]._y : 1 [by b.b._flushB:=0]
223253 b.out.d[5].t : 0 [by b.b.t_buf_func[5]._y:=1]
238549 b.out.d[2].t : 0 [by b.b.t_buf_func[2]._y:=1]
252217 b.out.d[3].t : 0 [by b.b.t_buf_func[3]._y:=1]
252217 b.flush : 0
252576 b.b._flushB : 1 [by b.flush:=0]
[] Sending in a 0
252576 b.b.f_buf_func[0].n1 : 1
252576 b.b.f_buf_func[6].n1 : 1
252576 b.b.f_buf_func[2].n1 : 1
252576 b.b.f_buf_func[5].n1 : 1
252576 b.b.f_buf_func[1].n1 : 1
252576 b.b.f_buf_func[4].n1 : 1
252576 b.b.f_buf_func[3].n1 : 1
252583 b.b.vc.OR2_tf[1]._y : 0 [by b.b.f_buf_func[1].n1:=1]
252583 b.b.vc.OR2_tf[6]._y : 0 [by b.b.f_buf_func[6].n1:=1]
252595 b.b.vc.ct.in[6] : 1 [by b.b.vc.OR2_tf[6]._y:=0]
252606 b.b.f_buf_func[6]._y : 0 [by b.b.f_buf_func[6].n1:=1]
252654 b.b.f_buf_func[4]._y : 0 [by b.b.f_buf_func[4].n1:=1]
252666 b.out.d[4].f : 1 [by b.b.f_buf_func[4]._y:=0]
252667 b.b.vc.OR2_tf[5]._y : 0 [by b.b.f_buf_func[5].n1:=1]
252682 b.b.vc.OR2_tf[4]._y : 0 [by b.b.f_buf_func[4].n1:=1]
252797 b.b.f_buf_func[0]._y : 0 [by b.b.f_buf_func[0].n1:=1]
252851 b.b.vc.OR2_tf[3]._y : 0 [by b.b.f_buf_func[3].n1:=1]
253010 b.out.d[6].f : 1 [by b.b.f_buf_func[6]._y:=0]
253038 b.b.vc.ct.in[1] : 1 [by b.b.vc.OR2_tf[1]._y:=0]
254765 b.b.f_buf_func[5]._y : 0 [by b.b.f_buf_func[5].n1:=1]
254767 b.out.d[5].f : 1 [by b.b.f_buf_func[5]._y:=0]
255363 b.b.f_buf_func[1]._y : 0 [by b.b.f_buf_func[1].n1:=1]
255696 b.out.d[0].f : 1 [by b.b.f_buf_func[0]._y:=0]
256958 b.b.vc.ct.in[4] : 1 [by b.b.vc.OR2_tf[4]._y:=0]
257146 b.b.vc.ct.in[3] : 1 [by b.b.vc.OR2_tf[3]._y:=0]
258583 b.b.vc.ct.in[5] : 1 [by b.b.vc.OR2_tf[5]._y:=0]
259289 b.b.vc.OR2_tf[2]._y : 0 [by b.b.f_buf_func[2].n1:=1]
259832 b.b.vc.ct.C3Els[0]._y : 0 [by b.b.vc.ct.in[5]:=1]
259898 b.out.d[1].f : 1 [by b.b.f_buf_func[1]._y:=0]
259998 b.b.vc.ct.tmp[9] : 1 [by b.b.vc.ct.C3Els[0]._y:=0]
262788 b.b.vc.ct.in[2] : 1 [by b.b.vc.OR2_tf[2]._y:=0]
262863 b.b.vc.ct.C2Els[1]._y : 0 [by b.b.vc.ct.in[2]:=1]
263208 b.b.vc.ct.tmp[8] : 1 [by b.b.vc.ct.C2Els[1]._y:=0]
266692 b.b.vc.OR2_tf[0]._y : 0 [by b.b.f_buf_func[0].n1:=1]
266830 b.b.vc.ct.in[0] : 1 [by b.b.vc.OR2_tf[0]._y:=0]
271572 b.b.f_buf_func[3]._y : 0 [by b.b.f_buf_func[3].n1:=1]
271574 b.out.d[3].f : 1 [by b.b.f_buf_func[3]._y:=0]
272093 b.b.vc.ct.C2Els[0]._y : 0 [by b.b.vc.ct.in[0]:=1]
310037 b.b.f_buf_func[2]._y : 0 [by b.b.f_buf_func[2].n1:=1]
310038 b.out.d[2].f : 1 [by b.b.f_buf_func[2]._y:=0]
316010 b.b.vc.ct.tmp[7] : 1 [by b.b.vc.ct.C2Els[0]._y:=0]
316558 b.b.vc.ct.C3Els[1]._y : 0 [by b.b.vc.ct.tmp[7]:=1]
316569 b.b._in_v : 1 [by b.b.vc.ct.C3Els[1]._y:=0]
316939 b.b.in_v_buf._y : 0 [by b.b._in_v:=1]
317006 b.in.v : 1 [by b.b.in_v_buf._y:=0]
[] Sending in output valid
317006 b.out_v : 1
319647 b.b._en : 0 [by b.out_v:=1]
319663 b.in.a : 1 [by b.b._en:=0]
320175 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
322610 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
324209 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
351089 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
[] Removing input
351089 b.b.f_buf_func[0].n1 : 0
351089 b.b.f_buf_func[6].n1 : 0
351089 b.b.f_buf_func[2].n1 : 0
351089 b.b.f_buf_func[5].n1 : 0
351089 b.b.f_buf_func[1].n1 : 0
351089 b.b.f_buf_func[4].n1 : 0
351089 b.b.f_buf_func[3].n1 : 0
351091 b.b.vc.OR2_tf[2]._y : 1 [by b.b.f_buf_func[2].n1:=0]
351092 b.b.vc.OR2_tf[1]._y : 1 [by b.b.f_buf_func[1].n1:=0]
351118 b.b.vc.OR2_tf[4]._y : 1 [by b.b.f_buf_func[4].n1:=0]
351162 b.b.vc.ct.in[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
351245 b.b.vc.ct.in[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
351406 b.b.vc.OR2_tf[3]._y : 1 [by b.b.f_buf_func[3].n1:=0]
352692 b.b.vc.ct.in[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
354167 b.b.vc.ct.in[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
364130 b.b.vc.OR2_tf[6]._y : 1 [by b.b.f_buf_func[6].n1:=0]
364131 b.b.vc.ct.in[6] : 0 [by b.b.vc.OR2_tf[6]._y:=1]
367850 b.b.vc.ct.C2Els[1]._y : 1 [by b.b.vc.ct.in[3]:=0]
368067 b.b.vc.ct.tmp[8] : 0 [by b.b.vc.ct.C2Els[1]._y:=1]
375014 b.b.vc.OR2_tf[0]._y : 1 [by b.b.f_buf_func[0].n1:=0]
375036 b.b.vc.ct.in[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
375037 b.b.vc.ct.C2Els[0]._y : 1 [by b.b.vc.ct.in[0]:=0]
376618 b.b.vc.ct.tmp[7] : 0 [by b.b.vc.ct.C2Els[0]._y:=1]
412047 b.b.vc.OR2_tf[5]._y : 1 [by b.b.f_buf_func[5].n1:=0]
421392 b.b.vc.ct.in[5] : 0 [by b.b.vc.OR2_tf[5]._y:=1]
421551 b.b.vc.ct.C3Els[0]._y : 1 [by b.b.vc.ct.in[5]:=0]
441227 b.b.vc.ct.tmp[9] : 0 [by b.b.vc.ct.C3Els[0]._y:=1]
442514 b.b.vc.ct.C3Els[1]._y : 1 [by b.b.vc.ct.tmp[9]:=0]
444746 b.b._in_v : 0 [by b.b.vc.ct.C3Els[1]._y:=1]
444891 b.b.in_v_buf._y : 1 [by b.b._in_v:=0]
447723 b.in.v : 0 [by b.b.in_v_buf._y:=1]
454077 b.b._en : 1 [by b.in.v:=0]
454078 b.in.a : 0 [by b.b._en:=1]
454239 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
461608 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
493361 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
493375 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
[] Flushing data
493375 b.flush : 1
493382 b.b._flushB : 0 [by b.flush:=1]
493383 b.b.f_buf_func[2]._y : 1 [by b.b._flushB:=0]
493383 b.b.f_buf_func[3]._y : 1 [by b.b._flushB:=0]
493383 b.b.f_buf_func[4]._y : 1 [by b.b._flushB:=0]
493384 b.out.d[2].f : 0 [by b.b.f_buf_func[2]._y:=1]
493542 b.b.f_buf_func[0]._y : 1 [by b.b._flushB:=0]
493543 b.out.d[0].f : 0 [by b.b.f_buf_func[0]._y:=1]
493569 b.b.f_buf_func[6]._y : 1 [by b.b._flushB:=0]
494422 b.out.d[6].f : 0 [by b.b.f_buf_func[6]._y:=1]
495625 b.b.f_buf_func[5]._y : 1 [by b.b._flushB:=0]
495630 b.out.d[5].f : 0 [by b.b.f_buf_func[5]._y:=1]
497565 b.out.d[3].f : 0 [by b.b.f_buf_func[3]._y:=1]
514939 b.b.f_buf_func[1]._y : 1 [by b.b._flushB:=0]
515830 b.out.d[1].f : 0 [by b.b.f_buf_func[1]._y:=1]
528165 b.out.d[4].f : 0 [by b.b.f_buf_func[4]._y:=1]
528165 b.out_v : 0
528165 b.flush : 0
528166 b.b._flushB : 1 [by b.flush:=0]
[] Sending in a 127
528166 b.b.t_buf_func[0].n1 : 1
528166 b.b.t_buf_func[6].n1 : 1
528166 b.b.t_buf_func[2].n1 : 1
528166 b.b.t_buf_func[5].n1 : 1
528166 b.b.t_buf_func[1].n1 : 1
528166 b.b.t_buf_func[4].n1 : 1
528166 b.b.t_buf_func[3].n1 : 1
528167 b.b.vc.OR2_tf[5]._y : 0 [by b.b.t_buf_func[5].n1:=1]
528169 b.b.t_buf_func[6]._y : 0 [by b.b.t_buf_func[6].n1:=1]
528174 b.b.vc.OR2_tf[3]._y : 0 [by b.b.t_buf_func[3].n1:=1]
528178 b.b.vc.ct.in[3] : 1 [by b.b.vc.OR2_tf[3]._y:=0]
528183 b.b.vc.OR2_tf[0]._y : 0 [by b.b.t_buf_func[0].n1:=1]
528200 b.b.t_buf_func[3]._y : 0 [by b.b.t_buf_func[3].n1:=1]
528208 b.b.t_buf_func[5]._y : 0 [by b.b.t_buf_func[5].n1:=1]
528261 b.b.vc.OR2_tf[4]._y : 0 [by b.b.t_buf_func[4].n1:=1]
528501 b.b.t_buf_func[4]._y : 0 [by b.b.t_buf_func[4].n1:=1]
528549 b.out.d[4].t : 1 [by b.b.t_buf_func[4]._y:=0]
529087 b.out.d[6].t : 1 [by b.b.t_buf_func[6]._y:=0]
529107 b.b.vc.OR2_tf[2]._y : 0 [by b.b.t_buf_func[2].n1:=1]
529110 b.b.vc.ct.in[2] : 1 [by b.b.vc.OR2_tf[2]._y:=0]
529288 b.b.vc.ct.C2Els[1]._y : 0 [by b.b.vc.ct.in[2]:=1]
530598 b.out.d[3].t : 1 [by b.b.t_buf_func[3]._y:=0]
530739 b.b.t_buf_func[0]._y : 0 [by b.b.t_buf_func[0].n1:=1]
530983 b.b.vc.OR2_tf[1]._y : 0 [by b.b.t_buf_func[1].n1:=1]
531423 b.out.d[5].t : 1 [by b.b.t_buf_func[5]._y:=0]
536527 b.b.vc.OR2_tf[6]._y : 0 [by b.b.t_buf_func[6].n1:=1]
536934 b.b.vc.ct.in[1] : 1 [by b.b.vc.OR2_tf[1]._y:=0]
541899 b.b.t_buf_func[1]._y : 0 [by b.b.t_buf_func[1].n1:=1]
542054 b.b.vc.ct.in[5] : 1 [by b.b.vc.OR2_tf[5]._y:=0]
542638 b.out.d[0].t : 1 [by b.b.t_buf_func[0]._y:=0]
542726 b.out.d[1].t : 1 [by b.b.t_buf_func[1]._y:=0]
550265 b.b.vc.ct.tmp[8] : 1 [by b.b.vc.ct.C2Els[1]._y:=0]
574561 b.b.vc.ct.in[0] : 1 [by b.b.vc.OR2_tf[0]._y:=0]
574734 b.b.vc.ct.C2Els[0]._y : 0 [by b.b.vc.ct.in[0]:=1]
574918 b.b.vc.ct.tmp[7] : 1 [by b.b.vc.ct.C2Els[0]._y:=0]
575380 b.b.vc.ct.in[4] : 1 [by b.b.vc.OR2_tf[4]._y:=0]
576012 b.b.vc.ct.in[6] : 1 [by b.b.vc.OR2_tf[6]._y:=0]
576013 b.b.vc.ct.C3Els[0]._y : 0 [by b.b.vc.ct.in[6]:=1]
576086 b.b.vc.ct.tmp[9] : 1 [by b.b.vc.ct.C3Els[0]._y:=0]
576090 b.b.vc.ct.C3Els[1]._y : 0 [by b.b.vc.ct.tmp[9]:=1]
587128 b.b.t_buf_func[2]._y : 0 [by b.b.t_buf_func[2].n1:=1]
587224 b.out.d[2].t : 1 [by b.b.t_buf_func[2]._y:=0]
613378 b.b._in_v : 1 [by b.b.vc.ct.C3Els[1]._y:=0]
613514 b.b.in_v_buf._y : 0 [by b.b._in_v:=1]
613515 b.in.v : 1 [by b.b.in_v_buf._y:=0]
[] Sending in output valid
613515 b.out_v : 1
632561 b.b._en : 0 [by b.out_v:=1]
632573 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
632802 b.in.a : 1 [by b.b._en:=0]
636473 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
636520 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
637549 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
[] Removing input
637549 b.b.t_buf_func[0].n1 : 0
637549 b.b.t_buf_func[6].n1 : 0
637549 b.b.t_buf_func[2].n1 : 0
637549 b.b.t_buf_func[5].n1 : 0
637549 b.b.t_buf_func[1].n1 : 0
637549 b.b.t_buf_func[4].n1 : 0
637549 b.b.t_buf_func[3].n1 : 0
637550 b.b.vc.OR2_tf[0]._y : 1 [by b.b.t_buf_func[0].n1:=0]
637550 b.b.vc.OR2_tf[3]._y : 1 [by b.b.t_buf_func[3].n1:=0]
637550 b.b.vc.OR2_tf[5]._y : 1 [by b.b.t_buf_func[5].n1:=0]
637563 b.b.vc.ct.in[5] : 0 [by b.b.vc.OR2_tf[5]._y:=1]
637586 b.b.vc.OR2_tf[1]._y : 1 [by b.b.t_buf_func[1].n1:=0]
637605 b.b.vc.OR2_tf[6]._y : 1 [by b.b.t_buf_func[6].n1:=0]
637962 b.b.vc.ct.in[6] : 0 [by b.b.vc.OR2_tf[6]._y:=1]
639242 b.b.vc.ct.in[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
641114 b.b.vc.ct.in[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
654570 b.b.vc.ct.in[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
654595 b.b.vc.ct.C2Els[0]._y : 1 [by b.b.vc.ct.in[1]:=0]
654616 b.b.vc.ct.tmp[7] : 0 [by b.b.vc.ct.C2Els[0]._y:=1]
660924 b.b.vc.OR2_tf[4]._y : 1 [by b.b.t_buf_func[4].n1:=0]
660925 b.b.vc.ct.in[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
670573 b.b.vc.ct.C3Els[0]._y : 1 [by b.b.vc.ct.in[4]:=0]
670574 b.b.vc.ct.tmp[9] : 0 [by b.b.vc.ct.C3Els[0]._y:=1]
682555 b.b.vc.OR2_tf[2]._y : 1 [by b.b.t_buf_func[2].n1:=0]
682556 b.b.vc.ct.in[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
682717 b.b.vc.ct.C2Els[1]._y : 1 [by b.b.vc.ct.in[2]:=0]
683754 b.b.vc.ct.tmp[8] : 0 [by b.b.vc.ct.C2Els[1]._y:=1]
683759 b.b.vc.ct.C3Els[1]._y : 1 [by b.b.vc.ct.tmp[8]:=0]
684340 b.b._in_v : 0 [by b.b.vc.ct.C3Els[1]._y:=1]
684748 b.b.in_v_buf._y : 1 [by b.b._in_v:=0]
684759 b.in.v : 0 [by b.b.in_v_buf._y:=1]
685806 b.b._en : 1 [by b.in.v:=0]
685810 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
685820 b.in.a : 0 [by b.b._en:=1]
685824 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
685914 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
717268 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
[] Flushing data
717268 b.flush : 1
718472 b.b._flushB : 0 [by b.flush:=1]
718483 b.b.t_buf_func[6]._y : 1 [by b.b._flushB:=0]
718486 b.out.d[6].t : 0 [by b.b.t_buf_func[6]._y:=1]
718542 b.b.t_buf_func[4]._y : 1 [by b.b._flushB:=0]
718596 b.out.d[4].t : 0 [by b.b.t_buf_func[4]._y:=1]
718700 b.b.t_buf_func[1]._y : 1 [by b.b._flushB:=0]
719315 b.b.t_buf_func[2]._y : 1 [by b.b._flushB:=0]
719848 b.out.d[1].t : 0 [by b.b.t_buf_func[1]._y:=1]
719931 b.b.t_buf_func[3]._y : 1 [by b.b._flushB:=0]
720476 b.out.d[2].t : 0 [by b.b.t_buf_func[2]._y:=1]
726927 b.b.t_buf_func[0]._y : 1 [by b.b._flushB:=0]
727008 b.out.d[0].t : 0 [by b.b.t_buf_func[0]._y:=1]
728583 b.out.d[3].t : 0 [by b.b.t_buf_func[3]._y:=1]
768894 b.b.t_buf_func[5]._y : 1 [by b.b._flushB:=0]
779971 b.out.d[5].t : 0 [by b.b.t_buf_func[5]._y:=1]
779971 b.out_v : 0
779971 b.flush : 0
797954 b.b._flushB : 1 [by b.flush:=0]
[] Sending in a 56
797954 b.b.f_buf_func[0].n1 : 1
797954 b.b.f_buf_func[6].n1 : 1
797954 b.b.f_buf_func[2].n1 : 1
797954 b.b.t_buf_func[5].n1 : 1
797954 b.b.f_buf_func[1].n1 : 1
797954 b.b.t_buf_func[4].n1 : 1
797954 b.b.t_buf_func[3].n1 : 1
797961 b.b.t_buf_func[4]._y : 0 [by b.b.t_buf_func[4].n1:=1]
797963 b.out.d[4].t : 1 [by b.b.t_buf_func[4]._y:=0]
797999 b.b.f_buf_func[2]._y : 0 [by b.b.f_buf_func[2].n1:=1]
798006 b.b.vc.OR2_tf[4]._y : 0 [by b.b.t_buf_func[4].n1:=1]
798046 b.b.vc.OR2_tf[0]._y : 0 [by b.b.f_buf_func[0].n1:=1]
798047 b.b.vc.ct.in[0] : 1 [by b.b.vc.OR2_tf[0]._y:=0]
798139 b.b.vc.ct.in[4] : 1 [by b.b.vc.OR2_tf[4]._y:=0]
798353 b.out.d[2].f : 1 [by b.b.f_buf_func[2]._y:=0]
798479 b.b.vc.OR2_tf[1]._y : 0 [by b.b.f_buf_func[1].n1:=1]
798483 b.b.vc.ct.in[1] : 1 [by b.b.vc.OR2_tf[1]._y:=0]
798567 b.b.f_buf_func[6]._y : 0 [by b.b.f_buf_func[6].n1:=1]
798854 b.b.f_buf_func[1]._y : 0 [by b.b.f_buf_func[1].n1:=1]
798855 b.out.d[1].f : 1 [by b.b.f_buf_func[1]._y:=0]
798951 b.b.vc.OR2_tf[5]._y : 0 [by b.b.t_buf_func[5].n1:=1]
799029 b.b.vc.ct.C2Els[0]._y : 0 [by b.b.vc.ct.in[1]:=1]
799108 b.b.vc.ct.tmp[7] : 1 [by b.b.vc.ct.C2Els[0]._y:=0]
799603 b.b.t_buf_func[5]._y : 0 [by b.b.t_buf_func[5].n1:=1]
799698 b.b.vc.OR2_tf[6]._y : 0 [by b.b.f_buf_func[6].n1:=1]
799786 b.b.vc.ct.in[6] : 1 [by b.b.vc.OR2_tf[6]._y:=0]
802036 b.out.d[5].t : 1 [by b.b.t_buf_func[5]._y:=0]
804421 b.b.t_buf_func[3]._y : 0 [by b.b.t_buf_func[3].n1:=1]
806265 b.b.f_buf_func[0]._y : 0 [by b.b.f_buf_func[0].n1:=1]
811329 b.b.vc.ct.in[5] : 1 [by b.b.vc.OR2_tf[5]._y:=0]
811388 b.b.vc.ct.C3Els[0]._y : 0 [by b.b.vc.ct.in[5]:=1]
811418 b.b.vc.ct.tmp[9] : 1 [by b.b.vc.ct.C3Els[0]._y:=0]
811976 b.b.vc.OR2_tf[2]._y : 0 [by b.b.f_buf_func[2].n1:=1]
812203 b.out.d[3].t : 1 [by b.b.t_buf_func[3]._y:=0]
813443 b.b.vc.ct.in[2] : 1 [by b.b.vc.OR2_tf[2]._y:=0]
813566 b.b.vc.OR2_tf[3]._y : 0 [by b.b.t_buf_func[3].n1:=1]
834592 b.out.d[0].f : 1 [by b.b.f_buf_func[0]._y:=0]
844130 b.out.d[6].f : 1 [by b.b.f_buf_func[6]._y:=0]
873070 b.b.vc.ct.in[3] : 1 [by b.b.vc.OR2_tf[3]._y:=0]
892454 b.b.vc.ct.C2Els[1]._y : 0 [by b.b.vc.ct.in[3]:=1]
893139 b.b.vc.ct.tmp[8] : 1 [by b.b.vc.ct.C2Els[1]._y:=0]
909854 b.b.vc.ct.C3Els[1]._y : 0 [by b.b.vc.ct.tmp[8]:=1]
909981 b.b._in_v : 1 [by b.b.vc.ct.C3Els[1]._y:=0]
910150 b.b.in_v_buf._y : 0 [by b.b._in_v:=1]
910193 b.in.v : 1 [by b.b.in_v_buf._y:=0]
[] Sending in output valid
910193 b.out_v : 1
910205 b.b._en : 0 [by b.out_v:=1]
910208 b.b.en_buf_t.buf2._y : 1 [by b.b._en:=0]
910246 b.b._en_X_t[0] : 0 [by b.b.en_buf_t.buf2._y:=1]
910438 b.b.en_buf_f.buf2._y : 1 [by b.b._en:=0]
910439 b.b._en_X_f[0] : 0 [by b.b.en_buf_f.buf2._y:=1]
911484 b.in.a : 1 [by b.b._en:=0]
[] Removing input
911484 b.b.f_buf_func[0].n1 : 0
911484 b.b.f_buf_func[6].n1 : 0
911484 b.b.f_buf_func[2].n1 : 0
911484 b.b.t_buf_func[5].n1 : 0
911484 b.b.f_buf_func[1].n1 : 0
911484 b.b.t_buf_func[4].n1 : 0
911484 b.b.t_buf_func[3].n1 : 0
911485 b.b.vc.OR2_tf[1]._y : 1 [by b.b.f_buf_func[1].n1:=0]
911486 b.b.vc.OR2_tf[3]._y : 1 [by b.b.t_buf_func[3].n1:=0]
911486 b.b.vc.OR2_tf[5]._y : 1 [by b.b.t_buf_func[5].n1:=0]
911503 b.b.vc.ct.in[1] : 0 [by b.b.vc.OR2_tf[1]._y:=1]
911576 b.b.vc.OR2_tf[6]._y : 1 [by b.b.f_buf_func[6].n1:=0]
911584 b.b.vc.ct.in[6] : 0 [by b.b.vc.OR2_tf[6]._y:=1]
911605 b.b.vc.ct.in[3] : 0 [by b.b.vc.OR2_tf[3]._y:=1]
912985 b.b.vc.OR2_tf[4]._y : 1 [by b.b.t_buf_func[4].n1:=0]
913039 b.b.vc.ct.in[4] : 0 [by b.b.vc.OR2_tf[4]._y:=1]
914211 b.b.vc.OR2_tf[2]._y : 1 [by b.b.f_buf_func[2].n1:=0]
917206 b.b.vc.ct.in[5] : 0 [by b.b.vc.OR2_tf[5]._y:=1]
917211 b.b.vc.ct.C3Els[0]._y : 1 [by b.b.vc.ct.in[5]:=0]
918278 b.b.vc.ct.tmp[9] : 0 [by b.b.vc.ct.C3Els[0]._y:=1]
924236 b.b.vc.OR2_tf[0]._y : 1 [by b.b.f_buf_func[0].n1:=0]
924237 b.b.vc.ct.in[0] : 0 [by b.b.vc.OR2_tf[0]._y:=1]
924375 b.b.vc.ct.C2Els[0]._y : 1 [by b.b.vc.ct.in[0]:=0]
924376 b.b.vc.ct.tmp[7] : 0 [by b.b.vc.ct.C2Els[0]._y:=1]
964749 b.b.vc.ct.in[2] : 0 [by b.b.vc.OR2_tf[2]._y:=1]
964813 b.b.vc.ct.C2Els[1]._y : 1 [by b.b.vc.ct.in[2]:=0]
964936 b.b.vc.ct.tmp[8] : 0 [by b.b.vc.ct.C2Els[1]._y:=1]
964938 b.b.vc.ct.C3Els[1]._y : 1 [by b.b.vc.ct.tmp[8]:=0]
964975 b.b._in_v : 0 [by b.b.vc.ct.C3Els[1]._y:=1]
965118 b.b.in_v_buf._y : 1 [by b.b._in_v:=0]
965169 b.in.v : 0 [by b.b.in_v_buf._y:=1]
965611 b.b._en : 1 [by b.in.v:=0]
965612 b.b.en_buf_f.buf2._y : 0 [by b.b._en:=1]
965620 b.b.en_buf_t.buf2._y : 0 [by b.b._en:=1]
965622 b.in.a : 0 [by b.b._en:=1]
965637 b.b._en_X_f[0] : 1 [by b.b.en_buf_f.buf2._y:=0]
975873 b.b._en_X_t[0] : 1 [by b.b.en_buf_t.buf2._y:=0]
[] Resetting
975873 Reset : 1
979394 b._reset_B : 0 [by Reset:=1]
979539 b.b.reset_buf._y : 1 [by b._reset_B:=0]
979769 b.b._reset_BX : 0 [by b.b.reset_buf._y:=1]
980460 b.b.reset_bufarray.buf2._y : 1 [by b.b._reset_BX:=0]
980474 b.b._reset_BXX[0] : 0 [by b.b.reset_bufarray.buf2._y:=1]
980485 b.b.f_buf_func[6]._y : 1 [by b.b._reset_BXX[0]:=0]
980486 b.out.d[6].f : 0 [by b.b.f_buf_func[6]._y:=1]
982017 b.b.f_buf_func[0]._y : 1 [by b.b._reset_BXX[0]:=0]
982018 b.out.d[0].f : 0 [by b.b.f_buf_func[0]._y:=1]
982085 b.b.f_buf_func[1]._y : 1 [by b.b._reset_BXX[0]:=0]
988586 b.out.d[1].f : 0 [by b.b.f_buf_func[1]._y:=1]
995562 b.b._reset : 1 [by b._reset_B:=0]
995563 b.b.t_buf_func[6]._y : 0 [by b.b._reset:=1]
995580 b.out.d[6].t : 1 [by b.b.t_buf_func[6]._y:=0]
995694 b.b.t_buf_func[2]._y : 0 [by b.b._reset:=1]
995846 b.out.d[2].t : 1 [by b.b.t_buf_func[2]._y:=0]
996201 b.b.t_buf_func[0]._y : 0 [by b.b._reset:=1]
997355 b.b.t_buf_func[1]._y : 0 [by b.b._reset:=1]
997358 b.out.d[1].t : 1 [by b.b.t_buf_func[1]._y:=0]
997986 b.b.f_buf_func[2]._y : 1 [by b.b._reset_BXX[0]:=0]
998410 b.out.d[2].f : 0 [by b.b.f_buf_func[2]._y:=1]
999184 b.out.d[0].t : 1 [by b.b.t_buf_func[0]._y:=0]
999184 Reset : 0
999190 b._reset_B : 1 [by Reset:=0]
1001651 b.b._reset : 0 [by b._reset_B:=1]
1001778 b.b.reset_buf._y : 0 [by b._reset_B:=1]
1002608 b.b._reset_BX : 1 [by b.b.reset_buf._y:=0]
1025540 b.b.reset_bufarray.buf2._y : 0 [by b.b._reset_BX:=1]
1025542 b.b._reset_BXX[0] : 1 [by b.b.reset_bufarray.buf2._y:=0]

746
test/unit_tests/buffer_register_7/run/test.prs
View File

@@ -1,746 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"b._reset_B"-
~("Reset")->"b._reset_B"+
= "b.b._en_X_f[0]" "b.b.en_buf_f.out[0]"
= "b.b._en_X_f[1]" "b.b.en_buf_f.out[1]"
= "b.b._en_X_f[2]" "b.b.en_buf_f.out[2]"
= "b.b._en_X_f[3]" "b.b.en_buf_f.out[3]"
= "b.b._en_X_f[4]" "b.b.en_buf_f.out[4]"
= "b.b._en_X_f[5]" "b.b.en_buf_f.out[5]"
= "b.b._en_X_f[6]" "b.b.en_buf_f.out[6]"
= "b.b._en_X_f[0]" "b.b.f_buf_func[6].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[5].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[4].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[3].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[2].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[1].n2"
= "b.b._en_X_f[0]" "b.b.f_buf_func[0].n2"
= "b.b._en_X_f[0]" "b.b._en_X_f[6]"
= "b.b._en_X_f[0]" "b.b._en_X_f[5]"
= "b.b._en_X_f[0]" "b.b._en_X_f[4]"
= "b.b._en_X_f[0]" "b.b._en_X_f[3]"
= "b.b._en_X_f[0]" "b.b._en_X_f[2]"
= "b.b._en_X_f[0]" "b.b._en_X_f[1]"
"b.b.in_v_buf.a"->"b.b.in_v_buf._y"-
~("b.b.in_v_buf.a")->"b.b.in_v_buf._y"+
"b.b.in_v_buf._y"->"b.b.in_v_buf.y"-
~("b.b.in_v_buf._y")->"b.b.in_v_buf.y"+
"b.b.reset_bufarray.buf2.a"->"b.b.reset_bufarray.buf2._y"-
~("b.b.reset_bufarray.buf2.a")->"b.b.reset_bufarray.buf2._y"+
"b.b.reset_bufarray.buf2._y"->"b.b.reset_bufarray.buf2.y"-
~("b.b.reset_bufarray.buf2._y")->"b.b.reset_bufarray.buf2.y"+
= "b.b.reset_bufarray.supply.vdd" "b.b.reset_bufarray.buf2.vdd"
= "b.b.reset_bufarray.supply.vss" "b.b.reset_bufarray.buf2.vss"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[6]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[5]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[4]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[3]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[2]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.out[1]"
= "b.b.reset_bufarray.out[0]" "b.b.reset_bufarray.buf2.y"
= "b.b.reset_bufarray.in" "b.b.reset_bufarray.buf2.a"
= "b.b.flush" "b.b.flush_inv.a"
~"b.b.inack_ctl.c1"&~"b.b.inack_ctl.c2"|~"b.b.inack_ctl.pr_B"->"b.b.inack_ctl.y"+
"b.b.inack_ctl.c1"&"b.b.inack_ctl.c2"&"b.b.inack_ctl.n1"&"b.b.inack_ctl.sr_B"->"b.b.inack_ctl.y"-
~"b.b.vc.ct.C2Els[0].c1"&~"b.b.vc.ct.C2Els[0].c2"->"b.b.vc.ct.C2Els[0]._y"+
"b.b.vc.ct.C2Els[0].c1"&"b.b.vc.ct.C2Els[0].c2"->"b.b.vc.ct.C2Els[0]._y"-
"b.b.vc.ct.C2Els[0]._y"->"b.b.vc.ct.C2Els[0].y"-
~("b.b.vc.ct.C2Els[0]._y")->"b.b.vc.ct.C2Els[0].y"+
~"b.b.vc.ct.C2Els[1].c1"&~"b.b.vc.ct.C2Els[1].c2"->"b.b.vc.ct.C2Els[1]._y"+
"b.b.vc.ct.C2Els[1].c1"&"b.b.vc.ct.C2Els[1].c2"->"b.b.vc.ct.C2Els[1]._y"-
"b.b.vc.ct.C2Els[1]._y"->"b.b.vc.ct.C2Els[1].y"-
~("b.b.vc.ct.C2Els[1]._y")->"b.b.vc.ct.C2Els[1].y"+
~"b.b.vc.ct.C3Els[0].c1"&~"b.b.vc.ct.C3Els[0].c2"&~"b.b.vc.ct.C3Els[0].c3"->"b.b.vc.ct.C3Els[0]._y"+
"b.b.vc.ct.C3Els[0].c1"&"b.b.vc.ct.C3Els[0].c2"&"b.b.vc.ct.C3Els[0].c3"->"b.b.vc.ct.C3Els[0]._y"-
"b.b.vc.ct.C3Els[0]._y"->"b.b.vc.ct.C3Els[0].y"-
~("b.b.vc.ct.C3Els[0]._y")->"b.b.vc.ct.C3Els[0].y"+
~"b.b.vc.ct.C3Els[1].c1"&~"b.b.vc.ct.C3Els[1].c2"&~"b.b.vc.ct.C3Els[1].c3"->"b.b.vc.ct.C3Els[1]._y"+
"b.b.vc.ct.C3Els[1].c1"&"b.b.vc.ct.C3Els[1].c2"&"b.b.vc.ct.C3Els[1].c3"->"b.b.vc.ct.C3Els[1]._y"-
"b.b.vc.ct.C3Els[1]._y"->"b.b.vc.ct.C3Els[1].y"-
~("b.b.vc.ct.C3Els[1]._y")->"b.b.vc.ct.C3Els[1].y"+
= "b.b.vc.ct.tmp[7]" "b.b.vc.ct.C3Els[1].c1"
= "b.b.vc.ct.tmp[7]" "b.b.vc.ct.C2Els[0].y"
= "b.b.vc.ct.tmp[8]" "b.b.vc.ct.C3Els[1].c2"
= "b.b.vc.ct.tmp[8]" "b.b.vc.ct.C2Els[1].y"
= "b.b.vc.ct.tmp[9]" "b.b.vc.ct.C3Els[1].c3"
= "b.b.vc.ct.tmp[9]" "b.b.vc.ct.C3Els[0].y"
= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C3Els[1].vdd"
= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C3Els[0].vdd"
= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C2Els[1].vdd"
= "b.b.vc.ct.supply.vdd" "b.b.vc.ct.C2Els[0].vdd"
= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C3Els[1].vss"
= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C3Els[0].vss"
= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C2Els[1].vss"
= "b.b.vc.ct.supply.vss" "b.b.vc.ct.C2Els[0].vss"
= "b.b.vc.ct.in[0]" "b.b.vc.ct.C2Els[0].c1"
= "b.b.vc.ct.in[0]" "b.b.vc.ct.tmp[0]"
= "b.b.vc.ct.in[1]" "b.b.vc.ct.C2Els[0].c2"
= "b.b.vc.ct.in[1]" "b.b.vc.ct.tmp[1]"
= "b.b.vc.ct.in[2]" "b.b.vc.ct.C2Els[1].c1"
= "b.b.vc.ct.in[2]" "b.b.vc.ct.tmp[2]"
= "b.b.vc.ct.in[3]" "b.b.vc.ct.C2Els[1].c2"
= "b.b.vc.ct.in[3]" "b.b.vc.ct.tmp[3]"
= "b.b.vc.ct.in[4]" "b.b.vc.ct.C3Els[0].c1"
= "b.b.vc.ct.in[4]" "b.b.vc.ct.tmp[4]"
= "b.b.vc.ct.in[5]" "b.b.vc.ct.C3Els[0].c2"
= "b.b.vc.ct.in[5]" "b.b.vc.ct.tmp[5]"
= "b.b.vc.ct.in[6]" "b.b.vc.ct.C3Els[0].c3"
= "b.b.vc.ct.in[6]" "b.b.vc.ct.tmp[6]"
= "b.b.vc.ct.out" "b.b.vc.ct.C3Els[1].y"
= "b.b.vc.ct.out" "b.b.vc.ct.tmp[10]"
= "b.b.vc.ct.in[0]" "b.b.vc.OR2_tf[0].y"
= "b.b.vc.ct.in[1]" "b.b.vc.OR2_tf[1].y"
= "b.b.vc.ct.in[2]" "b.b.vc.OR2_tf[2].y"
= "b.b.vc.ct.in[3]" "b.b.vc.OR2_tf[3].y"
= "b.b.vc.ct.in[4]" "b.b.vc.OR2_tf[4].y"
= "b.b.vc.ct.in[5]" "b.b.vc.OR2_tf[5].y"
= "b.b.vc.ct.in[6]" "b.b.vc.OR2_tf[6].y"
"b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b"->"b.b.vc.OR2_tf[0]._y"-
~("b.b.vc.OR2_tf[0].a"|"b.b.vc.OR2_tf[0].b")->"b.b.vc.OR2_tf[0]._y"+
"b.b.vc.OR2_tf[0]._y"->"b.b.vc.OR2_tf[0].y"-
~("b.b.vc.OR2_tf[0]._y")->"b.b.vc.OR2_tf[0].y"+
"b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b"->"b.b.vc.OR2_tf[1]._y"-
~("b.b.vc.OR2_tf[1].a"|"b.b.vc.OR2_tf[1].b")->"b.b.vc.OR2_tf[1]._y"+
"b.b.vc.OR2_tf[1]._y"->"b.b.vc.OR2_tf[1].y"-
~("b.b.vc.OR2_tf[1]._y")->"b.b.vc.OR2_tf[1].y"+
"b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b"->"b.b.vc.OR2_tf[2]._y"-
~("b.b.vc.OR2_tf[2].a"|"b.b.vc.OR2_tf[2].b")->"b.b.vc.OR2_tf[2]._y"+
"b.b.vc.OR2_tf[2]._y"->"b.b.vc.OR2_tf[2].y"-
~("b.b.vc.OR2_tf[2]._y")->"b.b.vc.OR2_tf[2].y"+
"b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b"->"b.b.vc.OR2_tf[3]._y"-
~("b.b.vc.OR2_tf[3].a"|"b.b.vc.OR2_tf[3].b")->"b.b.vc.OR2_tf[3]._y"+
"b.b.vc.OR2_tf[3]._y"->"b.b.vc.OR2_tf[3].y"-
~("b.b.vc.OR2_tf[3]._y")->"b.b.vc.OR2_tf[3].y"+
"b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b"->"b.b.vc.OR2_tf[4]._y"-
~("b.b.vc.OR2_tf[4].a"|"b.b.vc.OR2_tf[4].b")->"b.b.vc.OR2_tf[4]._y"+
"b.b.vc.OR2_tf[4]._y"->"b.b.vc.OR2_tf[4].y"-
~("b.b.vc.OR2_tf[4]._y")->"b.b.vc.OR2_tf[4].y"+
"b.b.vc.OR2_tf[5].a"|"b.b.vc.OR2_tf[5].b"->"b.b.vc.OR2_tf[5]._y"-
~("b.b.vc.OR2_tf[5].a"|"b.b.vc.OR2_tf[5].b")->"b.b.vc.OR2_tf[5]._y"+
"b.b.vc.OR2_tf[5]._y"->"b.b.vc.OR2_tf[5].y"-
~("b.b.vc.OR2_tf[5]._y")->"b.b.vc.OR2_tf[5].y"+
"b.b.vc.OR2_tf[6].a"|"b.b.vc.OR2_tf[6].b"->"b.b.vc.OR2_tf[6]._y"-
~("b.b.vc.OR2_tf[6].a"|"b.b.vc.OR2_tf[6].b")->"b.b.vc.OR2_tf[6]._y"+
"b.b.vc.OR2_tf[6]._y"->"b.b.vc.OR2_tf[6].y"-
~("b.b.vc.OR2_tf[6]._y")->"b.b.vc.OR2_tf[6].y"+
= "b.b.vc.supply.vss" "b.b.vc.ct.supply.vss"
= "b.b.vc.supply.vdd" "b.b.vc.ct.supply.vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[6].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[5].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[4].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[3].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[2].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[1].vdd"
= "b.b.vc.supply.vdd" "b.b.vc.OR2_tf[0].vdd"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[6].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[5].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[4].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[3].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[2].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[1].vss"
= "b.b.vc.supply.vss" "b.b.vc.OR2_tf[0].vss"
= "b.b.vc.out" "b.b.vc.ct.out"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.vc.in.d[6].d[0]" "b.b.vc.OR2_tf[6].b"
= "b.b.vc.in.d[6].d[0]" "b.b.vc.in.d[6].f"
= "b.b.vc.in.d[6].d[1]" "b.b.vc.OR2_tf[6].a"
= "b.b.vc.in.d[6].d[1]" "b.b.vc.in.d[6].t"
= "b.b.vc.in.d[5].d[0]" "b.b.vc.OR2_tf[5].b"
= "b.b.vc.in.d[5].d[0]" "b.b.vc.in.d[5].f"
= "b.b.vc.in.d[5].d[1]" "b.b.vc.OR2_tf[5].a"
= "b.b.vc.in.d[5].d[1]" "b.b.vc.in.d[5].t"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.OR2_tf[4].b"
= "b.b.vc.in.d[4].d[0]" "b.b.vc.in.d[4].f"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.OR2_tf[4].a"
= "b.b.vc.in.d[4].d[1]" "b.b.vc.in.d[4].t"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.OR2_tf[3].b"
= "b.b.vc.in.d[3].d[0]" "b.b.vc.in.d[3].f"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.OR2_tf[3].a"
= "b.b.vc.in.d[3].d[1]" "b.b.vc.in.d[3].t"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.OR2_tf[2].b"
= "b.b.vc.in.d[2].d[0]" "b.b.vc.in.d[2].f"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.OR2_tf[2].a"
= "b.b.vc.in.d[2].d[1]" "b.b.vc.in.d[2].t"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.OR2_tf[1].b"
= "b.b.vc.in.d[1].d[0]" "b.b.vc.in.d[1].f"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.OR2_tf[1].a"
= "b.b.vc.in.d[1].d[1]" "b.b.vc.in.d[1].t"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.OR2_tf[0].b"
= "b.b.vc.in.d[0].d[0]" "b.b.vc.in.d[0].f"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.OR2_tf[0].a"
= "b.b.vc.in.d[0].d[1]" "b.b.vc.in.d[0].t"
= "b.b.supply.vss" "b.b.en_buf_f.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_f.supply.vdd"
= "b.b.supply.vss" "b.b.en_buf_t.supply.vss"
= "b.b.supply.vdd" "b.b.en_buf_t.supply.vdd"
= "b.b.supply.vss" "b.b.vc.supply.vss"
= "b.b.supply.vdd" "b.b.vc.supply.vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[6].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[6].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[5].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[5].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[4].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[3].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[2].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[1].vdd"
= "b.b.supply.vdd" "b.b.t_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.f_buf_func[0].vdd"
= "b.b.supply.vdd" "b.b.in_v_buf.vdd"
= "b.b.supply.vdd" "b.b.reset_buf.vdd"
= "b.b.supply.vdd" "b.b.inack_inv.vdd"
= "b.b.supply.vdd" "b.b.inack_ctl.vdd"
= "b.b.supply.vss" "b.b.t_buf_func[6].vss"
= "b.b.supply.vss" "b.b.f_buf_func[6].vss"
= "b.b.supply.vss" "b.b.t_buf_func[5].vss"
= "b.b.supply.vss" "b.b.f_buf_func[5].vss"
= "b.b.supply.vss" "b.b.t_buf_func[4].vss"
= "b.b.supply.vss" "b.b.f_buf_func[4].vss"
= "b.b.supply.vss" "b.b.t_buf_func[3].vss"
= "b.b.supply.vss" "b.b.f_buf_func[3].vss"
= "b.b.supply.vss" "b.b.t_buf_func[2].vss"
= "b.b.supply.vss" "b.b.f_buf_func[2].vss"
= "b.b.supply.vss" "b.b.t_buf_func[1].vss"
= "b.b.supply.vss" "b.b.f_buf_func[1].vss"
= "b.b.supply.vss" "b.b.t_buf_func[0].vss"
= "b.b.supply.vss" "b.b.f_buf_func[0].vss"
= "b.b.supply.vss" "b.b.in_v_buf.vss"
= "b.b.supply.vss" "b.b.reset_buf.vss"
= "b.b.supply.vss" "b.b.inack_inv.vss"
= "b.b.supply.vss" "b.b.inack_ctl.vss"
= "b.b._en" "b.b.en_buf_f.in"
= "b.b._en" "b.b.en_buf_t.in"
= "b.b._en" "b.b.inack_inv.a"
= "b.b._en" "b.b.inack_ctl.y"
= "b.b._en" "b.b.inack_ctl.c1"
= "b.b._en" "b.b._in_aB"
"b.b.reset_inv.a"->"b.b.reset_inv.y"-
~("b.b.reset_inv.a")->"b.b.reset_inv.y"+
= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
= "b.b.out.d[6].d[0]" "b.b.f_buf_func[6].y"
= "b.b.out.d[6].d[0]" "b.b.out.d[6].f"
= "b.b.out.d[6].d[1]" "b.b.t_buf_func[6].y"
= "b.b.out.d[6].d[1]" "b.b.out.d[6].t"
= "b.b.out.d[5].d[0]" "b.b.f_buf_func[5].y"
= "b.b.out.d[5].d[0]" "b.b.out.d[5].f"
= "b.b.out.d[5].d[1]" "b.b.t_buf_func[5].y"
= "b.b.out.d[5].d[1]" "b.b.out.d[5].t"
= "b.b.out.d[4].d[0]" "b.b.f_buf_func[4].y"
= "b.b.out.d[4].d[0]" "b.b.out.d[4].f"
= "b.b.out.d[4].d[1]" "b.b.t_buf_func[4].y"
= "b.b.out.d[4].d[1]" "b.b.out.d[4].t"
= "b.b.out.d[3].d[0]" "b.b.f_buf_func[3].y"
= "b.b.out.d[3].d[0]" "b.b.out.d[3].f"
= "b.b.out.d[3].d[1]" "b.b.t_buf_func[3].y"
= "b.b.out.d[3].d[1]" "b.b.out.d[3].t"
= "b.b.out.d[2].d[0]" "b.b.f_buf_func[2].y"
= "b.b.out.d[2].d[0]" "b.b.out.d[2].f"
= "b.b.out.d[2].d[1]" "b.b.t_buf_func[2].y"
= "b.b.out.d[2].d[1]" "b.b.out.d[2].t"
= "b.b.out.d[1].d[0]" "b.b.f_buf_func[1].y"
= "b.b.out.d[1].d[0]" "b.b.out.d[1].f"
= "b.b.out.d[1].d[1]" "b.b.t_buf_func[1].y"
= "b.b.out.d[1].d[1]" "b.b.out.d[1].t"
= "b.b.out.d[0].d[0]" "b.b.f_buf_func[0].y"
= "b.b.out.d[0].d[0]" "b.b.out.d[0].f"
= "b.b.out.d[0].d[1]" "b.b.t_buf_func[0].y"
= "b.b.out.d[0].d[1]" "b.b.out.d[0].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
= "b.b.in.d.d[0].f" "b.b.vc.in.d[0].f"
= "b.b.in.d.d[0].t" "b.b.vc.in.d[0].t"
= "b.b.in.d.d[0].d[0]" "b.b.vc.in.d[0].d[0]"
= "b.b.in.d.d[0].d[1]" "b.b.vc.in.d[0].d[1]"
= "b.b.in.d.d[1].f" "b.b.vc.in.d[1].f"
= "b.b.in.d.d[1].t" "b.b.vc.in.d[1].t"
= "b.b.in.d.d[1].d[0]" "b.b.vc.in.d[1].d[0]"
= "b.b.in.d.d[1].d[1]" "b.b.vc.in.d[1].d[1]"
= "b.b.in.d.d[2].f" "b.b.vc.in.d[2].f"
= "b.b.in.d.d[2].t" "b.b.vc.in.d[2].t"
= "b.b.in.d.d[2].d[0]" "b.b.vc.in.d[2].d[0]"
= "b.b.in.d.d[2].d[1]" "b.b.vc.in.d[2].d[1]"
= "b.b.in.d.d[3].f" "b.b.vc.in.d[3].f"
= "b.b.in.d.d[3].t" "b.b.vc.in.d[3].t"
= "b.b.in.d.d[3].d[0]" "b.b.vc.in.d[3].d[0]"
= "b.b.in.d.d[3].d[1]" "b.b.vc.in.d[3].d[1]"
= "b.b.in.d.d[4].f" "b.b.vc.in.d[4].f"
= "b.b.in.d.d[4].t" "b.b.vc.in.d[4].t"
= "b.b.in.d.d[4].d[0]" "b.b.vc.in.d[4].d[0]"
= "b.b.in.d.d[4].d[1]" "b.b.vc.in.d[4].d[1]"
= "b.b.in.d.d[5].f" "b.b.vc.in.d[5].f"
= "b.b.in.d.d[5].t" "b.b.vc.in.d[5].t"
= "b.b.in.d.d[5].d[0]" "b.b.vc.in.d[5].d[0]"
= "b.b.in.d.d[5].d[1]" "b.b.vc.in.d[5].d[1]"
= "b.b.in.d.d[6].f" "b.b.vc.in.d[6].f"
= "b.b.in.d.d[6].t" "b.b.vc.in.d[6].t"
= "b.b.in.d.d[6].d[0]" "b.b.vc.in.d[6].d[0]"
= "b.b.in.d.d[6].d[1]" "b.b.vc.in.d[6].d[1]"
= "b.b.in.a" "b.b.inack_inv.y"
= "b.b.in.v" "b.b.in_v_buf.y"
= "b.b.in.v" "b.b.inack_ctl.c2"
= "b.b.in.d.d[6].d[0]" "b.b.f_buf_func[6].n1"
= "b.b.in.d.d[6].d[0]" "b.b.in.d.d[6].f"
= "b.b.in.d.d[6].d[1]" "b.b.t_buf_func[6].n1"
= "b.b.in.d.d[6].d[1]" "b.b.in.d.d[6].t"
= "b.b.in.d.d[5].d[0]" "b.b.f_buf_func[5].n1"
= "b.b.in.d.d[5].d[0]" "b.b.in.d.d[5].f"
= "b.b.in.d.d[5].d[1]" "b.b.t_buf_func[5].n1"
= "b.b.in.d.d[5].d[1]" "b.b.in.d.d[5].t"
= "b.b.in.d.d[4].d[0]" "b.b.f_buf_func[4].n1"
= "b.b.in.d.d[4].d[0]" "b.b.in.d.d[4].f"
= "b.b.in.d.d[4].d[1]" "b.b.t_buf_func[4].n1"
= "b.b.in.d.d[4].d[1]" "b.b.in.d.d[4].t"
= "b.b.in.d.d[3].d[0]" "b.b.f_buf_func[3].n1"
= "b.b.in.d.d[3].d[0]" "b.b.in.d.d[3].f"
= "b.b.in.d.d[3].d[1]" "b.b.t_buf_func[3].n1"
= "b.b.in.d.d[3].d[1]" "b.b.in.d.d[3].t"
= "b.b.in.d.d[2].d[0]" "b.b.f_buf_func[2].n1"
= "b.b.in.d.d[2].d[0]" "b.b.in.d.d[2].f"
= "b.b.in.d.d[2].d[1]" "b.b.t_buf_func[2].n1"
= "b.b.in.d.d[2].d[1]" "b.b.in.d.d[2].t"
= "b.b.in.d.d[1].d[0]" "b.b.f_buf_func[1].n1"
= "b.b.in.d.d[1].d[0]" "b.b.in.d.d[1].f"
= "b.b.in.d.d[1].d[1]" "b.b.t_buf_func[1].n1"
= "b.b.in.d.d[1].d[1]" "b.b.in.d.d[1].t"
= "b.b.in.d.d[0].d[0]" "b.b.f_buf_func[0].n1"
= "b.b.in.d.d[0].d[0]" "b.b.in.d.d[0].f"
= "b.b.in.d.d[0].d[1]" "b.b.t_buf_func[0].n1"
= "b.b.in.d.d[0].d[1]" "b.b.in.d.d[0].t"
"b.b.inack_inv.a"->"b.b.inack_inv.y"-
~("b.b.inack_inv.a")->"b.b.inack_inv.y"+
= "b.b._in_v" "b.b.in_v_buf.a"
= "b.b._in_v" "b.b.vc.out"
"b.b.reset_buf.a"->"b.b.reset_buf._y"-
~("b.b.reset_buf.a")->"b.b.reset_buf._y"+
"b.b.reset_buf._y"->"b.b.reset_buf.y"-
~("b.b.reset_buf._y")->"b.b.reset_buf.y"+
"b.b.flush_inv.a"->"b.b.flush_inv.y"-
~("b.b.flush_inv.a")->"b.b.flush_inv.y"+
= "b.b._reset_BX" "b.b.reset_bufarray.in"
= "b.b._reset_BX" "b.b.reset_buf.y"
= "b.b._reset_BX" "b.b.inack_ctl.sr_B"
= "b.b._reset_BX" "b.b.inack_ctl.pr_B"
= "b.b.reset_B" "b.b.reset_buf.a"
= "b.b.reset_B" "b.b.reset_inv.a"
= "b.b._reset" "b.b.t_buf_func[6].sr"
= "b.b._reset" "b.b.t_buf_func[6].pr"
= "b.b._reset" "b.b.t_buf_func[5].sr"
= "b.b._reset" "b.b.t_buf_func[5].pr"
= "b.b._reset" "b.b.t_buf_func[4].sr"
= "b.b._reset" "b.b.t_buf_func[4].pr"
= "b.b._reset" "b.b.t_buf_func[3].sr"
= "b.b._reset" "b.b.t_buf_func[3].pr"
= "b.b._reset" "b.b.t_buf_func[2].sr"
= "b.b._reset" "b.b.t_buf_func[2].pr"
= "b.b._reset" "b.b.t_buf_func[1].sr"
= "b.b._reset" "b.b.t_buf_func[1].pr"
= "b.b._reset" "b.b.t_buf_func[0].sr"
= "b.b._reset" "b.b.t_buf_func[0].pr"
= "b.b._reset" "b.b.reset_inv.y"
= "b.b._flushB" "b.b.t_buf_func[6].c1"
= "b.b._flushB" "b.b.f_buf_func[6].c1"
= "b.b._flushB" "b.b.t_buf_func[5].c1"
= "b.b._flushB" "b.b.f_buf_func[5].c1"
= "b.b._flushB" "b.b.t_buf_func[4].c1"
= "b.b._flushB" "b.b.f_buf_func[4].c1"
= "b.b._flushB" "b.b.t_buf_func[3].c1"
= "b.b._flushB" "b.b.f_buf_func[3].c1"
= "b.b._flushB" "b.b.t_buf_func[2].c1"
= "b.b._flushB" "b.b.f_buf_func[2].c1"
= "b.b._flushB" "b.b.t_buf_func[1].c1"
= "b.b._flushB" "b.b.f_buf_func[1].c1"
= "b.b._flushB" "b.b.t_buf_func[0].c1"
= "b.b._flushB" "b.b.f_buf_func[0].c1"
= "b.b._flushB" "b.b.flush_inv.y"
"b.b.en_buf_f.buf2.a"->"b.b.en_buf_f.buf2._y"-
~("b.b.en_buf_f.buf2.a")->"b.b.en_buf_f.buf2._y"+
"b.b.en_buf_f.buf2._y"->"b.b.en_buf_f.buf2.y"-
~("b.b.en_buf_f.buf2._y")->"b.b.en_buf_f.buf2.y"+
= "b.b.en_buf_f.supply.vdd" "b.b.en_buf_f.buf2.vdd"
= "b.b.en_buf_f.supply.vss" "b.b.en_buf_f.buf2.vss"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[6]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[5]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[4]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[3]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[2]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.out[1]"
= "b.b.en_buf_f.out[0]" "b.b.en_buf_f.buf2.y"
= "b.b.en_buf_f.in" "b.b.en_buf_f.buf2.a"
"b.b.en_buf_t.buf2.a"->"b.b.en_buf_t.buf2._y"-
~("b.b.en_buf_t.buf2.a")->"b.b.en_buf_t.buf2._y"+
"b.b.en_buf_t.buf2._y"->"b.b.en_buf_t.buf2.y"-
~("b.b.en_buf_t.buf2._y")->"b.b.en_buf_t.buf2.y"+
= "b.b.en_buf_t.supply.vdd" "b.b.en_buf_t.buf2.vdd"
= "b.b.en_buf_t.supply.vss" "b.b.en_buf_t.buf2.vss"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[6]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[5]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[4]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[3]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[2]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.out[1]"
= "b.b.en_buf_t.out[0]" "b.b.en_buf_t.buf2.y"
= "b.b.en_buf_t.in" "b.b.en_buf_t.buf2.a"
= "b.b._reset_BXX[0]" "b.b.reset_bufarray.out[0]"
= "b.b._reset_BXX[1]" "b.b.reset_bufarray.out[1]"
= "b.b._reset_BXX[2]" "b.b.reset_bufarray.out[2]"
= "b.b._reset_BXX[3]" "b.b.reset_bufarray.out[3]"
= "b.b._reset_BXX[4]" "b.b.reset_bufarray.out[4]"
= "b.b._reset_BXX[5]" "b.b.reset_bufarray.out[5]"
= "b.b._reset_BXX[6]" "b.b.reset_bufarray.out[6]"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[6].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[6].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[5].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[5].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[4].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[3].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[2].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[1].pr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].sr_B"
= "b.b._reset_BXX[0]" "b.b.f_buf_func[0].pr_B"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[6]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[5]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[4]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[3]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[2]"
= "b.b._reset_BXX[0]" "b.b._reset_BXX[1]"
~"b.b.t_buf_func[0].c1"&~"b.b.t_buf_func[0].sr"->"b.b.t_buf_func[0]._y"+
"b.b.t_buf_func[0].c1"&"b.b.t_buf_func[0].n1"&"b.b.t_buf_func[0].n2"|"b.b.t_buf_func[0].pr"->"b.b.t_buf_func[0]._y"-
"b.b.t_buf_func[0]._y"->"b.b.t_buf_func[0].y"-
~("b.b.t_buf_func[0]._y")->"b.b.t_buf_func[0].y"+
~"b.b.t_buf_func[1].c1"&~"b.b.t_buf_func[1].sr"->"b.b.t_buf_func[1]._y"+
"b.b.t_buf_func[1].c1"&"b.b.t_buf_func[1].n1"&"b.b.t_buf_func[1].n2"|"b.b.t_buf_func[1].pr"->"b.b.t_buf_func[1]._y"-
"b.b.t_buf_func[1]._y"->"b.b.t_buf_func[1].y"-
~("b.b.t_buf_func[1]._y")->"b.b.t_buf_func[1].y"+
~"b.b.t_buf_func[2].c1"&~"b.b.t_buf_func[2].sr"->"b.b.t_buf_func[2]._y"+
"b.b.t_buf_func[2].c1"&"b.b.t_buf_func[2].n1"&"b.b.t_buf_func[2].n2"|"b.b.t_buf_func[2].pr"->"b.b.t_buf_func[2]._y"-
"b.b.t_buf_func[2]._y"->"b.b.t_buf_func[2].y"-
~("b.b.t_buf_func[2]._y")->"b.b.t_buf_func[2].y"+
~"b.b.t_buf_func[3].c1"&~"b.b.t_buf_func[3].sr"->"b.b.t_buf_func[3]._y"+
"b.b.t_buf_func[3].c1"&"b.b.t_buf_func[3].n1"&"b.b.t_buf_func[3].n2"|"b.b.t_buf_func[3].pr"->"b.b.t_buf_func[3]._y"-
"b.b.t_buf_func[3]._y"->"b.b.t_buf_func[3].y"-
~("b.b.t_buf_func[3]._y")->"b.b.t_buf_func[3].y"+
~"b.b.t_buf_func[4].c1"&~"b.b.t_buf_func[4].sr"->"b.b.t_buf_func[4]._y"+
"b.b.t_buf_func[4].c1"&"b.b.t_buf_func[4].n1"&"b.b.t_buf_func[4].n2"|"b.b.t_buf_func[4].pr"->"b.b.t_buf_func[4]._y"-
"b.b.t_buf_func[4]._y"->"b.b.t_buf_func[4].y"-
~("b.b.t_buf_func[4]._y")->"b.b.t_buf_func[4].y"+
~"b.b.t_buf_func[5].c1"&~"b.b.t_buf_func[5].sr"->"b.b.t_buf_func[5]._y"+
"b.b.t_buf_func[5].c1"&"b.b.t_buf_func[5].n1"&"b.b.t_buf_func[5].n2"|"b.b.t_buf_func[5].pr"->"b.b.t_buf_func[5]._y"-
"b.b.t_buf_func[5]._y"->"b.b.t_buf_func[5].y"-
~("b.b.t_buf_func[5]._y")->"b.b.t_buf_func[5].y"+
~"b.b.t_buf_func[6].c1"&~"b.b.t_buf_func[6].sr"->"b.b.t_buf_func[6]._y"+
"b.b.t_buf_func[6].c1"&"b.b.t_buf_func[6].n1"&"b.b.t_buf_func[6].n2"|"b.b.t_buf_func[6].pr"->"b.b.t_buf_func[6]._y"-
"b.b.t_buf_func[6]._y"->"b.b.t_buf_func[6].y"-
~("b.b.t_buf_func[6]._y")->"b.b.t_buf_func[6].y"+
~"b.b.f_buf_func[0].c1"|~"b.b.f_buf_func[0].pr_B"->"b.b.f_buf_func[0]._y"+
"b.b.f_buf_func[0].c1"&"b.b.f_buf_func[0].n1"&"b.b.f_buf_func[0].n2"&"b.b.f_buf_func[0].sr_B"->"b.b.f_buf_func[0]._y"-
"b.b.f_buf_func[0]._y"->"b.b.f_buf_func[0].y"-
~("b.b.f_buf_func[0]._y")->"b.b.f_buf_func[0].y"+
~"b.b.f_buf_func[1].c1"|~"b.b.f_buf_func[1].pr_B"->"b.b.f_buf_func[1]._y"+
"b.b.f_buf_func[1].c1"&"b.b.f_buf_func[1].n1"&"b.b.f_buf_func[1].n2"&"b.b.f_buf_func[1].sr_B"->"b.b.f_buf_func[1]._y"-
"b.b.f_buf_func[1]._y"->"b.b.f_buf_func[1].y"-
~("b.b.f_buf_func[1]._y")->"b.b.f_buf_func[1].y"+
~"b.b.f_buf_func[2].c1"|~"b.b.f_buf_func[2].pr_B"->"b.b.f_buf_func[2]._y"+
"b.b.f_buf_func[2].c1"&"b.b.f_buf_func[2].n1"&"b.b.f_buf_func[2].n2"&"b.b.f_buf_func[2].sr_B"->"b.b.f_buf_func[2]._y"-
"b.b.f_buf_func[2]._y"->"b.b.f_buf_func[2].y"-
~("b.b.f_buf_func[2]._y")->"b.b.f_buf_func[2].y"+
~"b.b.f_buf_func[3].c1"|~"b.b.f_buf_func[3].pr_B"->"b.b.f_buf_func[3]._y"+
"b.b.f_buf_func[3].c1"&"b.b.f_buf_func[3].n1"&"b.b.f_buf_func[3].n2"&"b.b.f_buf_func[3].sr_B"->"b.b.f_buf_func[3]._y"-
"b.b.f_buf_func[3]._y"->"b.b.f_buf_func[3].y"-
~("b.b.f_buf_func[3]._y")->"b.b.f_buf_func[3].y"+
~"b.b.f_buf_func[4].c1"|~"b.b.f_buf_func[4].pr_B"->"b.b.f_buf_func[4]._y"+
"b.b.f_buf_func[4].c1"&"b.b.f_buf_func[4].n1"&"b.b.f_buf_func[4].n2"&"b.b.f_buf_func[4].sr_B"->"b.b.f_buf_func[4]._y"-
"b.b.f_buf_func[4]._y"->"b.b.f_buf_func[4].y"-
~("b.b.f_buf_func[4]._y")->"b.b.f_buf_func[4].y"+
~"b.b.f_buf_func[5].c1"|~"b.b.f_buf_func[5].pr_B"->"b.b.f_buf_func[5]._y"+
"b.b.f_buf_func[5].c1"&"b.b.f_buf_func[5].n1"&"b.b.f_buf_func[5].n2"&"b.b.f_buf_func[5].sr_B"->"b.b.f_buf_func[5]._y"-
"b.b.f_buf_func[5]._y"->"b.b.f_buf_func[5].y"-
~("b.b.f_buf_func[5]._y")->"b.b.f_buf_func[5].y"+
~"b.b.f_buf_func[6].c1"|~"b.b.f_buf_func[6].pr_B"->"b.b.f_buf_func[6]._y"+
"b.b.f_buf_func[6].c1"&"b.b.f_buf_func[6].n1"&"b.b.f_buf_func[6].n2"&"b.b.f_buf_func[6].sr_B"->"b.b.f_buf_func[6]._y"-
"b.b.f_buf_func[6]._y"->"b.b.f_buf_func[6].y"-
~("b.b.f_buf_func[6]._y")->"b.b.f_buf_func[6].y"+
= "b.b._en_X_t[0]" "b.b.en_buf_t.out[0]"
= "b.b._en_X_t[1]" "b.b.en_buf_t.out[1]"
= "b.b._en_X_t[2]" "b.b.en_buf_t.out[2]"
= "b.b._en_X_t[3]" "b.b.en_buf_t.out[3]"
= "b.b._en_X_t[4]" "b.b.en_buf_t.out[4]"
= "b.b._en_X_t[5]" "b.b.en_buf_t.out[5]"
= "b.b._en_X_t[6]" "b.b.en_buf_t.out[6]"
= "b.b._en_X_t[0]" "b.b.t_buf_func[6].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[5].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[4].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[3].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[2].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[1].n2"
= "b.b._en_X_t[0]" "b.b.t_buf_func[0].n2"
= "b.b._en_X_t[0]" "b.b._en_X_t[6]"
= "b.b._en_X_t[0]" "b.b._en_X_t[5]"
= "b.b._en_X_t[0]" "b.b._en_X_t[4]"
= "b.b._en_X_t[0]" "b.b._en_X_t[3]"
= "b.b._en_X_t[0]" "b.b._en_X_t[2]"
= "b.b._en_X_t[0]" "b.b._en_X_t[1]"
= "b.b.out_v" "b.b.inack_ctl.n1"
= "b._reset_B" "b.b.reset_B"
= "b.flush" "b.b.flush"
= "Vdd" "b.supply.vdd"
= "GND" "b.supply.vss"
= "b.out_v" "b.b.out_v"
= "b.out.d[0].d[0]" "b.out.d[0].f"
= "b.out.d[0].d[1]" "b.out.d[0].t"
= "b.out.d[1].d[0]" "b.out.d[1].f"
= "b.out.d[1].d[1]" "b.out.d[1].t"
= "b.out.d[2].d[0]" "b.out.d[2].f"
= "b.out.d[2].d[1]" "b.out.d[2].t"
= "b.out.d[3].d[0]" "b.out.d[3].f"
= "b.out.d[3].d[1]" "b.out.d[3].t"
= "b.out.d[4].d[0]" "b.out.d[4].f"
= "b.out.d[4].d[1]" "b.out.d[4].t"
= "b.out.d[5].d[0]" "b.out.d[5].f"
= "b.out.d[5].d[1]" "b.out.d[5].t"
= "b.out.d[6].d[0]" "b.out.d[6].f"
= "b.out.d[6].d[1]" "b.out.d[6].t"
= "b.out.d[6].d[0]" "b.out.d[6].f"
= "b.out.d[6].d[1]" "b.out.d[6].t"
= "b.out.d[5].d[0]" "b.out.d[5].f"
= "b.out.d[5].d[1]" "b.out.d[5].t"
= "b.out.d[4].d[0]" "b.out.d[4].f"
= "b.out.d[4].d[1]" "b.out.d[4].t"
= "b.out.d[3].d[0]" "b.out.d[3].f"
= "b.out.d[3].d[1]" "b.out.d[3].t"
= "b.out.d[2].d[0]" "b.out.d[2].f"
= "b.out.d[2].d[1]" "b.out.d[2].t"
= "b.out.d[1].d[0]" "b.out.d[1].f"
= "b.out.d[1].d[1]" "b.out.d[1].t"
= "b.out.d[0].d[0]" "b.out.d[0].f"
= "b.out.d[0].d[1]" "b.out.d[0].t"
= "b.out.d[0].f" "b.b.out.d[0].f"
= "b.out.d[0].t" "b.b.out.d[0].t"
= "b.out.d[0].d[0]" "b.b.out.d[0].d[0]"
= "b.out.d[0].d[1]" "b.b.out.d[0].d[1]"
= "b.out.d[1].f" "b.b.out.d[1].f"
= "b.out.d[1].t" "b.b.out.d[1].t"
= "b.out.d[1].d[0]" "b.b.out.d[1].d[0]"
= "b.out.d[1].d[1]" "b.b.out.d[1].d[1]"
= "b.out.d[2].f" "b.b.out.d[2].f"
= "b.out.d[2].t" "b.b.out.d[2].t"
= "b.out.d[2].d[0]" "b.b.out.d[2].d[0]"
= "b.out.d[2].d[1]" "b.b.out.d[2].d[1]"
= "b.out.d[3].f" "b.b.out.d[3].f"
= "b.out.d[3].t" "b.b.out.d[3].t"
= "b.out.d[3].d[0]" "b.b.out.d[3].d[0]"
= "b.out.d[3].d[1]" "b.b.out.d[3].d[1]"
= "b.out.d[4].f" "b.b.out.d[4].f"
= "b.out.d[4].t" "b.b.out.d[4].t"
= "b.out.d[4].d[0]" "b.b.out.d[4].d[0]"
= "b.out.d[4].d[1]" "b.b.out.d[4].d[1]"
= "b.out.d[5].f" "b.b.out.d[5].f"
= "b.out.d[5].t" "b.b.out.d[5].t"
= "b.out.d[5].d[0]" "b.b.out.d[5].d[0]"
= "b.out.d[5].d[1]" "b.b.out.d[5].d[1]"
= "b.out.d[6].f" "b.b.out.d[6].f"
= "b.out.d[6].t" "b.b.out.d[6].t"
= "b.out.d[6].d[0]" "b.b.out.d[6].d[0]"
= "b.out.d[6].d[1]" "b.b.out.d[6].d[1]"
= "b.out.d[6].d[0]" "b.out.d[6].f"
= "b.out.d[6].d[1]" "b.out.d[6].t"
= "b.out.d[5].d[0]" "b.out.d[5].f"
= "b.out.d[5].d[1]" "b.out.d[5].t"
= "b.out.d[4].d[0]" "b.out.d[4].f"
= "b.out.d[4].d[1]" "b.out.d[4].t"
= "b.out.d[3].d[0]" "b.out.d[3].f"
= "b.out.d[3].d[1]" "b.out.d[3].t"
= "b.out.d[2].d[0]" "b.out.d[2].f"
= "b.out.d[2].d[1]" "b.out.d[2].t"
= "b.out.d[1].d[0]" "b.out.d[1].f"
= "b.out.d[1].d[1]" "b.out.d[1].t"
= "b.out.d[0].d[0]" "b.out.d[0].f"
= "b.out.d[0].d[1]" "b.out.d[0].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"
= "b.in.v" "b.b.in.v"
= "b.in.a" "b.b.in.a"
= "b.in.d.d[0].f" "b.b.in.d.d[0].f"
= "b.in.d.d[0].t" "b.b.in.d.d[0].t"
= "b.in.d.d[0].d[0]" "b.b.in.d.d[0].d[0]"
= "b.in.d.d[0].d[1]" "b.b.in.d.d[0].d[1]"
= "b.in.d.d[1].f" "b.b.in.d.d[1].f"
= "b.in.d.d[1].t" "b.b.in.d.d[1].t"
= "b.in.d.d[1].d[0]" "b.b.in.d.d[1].d[0]"
= "b.in.d.d[1].d[1]" "b.b.in.d.d[1].d[1]"
= "b.in.d.d[2].f" "b.b.in.d.d[2].f"
= "b.in.d.d[2].t" "b.b.in.d.d[2].t"
= "b.in.d.d[2].d[0]" "b.b.in.d.d[2].d[0]"
= "b.in.d.d[2].d[1]" "b.b.in.d.d[2].d[1]"
= "b.in.d.d[3].f" "b.b.in.d.d[3].f"
= "b.in.d.d[3].t" "b.b.in.d.d[3].t"
= "b.in.d.d[3].d[0]" "b.b.in.d.d[3].d[0]"
= "b.in.d.d[3].d[1]" "b.b.in.d.d[3].d[1]"
= "b.in.d.d[4].f" "b.b.in.d.d[4].f"
= "b.in.d.d[4].t" "b.b.in.d.d[4].t"
= "b.in.d.d[4].d[0]" "b.b.in.d.d[4].d[0]"
= "b.in.d.d[4].d[1]" "b.b.in.d.d[4].d[1]"
= "b.in.d.d[5].f" "b.b.in.d.d[5].f"
= "b.in.d.d[5].t" "b.b.in.d.d[5].t"
= "b.in.d.d[5].d[0]" "b.b.in.d.d[5].d[0]"
= "b.in.d.d[5].d[1]" "b.b.in.d.d[5].d[1]"
= "b.in.d.d[6].f" "b.b.in.d.d[6].f"
= "b.in.d.d[6].t" "b.b.in.d.d[6].t"
= "b.in.d.d[6].d[0]" "b.b.in.d.d[6].d[0]"
= "b.in.d.d[6].d[1]" "b.b.in.d.d[6].d[1]"
= "b.in.d.d[6].d[0]" "b.in.d.d[6].f"
= "b.in.d.d[6].d[1]" "b.in.d.d[6].t"
= "b.in.d.d[5].d[0]" "b.in.d.d[5].f"
= "b.in.d.d[5].d[1]" "b.in.d.d[5].t"
= "b.in.d.d[4].d[0]" "b.in.d.d[4].f"
= "b.in.d.d[4].d[1]" "b.in.d.d[4].t"
= "b.in.d.d[3].d[0]" "b.in.d.d[3].f"
= "b.in.d.d[3].d[1]" "b.in.d.d[3].t"
= "b.in.d.d[2].d[0]" "b.in.d.d[2].f"
= "b.in.d.d[2].d[1]" "b.in.d.d[2].t"
= "b.in.d.d[1].d[0]" "b.in.d.d[1].f"
= "b.in.d.d[1].d[1]" "b.in.d.d[1].t"
= "b.in.d.d[0].d[0]" "b.in.d.d[0].f"
= "b.in.d.d[0].d[1]" "b.in.d.d[0].t"

52
test/unit_tests/buffer_register_7/test.act
View File

@@ -1,52 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/registers.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc buffer_register_7 (avMx1of2<7> in; Mx1of2<7> out; bool? out_v, flush){
bool _reset_B;
prs {
Reset => _reset_B-
}
power supply;
supply.vdd = Vdd;
supply.vss = GND;
buffer_register<7> b(.in = in, .out = out, .out_v = out_v, .flush = flush, .reset_B = _reset_B);
}
// fifo_decoder_neurons_encoder_fifo e;
buffer_register_7 b;

163
test/unit_tests/buffer_register_7/test.prsim
View File

@@ -1,163 +0,0 @@
watchall
set b.out_v 0
set b.flush 0
set-qdi-channel-neutral "b.in" 7
cycle
mode run
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle
assert b.in.a 0
assert b.in.v 0
system "echo '[] Flushing data'"
set b.flush 1
cycle
assert b.out.d[0].t 0
assert b.out.d[1].t 0
assert b.out.d[2].t 0
assert b.out.d[3].t 0
assert b.out.d[4].t 0
assert b.out.d[5].t 0
assert b.out.d[6].t 0
assert b.out.d[0].f 0
assert b.out.d[1].f 0
assert b.out.d[2].f 0
assert b.out.d[3].f 0
assert b.out.d[4].f 0
assert b.out.d[5].f 0
assert b.out.d[6].f 0
set b.out_v 0
set b.flush 0
cycle
system "echo '[] Sending in a 0'"
set-qdi-channel-valid "b.in" 7 0
cycle
# assert-qdi-channel-valid 'b.out' 7 127
assert b.in.a 0
assert b.in.v 1
assert-var-int "b.out" 7 0
system "echo '[] Sending in output valid'"
set b.out_v 1
cycle
assert b.in.a 1
assert b.in.v 1
assert-var-int "b.out" 7 0
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 7
cycle
assert b.in.a 0
assert b.in.v 0
assert-var-int "b.out" 7 0
system "echo '[] Flushing data'"
set b.flush 1
cycle
assert b.out.d[0].t 0
assert b.out.d[1].t 0
assert b.out.d[2].t 0
assert b.out.d[3].t 0
assert b.out.d[4].t 0
assert b.out.d[5].t 0
assert b.out.d[6].t 0
assert b.out.d[0].f 0
assert b.out.d[1].f 0
assert b.out.d[2].f 0
assert b.out.d[3].f 0
assert b.out.d[4].f 0
assert b.out.d[5].f 0
assert b.out.d[6].f 0
set b.out_v 0
cycle
set b.flush 0
cycle
system "echo '[] Sending in a 127'"
set-qdi-channel-valid "b.in" 7 127
cycle
# assert-qdi-channel-valid 'b.out' 7 127
assert b.in.a 0
assert b.in.v 1
assert-var-int "b.out" 7 127
system "echo '[] Sending in output valid'"
set b.out_v 1
cycle
assert b.in.a 1
assert b.in.v 1
assert-var-int "b.out" 7 127
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 7
cycle
assert b.in.a 0
assert b.in.v 0
assert-var-int "b.out" 7 127
system "echo '[] Flushing data'"
set b.flush 1
cycle
assert b.out.d[0].t 0
assert b.out.d[1].t 0
assert b.out.d[2].t 0
assert b.out.d[3].t 0
assert b.out.d[4].t 0
assert b.out.d[5].t 0
assert b.out.d[6].t 0
assert b.out.d[0].f 0
assert b.out.d[1].f 0
assert b.out.d[2].f 0
assert b.out.d[3].f 0
assert b.out.d[4].f 0
assert b.out.d[5].f 0
assert b.out.d[6].f 0
set b.out_v 0
cycle
set b.flush 0
cycle
system "echo '[] Sending in a 56'"
set-qdi-channel-valid "b.in" 7 56
cycle
assert b.in.a 0
assert b.in.v 1
assert-var-int "b.out" 7 56
system "echo '[] Sending in output valid'"
set b.out_v 1
cycle
assert b.in.a 1
assert b.in.v 1
assert-var-int "b.out" 7 56
system "echo '[] Removing input'"
set-qdi-channel-neutral "b.in" 7
cycle
assert b.in.a 0
assert b.in.v 0
assert-var-int "b.out" 7 56
system "echo '[] Resetting'"
set Reset 1
cycle
assert-var-int "b.out" 7 127
set Reset 0
cycle
assert-var-int "b.out" 7 127

29
test/unit_tests/buffer_token/run/prsim.out
View File

@@ -1,29 +0,0 @@
t.a._out_a_B t.in.r t.in.a t.out.r t.a._en t.a.inack_ctl._y t.out.a t.a.buf_func._y
[0] code starts
7093 t.in.r : 0
7093 t.out.a : 0
17560 t.a._out_a_B : 1 [by t.out.a:=0]
17560 Reset : 0
17562 t.a.reset_buf._y : 1 [by Reset:=0]
22315 t.a._reset_BX : 0 [by t.a.reset_buf._y:=1]
22429 t.a.inack_ctl._y : 1 [by t.a._reset_BX:=0]
23452 t.a.buf_func._y : 1 [by t.a._reset_BX:=0]
25178 t.out.r : 0 [by t.a.buf_func._y:=1]
87795 t.in.a : 0 [by t.a.inack_ctl._y:=1]
87834 t.a._en : 1 [by t.in.a:=0]
87834 Reset : 1
87849 t.a.reset_buf._y : 0 [by Reset:=1]
88340 t.a._reset_BX : 1 [by t.a.reset_buf._y:=0]
[1] reset done
----------------------------------------------------------------------------------------------------
88340 t.in.r : 1
88353 t.a.buf_func._y : 0 [by t.in.r:=1]
88393 t.out.r : 1 [by t.a.buf_func._y:=0]
88808 t.a.inack_ctl._y : 0 [by t.out.r:=1]
88828 t.in.a : 1 [by t.a.inack_ctl._y:=0]
94889 t.a._en : 0 [by t.in.a:=1]
94889 t.out.a : 1
94936 t.a._out_a_B : 0 [by t.out.a:=1]
94952 t.a.buf_func._y : 1 [by t.a._out_a_B:=0]
139050 t.out.r : 0 [by t.a.buf_func._y:=1]

43
test/unit_tests/buffer_token/test.act
View File

@@ -1,43 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc buffer_token_test(a1of1 in; a1of1 out)
{
buffer_t a(.in = in, .out = out);
a.supply.vdd = Vdd;
a.supply.vss = GND;
a.reset_B = Reset;
}
buffer_token_test t;

20
test/unit_tests/buffer_token/test.prsim
View File

@@ -1,20 +0,0 @@
watchall
system "echo '[0] code starts'"
set t.in.r 0
set t.out.a 0
cycle
set Reset 0
cycle
status X
mode run
set Reset 1
cycle
system "echo '[1] reset done'"
system "echo '----------------------------------------------------------------------------------------------------'"
set t.in.r 1
cycle
assert t.out.r 1
set t.out.a 1
cycle
assert t.in.a 1

4
test/unit_tests/ctree_15/run/prsim.out
View File

@@ -1,4 +0,0 @@
t.ctree_test.tmp[22] t.ctree_test.C2Els[0]._y t.ctree_test.tmp[17] t.in[14] t.in[4] t.in[2] t.in[8] t.in[13] t.ctree_test.tmp[21] t.ctree_test.tmp[23] t.out t.in[12] t.in[6] t.in[7] t.in[10] t.in[5] t.ctree_test.tmp[19] t.ctree_test.tmp[18] t.ctree_test.C3Els[0]._y t.in[3] t.ctree_test.tmp[24] t.ctree_test.C3Els[2]._y t.ctree_test.C2Els[4]._y t.in[0] t.in[1] t.ctree_test.tmp[15] t.ctree_test.tmp[16] t.in[11] t.ctree_test.tmp[20] t.ctree_test.C2Els[7]._y t.in[9] t.ctree_test.C2Els[2]._y t.ctree_test.C2Els[1]._y t.ctree_test.C2Els[6]._y t.ctree_test.C2Els[5]._y t.ctree_test.C2Els[3]._y t.ctree_test.C3Els[1]._y
[0] starting test all 1
[1] starting test all 0
[2] testing state holding

139
test/unit_tests/ctree_15/run/test.prs
View File

@@ -1,139 +0,0 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
~"t.ctree_test.C2Els[0].c1"&~"t.ctree_test.C2Els[0].c2"->"t.ctree_test.C2Els[0]._y"+
"t.ctree_test.C2Els[0].c1"&"t.ctree_test.C2Els[0].c2"->"t.ctree_test.C2Els[0]._y"-
"t.ctree_test.C2Els[0]._y"->"t.ctree_test.C2Els[0].y"-
~("t.ctree_test.C2Els[0]._y")->"t.ctree_test.C2Els[0].y"+
~"t.ctree_test.C2Els[1].c1"&~"t.ctree_test.C2Els[1].c2"->"t.ctree_test.C2Els[1]._y"+
"t.ctree_test.C2Els[1].c1"&"t.ctree_test.C2Els[1].c2"->"t.ctree_test.C2Els[1]._y"-
"t.ctree_test.C2Els[1]._y"->"t.ctree_test.C2Els[1].y"-
~("t.ctree_test.C2Els[1]._y")->"t.ctree_test.C2Els[1].y"+
~"t.ctree_test.C2Els[2].c1"&~"t.ctree_test.C2Els[2].c2"->"t.ctree_test.C2Els[2]._y"+
"t.ctree_test.C2Els[2].c1"&"t.ctree_test.C2Els[2].c2"->"t.ctree_test.C2Els[2]._y"-
"t.ctree_test.C2Els[2]._y"->"t.ctree_test.C2Els[2].y"-
~("t.ctree_test.C2Els[2]._y")->"t.ctree_test.C2Els[2].y"+
~"t.ctree_test.C2Els[3].c1"&~"t.ctree_test.C2Els[3].c2"->"t.ctree_test.C2Els[3]._y"+
"t.ctree_test.C2Els[3].c1"&"t.ctree_test.C2Els[3].c2"->"t.ctree_test.C2Els[3]._y"-
"t.ctree_test.C2Els[3]._y"->"t.ctree_test.C2Els[3].y"-
~("t.ctree_test.C2Els[3]._y")->"t.ctree_test.C2Els[3].y"+
~"t.ctree_test.C2Els[4].c1"&~"t.ctree_test.C2Els[4].c2"->"t.ctree_test.C2Els[4]._y"+
"t.ctree_test.C2Els[4].c1"&"t.ctree_test.C2Els[4].c2"->"t.ctree_test.C2Els[4]._y"-
"t.ctree_test.C2Els[4]._y"->"t.ctree_test.C2Els[4].y"-
~("t.ctree_test.C2Els[4]._y")->"t.ctree_test.C2Els[4].y"+
~"t.ctree_test.C2Els[5].c1"&~"t.ctree_test.C2Els[5].c2"->"t.ctree_test.C2Els[5]._y"+
"t.ctree_test.C2Els[5].c1"&"t.ctree_test.C2Els[5].c2"->"t.ctree_test.C2Els[5]._y"-
"t.ctree_test.C2Els[5]._y"->"t.ctree_test.C2Els[5].y"-
~("t.ctree_test.C2Els[5]._y")->"t.ctree_test.C2Els[5].y"+
~"t.ctree_test.C2Els[6].c1"&~"t.ctree_test.C2Els[6].c2"->"t.ctree_test.C2Els[6]._y"+
"t.ctree_test.C2Els[6].c1"&"t.ctree_test.C2Els[6].c2"->"t.ctree_test.C2Els[6]._y"-
"t.ctree_test.C2Els[6]._y"->"t.ctree_test.C2Els[6].y"-
~("t.ctree_test.C2Els[6]._y")->"t.ctree_test.C2Els[6].y"+
~"t.ctree_test.C2Els[7].c1"&~"t.ctree_test.C2Els[7].c2"->"t.ctree_test.C2Els[7]._y"+
"t.ctree_test.C2Els[7].c1"&"t.ctree_test.C2Els[7].c2"->"t.ctree_test.C2Els[7]._y"-
"t.ctree_test.C2Els[7]._y"->"t.ctree_test.C2Els[7].y"-
~("t.ctree_test.C2Els[7]._y")->"t.ctree_test.C2Els[7].y"+
~"t.ctree_test.C3Els[0].c1"&~"t.ctree_test.C3Els[0].c2"&~"t.ctree_test.C3Els[0].c3"->"t.ctree_test.C3Els[0]._y"+
"t.ctree_test.C3Els[0].c1"&"t.ctree_test.C3Els[0].c2"&"t.ctree_test.C3Els[0].c3"->"t.ctree_test.C3Els[0]._y"-
"t.ctree_test.C3Els[0]._y"->"t.ctree_test.C3Els[0].y"-
~("t.ctree_test.C3Els[0]._y")->"t.ctree_test.C3Els[0].y"+
~"t.ctree_test.C3Els[1].c1"&~"t.ctree_test.C3Els[1].c2"&~"t.ctree_test.C3Els[1].c3"->"t.ctree_test.C3Els[1]._y"+
"t.ctree_test.C3Els[1].c1"&"t.ctree_test.C3Els[1].c2"&"t.ctree_test.C3Els[1].c3"->"t.ctree_test.C3Els[1]._y"-
"t.ctree_test.C3Els[1]._y"->"t.ctree_test.C3Els[1].y"-
~("t.ctree_test.C3Els[1]._y")->"t.ctree_test.C3Els[1].y"+
~"t.ctree_test.C3Els[2].c1"&~"t.ctree_test.C3Els[2].c2"&~"t.ctree_test.C3Els[2].c3"->"t.ctree_test.C3Els[2]._y"+
"t.ctree_test.C3Els[2].c1"&"t.ctree_test.C3Els[2].c2"&"t.ctree_test.C3Els[2].c3"->"t.ctree_test.C3Els[2]._y"-
"t.ctree_test.C3Els[2]._y"->"t.ctree_test.C3Els[2].y"-
~("t.ctree_test.C3Els[2]._y")->"t.ctree_test.C3Els[2].y"+
= "t.ctree_test.tmp[15]" "t.ctree_test.C2Els[6].c1"
= "t.ctree_test.tmp[15]" "t.ctree_test.C2Els[0].y"
= "t.ctree_test.tmp[16]" "t.ctree_test.C2Els[6].c2"
= "t.ctree_test.tmp[16]" "t.ctree_test.C2Els[1].y"
= "t.ctree_test.tmp[17]" "t.ctree_test.C2Els[7].c1"
= "t.ctree_test.tmp[17]" "t.ctree_test.C2Els[2].y"
= "t.ctree_test.tmp[18]" "t.ctree_test.C2Els[7].c2"
= "t.ctree_test.tmp[18]" "t.ctree_test.C2Els[3].y"
= "t.ctree_test.tmp[19]" "t.ctree_test.C3Els[1].c1"
= "t.ctree_test.tmp[19]" "t.ctree_test.C2Els[4].y"
= "t.ctree_test.tmp[20]" "t.ctree_test.C3Els[1].c2"
= "t.ctree_test.tmp[20]" "t.ctree_test.C2Els[5].y"
= "t.ctree_test.tmp[21]" "t.ctree_test.C3Els[1].c3"
= "t.ctree_test.tmp[21]" "t.ctree_test.C3Els[0].y"
= "t.ctree_test.tmp[22]" "t.ctree_test.C3Els[2].c1"
= "t.ctree_test.tmp[22]" "t.ctree_test.C2Els[6].y"
= "t.ctree_test.tmp[23]" "t.ctree_test.C3Els[2].c2"
= "t.ctree_test.tmp[23]" "t.ctree_test.C2Els[7].y"
= "t.ctree_test.tmp[24]" "t.ctree_test.C3Els[2].c3"
= "t.ctree_test.tmp[24]" "t.ctree_test.C3Els[1].y"
= "t.ctree_test.supply.vdd" "t.ctree_test.C3Els[2].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C3Els[1].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C3Els[0].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[7].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[6].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[5].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[4].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[3].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[2].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[1].vdd"
= "t.ctree_test.supply.vdd" "t.ctree_test.C2Els[0].vdd"
= "t.ctree_test.supply.vss" "t.ctree_test.C3Els[2].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C3Els[1].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C3Els[0].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[7].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[6].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[5].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[4].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[3].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[2].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[1].vss"
= "t.ctree_test.supply.vss" "t.ctree_test.C2Els[0].vss"
= "t.ctree_test.in[0]" "t.ctree_test.C2Els[0].c1"
= "t.ctree_test.in[0]" "t.ctree_test.tmp[0]"
= "t.ctree_test.in[1]" "t.ctree_test.C2Els[0].c2"
= "t.ctree_test.in[1]" "t.ctree_test.tmp[1]"
= "t.ctree_test.in[2]" "t.ctree_test.C2Els[1].c1"
= "t.ctree_test.in[2]" "t.ctree_test.tmp[2]"
= "t.ctree_test.in[3]" "t.ctree_test.C2Els[1].c2"
= "t.ctree_test.in[3]" "t.ctree_test.tmp[3]"
= "t.ctree_test.in[4]" "t.ctree_test.C2Els[2].c1"
= "t.ctree_test.in[4]" "t.ctree_test.tmp[4]"
= "t.ctree_test.in[5]" "t.ctree_test.C2Els[2].c2"
= "t.ctree_test.in[5]" "t.ctree_test.tmp[5]"
= "t.ctree_test.in[6]" "t.ctree_test.C2Els[3].c1"
= "t.ctree_test.in[6]" "t.ctree_test.tmp[6]"
= "t.ctree_test.in[7]" "t.ctree_test.C2Els[3].c2"
= "t.ctree_test.in[7]" "t.ctree_test.tmp[7]"
= "t.ctree_test.in[8]" "t.ctree_test.C2Els[4].c1"
= "t.ctree_test.in[8]" "t.ctree_test.tmp[8]"
= "t.ctree_test.in[9]" "t.ctree_test.C2Els[4].c2"
= "t.ctree_test.in[9]" "t.ctree_test.tmp[9]"
= "t.ctree_test.in[10]" "t.ctree_test.C2Els[5].c1"
= "t.ctree_test.in[10]" "t.ctree_test.tmp[10]"
= "t.ctree_test.in[11]" "t.ctree_test.C2Els[5].c2"
= "t.ctree_test.in[11]" "t.ctree_test.tmp[11]"
= "t.ctree_test.in[12]" "t.ctree_test.C3Els[0].c1"
= "t.ctree_test.in[12]" "t.ctree_test.tmp[12]"
= "t.ctree_test.in[13]" "t.ctree_test.C3Els[0].c2"
= "t.ctree_test.in[13]" "t.ctree_test.tmp[13]"
= "t.ctree_test.in[14]" "t.ctree_test.C3Els[0].c3"
= "t.ctree_test.in[14]" "t.ctree_test.tmp[14]"
= "t.ctree_test.out" "t.ctree_test.C3Els[2].y"
= "t.ctree_test.out" "t.ctree_test.tmp[25]"
= "Vdd" "t.ctree_test.supply.vdd"
= "GND" "t.ctree_test.supply.vss"
= "t.out" "t.ctree_test.out"
= "t.in[0]" "t.ctree_test.in[0]"
= "t.in[1]" "t.ctree_test.in[1]"
= "t.in[2]" "t.ctree_test.in[2]"
= "t.in[3]" "t.ctree_test.in[3]"
= "t.in[4]" "t.ctree_test.in[4]"
= "t.in[5]" "t.ctree_test.in[5]"
= "t.in[6]" "t.ctree_test.in[6]"
= "t.in[7]" "t.ctree_test.in[7]"
= "t.in[8]" "t.ctree_test.in[8]"
= "t.in[9]" "t.ctree_test.in[9]"
= "t.in[10]" "t.ctree_test.in[10]"
= "t.in[11]" "t.ctree_test.in[11]"
= "t.in[12]" "t.ctree_test.in[12]"
= "t.in[13]" "t.ctree_test.in[13]"
= "t.in[14]" "t.ctree_test.in[14]"

41
test/unit_tests/ctree_15/test.act
View File

@@ -1,41 +0,0 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc ctree_15 (bool? in[15]; bool! out){
ctree<15> ctree_test(.in=in, .out=out);
ctree_test.supply.vss = GND;
ctree_test.supply.vdd = Vdd;
}
ctree_15 t;

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