65 lines
2.3 KiB
Verilog
65 lines
2.3 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0delayprog_34_4(out, in, Is0 , Is1 , Is2 , Is3 , vdd, vss);
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input vdd;
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input vss;
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output out;
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input in;
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input Is0 ;
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input Is1 ;
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input Is2 ;
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input Is3 ;
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// -- signals ---
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wire Idly5_a ;
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wire Idly7_a ;
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wire Is2 ;
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wire Idly0_a ;
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wire Is1 ;
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wire Is3 ;
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wire I_a3 ;
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wire Idly1_a ;
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wire in;
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wire Idly6_a ;
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wire Idly14_y ;
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wire I_a2 ;
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wire Is0 ;
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wire out ;
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wire Idly14_a ;
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wire Idly4_a ;
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wire I_a1 ;
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wire Idly2_a ;
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wire Idly10_a ;
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wire Idly2_y ;
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wire Idly12_a ;
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wire Idly9_a ;
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wire Idly6_y ;
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wire Idly0_y ;
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wire Idly3_a ;
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wire Idly11_a ;
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wire Idly13_a ;
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wire Idly8_a ;
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// --- instances
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AND2_X1 Iand20 (.y(Idly0_a ), .a(in), .b(Is0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand21 (.y(Idly1_a ), .a(I_a1 ), .b(Is1 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand22 (.y(Idly3_a ), .a(I_a2 ), .b(Is2 ), .vdd(vdd), .vss(vss));
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AND2_X1 Iand23 (.y(Idly7_a ), .a(I_a3 ), .b(Is3 ), .vdd(vdd), .vss(vss));
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MUX2_X1 Imu20 (.y(I_a1 ), .a(in), .b(Idly0_y ), .s(Is0 ), .vdd(vdd), .vss(vss));
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MUX2_X1 Imu21 (.y(I_a2 ), .a(I_a1 ), .b(Idly2_y ), .s(Is1 ), .vdd(vdd), .vss(vss));
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MUX2_X1 Imu22 (.y(I_a3 ), .a(I_a2 ), .b(Idly6_y ), .s(Is2 ), .vdd(vdd), .vss(vss));
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MUX2_X1 Imu23 (.y(out), .a(I_a3 ), .b(Idly14_y ), .s(Is3 ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly0 (.y(Idly0_y ), .a(Idly0_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly1 (.y(Idly2_a ), .a(Idly1_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly2 (.y(Idly2_y ), .a(Idly2_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly3 (.y(Idly4_a ), .a(Idly3_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly4 (.y(Idly5_a ), .a(Idly4_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly5 (.y(Idly6_a ), .a(Idly5_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly6 (.y(Idly6_y ), .a(Idly6_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly7 (.y(Idly8_a ), .a(Idly7_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly8 (.y(Idly9_a ), .a(Idly8_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly9 (.y(Idly10_a ), .a(Idly9_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly10 (.y(Idly11_a ), .a(Idly10_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly11 (.y(Idly12_a ), .a(Idly11_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly12 (.y(Idly13_a ), .a(Idly12_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly13 (.y(Idly14_a ), .a(Idly13_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly14 (.y(Idly14_y ), .a(Idly14_a ), .vdd(vdd), .vss(vss));
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endmodule |