115 lines
4.2 KiB
Verilog
115 lines
4.2 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0append_37_724_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d1 , Iout_d_d9_d1 , Iout_d_d10_d1 , Iout_d_d11_d1 , Iout_d_d12_d1 , Iout_d_d13_d1 , Iout_d_d14_d1 , Iout_d_d15_d1 , Iout_d_d16_d1 , Iout_d_d17_d1 , Iout_d_d18_d1 , Iout_d_d19_d1 , Iout_d_d20_d1 , Iout_d_d21_d1 , Iout_d_d22_d1 , Iout_d_d23_d1 , Iout_d_d24_d1 , Iout_d_d25_d1 , Iout_d_d26_d1 , Iout_d_d27_d1 , Iout_d_d28_d1 , Iout_d_d29_d1 , Iout_d_d30_d1 , Isupply_vss , vdd, vss);
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input vdd;
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input vss;
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input Iin_d_d0_d0 ;
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input Iin_d_d0_d1 ;
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input Iin_d_d1_d0 ;
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input Iin_d_d1_d1 ;
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input Iin_d_d2_d0 ;
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input Iin_d_d2_d1 ;
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input Iin_d_d3_d0 ;
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input Iin_d_d3_d1 ;
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input Iin_d_d4_d0 ;
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input Iin_d_d4_d1 ;
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input Iin_d_d5_d0 ;
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input Iin_d_d5_d1 ;
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input Iin_d_d6_d0 ;
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input Iin_d_d6_d1 ;
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input Isupply_vss ;
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// -- signals ---
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wire Iin_d_d0_d1 ;
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output Iout_d_d20_d1 ;
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wire Iin_d_d6_d0 ;
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output Iout_d_d30_d1 ;
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output Iout_d_d15_d1 ;
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wire Iin_d_d5_d0 ;
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output Iout_d_d22_d1 ;
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output Iout_d_d24_d1 ;
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wire Iin_d_d4_d0 ;
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output Iout_d_d29_d1 ;
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output Iout_d_d12_d1 ;
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output Iout_d_d11_d1 ;
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wire Iin_d_d2_d0 ;
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output Iout_d_d21_d1 ;
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output Iout_d_d18_d1 ;
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wire Iin_d_d0_d0 ;
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wire Iin_d_d5_d1 ;
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output Iout_d_d27_d1 ;
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output Iout_d_d19_d1 ;
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output Iout_d_d7_d0 ;
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wire Iin_d_d2_d1 ;
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wire Iin_d_d1_d0 ;
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output Iout_d_d17_d1 ;
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wire Iin_d_d6_d1 ;
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wire Isupply_vss ;
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output Iout_d_d26_d1 ;
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output Iout_d_d14_d1 ;
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output Iout_d_d13_d1 ;
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output Iout_d_d9_d1 ;
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wire Iin_d_d1_d1 ;
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wire Iin_d_d4_d1 ;
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output Iout_d_d28_d1 ;
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output Iout_d_d16_d1 ;
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wire Isb_in ;
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output Iout_d_d25_d1 ;
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output Iout_d_d8_d1 ;
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wire Iin_d_d3_d0 ;
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output Iout_d_d23_d1 ;
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output Iout_d_d7_d1 ;
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wire Iin_d_d3_d1 ;
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output Iout_d_d10_d1 ;
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// --- instances
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TIELO_X1 Itielows0 (.y(Iout_d_d7_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows1 (.y(Iout_d_d8_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows2 (.y(Iout_d_d9_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows3 (.y(Iout_d_d10_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows4 (.y(Iout_d_d11_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows5 (.y(Iout_d_d12_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows6 (.y(Iout_d_d13_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows7 (.y(Iout_d_d14_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows8 (.y(Iout_d_d15_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows9 (.y(Iout_d_d16_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows10 (.y(Iout_d_d17_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows11 (.y(Iout_d_d18_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows12 (.y(Iout_d_d19_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows13 (.y(Iout_d_d20_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows14 (.y(Iout_d_d21_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows15 (.y(Iout_d_d22_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows16 (.y(Iout_d_d23_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows17 (.y(Iout_d_d24_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows18 (.y(Iout_d_d25_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows19 (.y(Iout_d_d26_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows20 (.y(Iout_d_d27_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows21 (.y(Iout_d_d28_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows22 (.y(Iout_d_d29_d1 ), .vdd(vdd), .vss(vss));
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TIELO_X1 Itielows23 (.y(Iout_d_d30_d1 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0vtree_37_4 Iin_val (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_324_4 Isb (.in(Isb_in ), .Iout0 (Iout_d_d7_d0 ), .vdd(vdd), .vss(vss));
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endmodule |