112 lines
5.0 KiB
Verilog
112 lines
5.0 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0arbtree_315_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iin6_d_d0 , Iin6_a , Iin7_d_d0 , Iin7_a , Iin8_d_d0 , Iin8_a , Iin9_d_d0 , Iin9_a , Iin10_d_d0 , Iin10_a , Iin11_d_d0 , Iin11_a , Iin12_d_d0 , Iin12_a , Iin13_d_d0 , Iin13_a , Iin14_d_d0 , Iin14_a , Iout_d_d0 , Iout_a , vdd, vss);
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input vdd;
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input vss;
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input Iin0_d_d0 ;
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input Iin1_d_d0 ;
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input Iin2_d_d0 ;
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input Iin3_d_d0 ;
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input Iin4_d_d0 ;
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input Iin5_d_d0 ;
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input Iin6_d_d0 ;
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input Iin7_d_d0 ;
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input Iin8_d_d0 ;
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input Iin9_d_d0 ;
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input Iin10_d_d0 ;
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input Iin11_d_d0 ;
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input Iin12_d_d0 ;
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input Iin13_d_d0 ;
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input Iin14_d_d0 ;
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input Iout_a ;
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// -- signals ---
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output Iin14_a ;
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output Iin11_a ;
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wire Itmp24_d_d0 ;
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wire Itmp23_d_d0 ;
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output Iin7_a ;
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wire Itmp24_a ;
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wire Itmp17_a ;
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wire Iout_a ;
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wire Itmp27_d_d0 ;
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wire Iin8_d_d0 ;
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wire Iin5_d_d0 ;
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output Iin1_a ;
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wire Itmp16_a ;
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output Iin12_a ;
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wire Iin0_d_d0 ;
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output Iin9_a ;
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wire Itmp28_d_d0 ;
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wire Itmp26_a ;
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wire Itmp21_a ;
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wire Itmp17_d_d0 ;
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wire Itmp15_a ;
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wire Itmp25_a ;
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output Iin4_a ;
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output Iin8_a ;
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output Iin0_a ;
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wire Itmp20_a ;
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wire Itmp18_a ;
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wire Iin2_d_d0 ;
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output Iin2_a ;
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wire Itmp21_d_d0 ;
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wire Itmp16_d_d0 ;
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wire Iin12_d_d0 ;
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wire Itmp19_a ;
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wire Itmp15_d_d0 ;
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wire Iin4_d_d0 ;
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wire Itmp23_a ;
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output Iin10_a ;
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output Iin3_a ;
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wire Itmp28_a ;
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wire Itmp26_d_d0 ;
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output Iin13_a ;
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output Iout_d_d0 ;
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wire Iin6_d_d0 ;
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wire Iin1_d_d0 ;
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wire Iin14_d_d0 ;
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wire Itmp25_d_d0 ;
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wire Itmp20_d_d0 ;
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wire Iin9_d_d0 ;
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output Iin5_a ;
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wire Itmp19_d_d0 ;
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wire Iin7_d_d0 ;
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output Iin6_a ;
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wire Iin13_d_d0 ;
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wire Iin10_d_d0 ;
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wire Iin3_d_d0 ;
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wire Itmp27_a ;
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wire Iin11_d_d0 ;
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wire Itmp18_d_d0 ;
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// --- instances
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0 (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp15_d_d0 ), .Iout_a (Itmp15_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs1 (.Iin1_d_d0 (Iin2_d_d0 ), .Iin1_a (Iin2_a ), .Iin2_d_d0 (Iin3_d_d0 ), .Iin2_a (Iin3_a ), .Iout_d_d0 (Itmp16_d_d0 ), .Iout_a (Itmp16_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs2 (.Iin1_d_d0 (Iin4_d_d0 ), .Iin1_a (Iin4_a ), .Iin2_d_d0 (Iin5_d_d0 ), .Iin2_a (Iin5_a ), .Iout_d_d0 (Itmp17_d_d0 ), .Iout_a (Itmp17_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs3 (.Iin1_d_d0 (Iin6_d_d0 ), .Iin1_a (Iin6_a ), .Iin2_d_d0 (Iin7_d_d0 ), .Iin2_a (Iin7_a ), .Iout_d_d0 (Itmp18_d_d0 ), .Iout_a (Itmp18_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs4 (.Iin1_d_d0 (Iin8_d_d0 ), .Iin1_a (Iin8_a ), .Iin2_d_d0 (Iin9_d_d0 ), .Iin2_a (Iin9_a ), .Iout_d_d0 (Itmp19_d_d0 ), .Iout_a (Itmp19_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs5 (.Iin1_d_d0 (Iin10_d_d0 ), .Iin1_a (Iin10_a ), .Iin2_d_d0 (Iin11_d_d0 ), .Iin2_a (Iin11_a ), .Iout_d_d0 (Itmp20_d_d0 ), .Iout_a (Itmp20_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs6 (.Iin1_d_d0 (Iin12_d_d0 ), .Iin1_a (Iin12_a ), .Iin2_d_d0 (Iin13_d_d0 ), .Iin2_a (Iin13_a ), .Iout_d_d0 (Itmp21_d_d0 ), .Iout_a (Itmp21_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs7 (.Iin1_d_d0 (Itmp15_d_d0 ), .Iin1_a (Itmp15_a ), .Iin2_d_d0 (Itmp16_d_d0 ), .Iin2_a (Itmp16_a ), .Iout_d_d0 (Itmp23_d_d0 ), .Iout_a (Itmp23_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs8 (.Iin1_d_d0 (Itmp17_d_d0 ), .Iin1_a (Itmp17_a ), .Iin2_d_d0 (Itmp18_d_d0 ), .Iin2_a (Itmp18_a ), .Iout_d_d0 (Itmp24_d_d0 ), .Iout_a (Itmp24_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs9 (.Iin1_d_d0 (Itmp19_d_d0 ), .Iin1_a (Itmp19_a ), .Iin2_d_d0 (Itmp20_d_d0 ), .Iin2_a (Itmp20_a ), .Iout_d_d0 (Itmp25_d_d0 ), .Iout_a (Itmp25_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs10 (.Iin1_d_d0 (Itmp21_d_d0 ), .Iin1_a (Itmp21_a ), .Iin2_d_d0 (Iin14_d_d0 ), .Iin2_a (Iin14_a ), .Iout_d_d0 (Itmp26_d_d0 ), .Iout_a (Itmp26_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs11 (.Iin1_d_d0 (Itmp23_d_d0 ), .Iin1_a (Itmp23_a ), .Iin2_d_d0 (Itmp24_d_d0 ), .Iin2_a (Itmp24_a ), .Iout_d_d0 (Itmp27_d_d0 ), .Iout_a (Itmp27_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs12 (.Iin1_d_d0 (Itmp25_d_d0 ), .Iin1_a (Itmp25_a ), .Iin2_d_d0 (Itmp26_d_d0 ), .Iin2_a (Itmp26_a ), .Iout_d_d0 (Itmp28_d_d0 ), .Iout_a (Itmp28_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs13 (.Iin1_d_d0 (Itmp27_d_d0 ), .Iin1_a (Itmp27_a ), .Iin2_d_d0 (Itmp28_d_d0 ), .Iin2_a (Itmp28_a ), .Iout_d_d0 (Iout_d_d0 ), .Iout_a (Iout_a ), .vdd(vdd), .vss(vss));
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endmodule |