135 lines
4.4 KiB
Verilog
135 lines
4.4 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0ctree_332_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , Iin29 , Iin30 , Iin31 , out, vdd, vss);
|
|
input vdd;
|
|
input vss;
|
|
input Iin0 ;
|
|
input Iin1 ;
|
|
input Iin2 ;
|
|
input Iin3 ;
|
|
input Iin4 ;
|
|
input Iin5 ;
|
|
input Iin6 ;
|
|
input Iin7 ;
|
|
input Iin8 ;
|
|
input Iin9 ;
|
|
input Iin10 ;
|
|
input Iin11 ;
|
|
input Iin12 ;
|
|
input Iin13 ;
|
|
input Iin14 ;
|
|
input Iin15 ;
|
|
input Iin16 ;
|
|
input Iin17 ;
|
|
input Iin18 ;
|
|
input Iin19 ;
|
|
input Iin20 ;
|
|
input Iin21 ;
|
|
input Iin22 ;
|
|
input Iin23 ;
|
|
input Iin24 ;
|
|
input Iin25 ;
|
|
input Iin26 ;
|
|
input Iin27 ;
|
|
input Iin28 ;
|
|
input Iin29 ;
|
|
input Iin30 ;
|
|
input Iin31 ;
|
|
output out;
|
|
|
|
// -- signals ---
|
|
wire Itmp61 ;
|
|
wire Itmp51 ;
|
|
wire Iin21 ;
|
|
wire Itmp40 ;
|
|
wire Itmp59 ;
|
|
wire Itmp52 ;
|
|
wire Itmp36 ;
|
|
wire Itmp50 ;
|
|
wire Itmp42 ;
|
|
wire Itmp44 ;
|
|
wire Iin19 ;
|
|
wire Iin17 ;
|
|
wire Iin8 ;
|
|
wire Itmp49 ;
|
|
wire Itmp48 ;
|
|
wire Itmp45 ;
|
|
wire Itmp56 ;
|
|
wire Itmp54 ;
|
|
wire Iin20 ;
|
|
wire Itmp53 ;
|
|
wire Itmp46 ;
|
|
wire Itmp43 ;
|
|
wire Itmp39 ;
|
|
wire Itmp35 ;
|
|
wire Iin15 ;
|
|
wire Iin12 ;
|
|
wire Iin11 ;
|
|
wire Iin10 ;
|
|
wire Itmp33 ;
|
|
wire Iin27 ;
|
|
wire Iin16 ;
|
|
wire Iin13 ;
|
|
wire Iin2 ;
|
|
wire Itmp57 ;
|
|
wire Iin7 ;
|
|
wire Itmp58 ;
|
|
wire Iin5 ;
|
|
wire Iin25 ;
|
|
wire Iin22 ;
|
|
wire Iin31 ;
|
|
wire Itmp34 ;
|
|
wire Itmp38 ;
|
|
wire Iin1 ;
|
|
wire Itmp32 ;
|
|
wire out ;
|
|
wire Iin26 ;
|
|
wire Iin18 ;
|
|
wire Iin30 ;
|
|
wire Itmp41 ;
|
|
wire Itmp37 ;
|
|
wire Iin6 ;
|
|
wire Iin4 ;
|
|
wire Iin24 ;
|
|
wire Iin9 ;
|
|
wire Iin0 ;
|
|
wire Itmp60 ;
|
|
wire Iin23 ;
|
|
wire Itmp47 ;
|
|
wire Iin3 ;
|
|
wire Iin28 ;
|
|
wire Itmp55 ;
|
|
wire Iin14 ;
|
|
wire Iin29 ;
|
|
|
|
// --- instances
|
|
A_2C_B_X1 IC2Els0 (.y(Itmp32 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els1 (.y(Itmp33 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els2 (.y(Itmp34 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els3 (.y(Itmp35 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els4 (.y(Itmp36 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els5 (.y(Itmp37 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els6 (.y(Itmp38 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els7 (.y(Itmp39 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els8 (.y(Itmp40 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els9 (.y(Itmp41 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els10 (.y(Itmp42 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els11 (.y(Itmp43 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els12 (.y(Itmp44 ), .c1(Iin24 ), .c2(Iin25 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els13 (.y(Itmp45 ), .c1(Iin26 ), .c2(Iin27 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els14 (.y(Itmp46 ), .c1(Iin28 ), .c2(Iin29 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els15 (.y(Itmp47 ), .c1(Iin30 ), .c2(Iin31 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els16 (.y(Itmp48 ), .c1(Itmp32 ), .c2(Itmp33 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els17 (.y(Itmp49 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els18 (.y(Itmp50 ), .c1(Itmp36 ), .c2(Itmp37 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els19 (.y(Itmp51 ), .c1(Itmp38 ), .c2(Itmp39 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els20 (.y(Itmp52 ), .c1(Itmp40 ), .c2(Itmp41 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els21 (.y(Itmp53 ), .c1(Itmp42 ), .c2(Itmp43 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els22 (.y(Itmp54 ), .c1(Itmp44 ), .c2(Itmp45 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els23 (.y(Itmp55 ), .c1(Itmp46 ), .c2(Itmp47 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els24 (.y(Itmp56 ), .c1(Itmp48 ), .c2(Itmp49 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els25 (.y(Itmp57 ), .c1(Itmp50 ), .c2(Itmp51 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els26 (.y(Itmp58 ), .c1(Itmp52 ), .c2(Itmp53 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els27 (.y(Itmp59 ), .c1(Itmp54 ), .c2(Itmp55 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els28 (.y(Itmp60 ), .c1(Itmp56 ), .c2(Itmp57 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els29 (.y(Itmp61 ), .c1(Itmp58 ), .c2(Itmp59 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els30 (.y(out), .c1(Itmp60 ), .c2(Itmp61 ), .vdd(vdd), .vss(vss));
|
|
endmodule |