80 lines
4.3 KiB
Verilog
80 lines
4.3 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail_36_78_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iin_d4_d0 , Iin_d4_d1 , Iin_d5_d0 , Iin_d5_d1 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , vdd, vss);
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input vdd;
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input vss;
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input Iin_d0_d0 ;
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input Iin_d0_d1 ;
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input Iin_d1_d0 ;
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input Iin_d1_d1 ;
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input Iin_d2_d0 ;
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input Iin_d2_d1 ;
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input Iin_d3_d0 ;
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input Iin_d3_d1 ;
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input Iin_d4_d0 ;
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input Iin_d4_d1 ;
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input Iin_d5_d0 ;
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input Iin_d5_d1 ;
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// -- signals ---
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wire Iin_d3_d1 ;
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wire Iatree7_in2 ;
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wire Iatree5_in1 ;
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wire Iin_d5_d0 ;
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output Iout0 ;
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output Iout6 ;
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wire Iatree6_in0 ;
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wire Iin_tX5_out0 ;
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output Iout7 ;
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wire Iatree3_in2 ;
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wire Iin_d1_d0 ;
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wire Iatree7_in1 ;
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wire Iin_tX3_out0 ;
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wire Iatree7_in0 ;
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wire Iin_d0_d0 ;
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wire Iin_d2_d0 ;
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wire Iin_d1_d1 ;
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output Iout5 ;
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output Iout3 ;
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wire Iatree7_in4 ;
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output Iout2 ;
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wire Iin_d4_d0 ;
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wire Iin_tX4_out0 ;
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wire Iin_d2_d1 ;
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wire Iin_d5_d1 ;
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wire Iin_d0_d1 ;
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wire Iatree7_in5 ;
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wire Iin_d3_d0 ;
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wire Iin_d4_d1 ;
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output Iout4 ;
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output Iout1 ;
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wire Iatree7_in3 ;
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// --- instances
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tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree0 (.Iin0 (Iatree6_in0 ), .Iin1 (Iatree5_in1 ), .Iin2 (Iatree3_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree1 (.Iin0 (Iatree7_in0 ), .Iin1 (Iatree5_in1 ), .Iin2 (Iatree3_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout1 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree2 (.Iin0 (Iatree6_in0 ), .Iin1 (Iatree7_in1 ), .Iin2 (Iatree3_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout2 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree3 (.Iin0 (Iatree7_in0 ), .Iin1 (Iatree7_in1 ), .Iin2 (Iatree3_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout3 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree4 (.Iin0 (Iatree6_in0 ), .Iin1 (Iatree5_in1 ), .Iin2 (Iatree7_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout4 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree5 (.Iin0 (Iatree7_in0 ), .Iin1 (Iatree5_in1 ), .Iin2 (Iatree7_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout5 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree6 (.Iin0 (Iatree6_in0 ), .Iin1 (Iatree7_in1 ), .Iin2 (Iatree7_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout6 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_36_4 Iatree7 (.Iin0 (Iatree7_in0 ), .Iin1 (Iatree7_in1 ), .Iin2 (Iatree7_in2 ), .Iin3 (Iatree7_in3 ), .Iin4 (Iatree7_in4 ), .Iin5 (Iatree7_in5 ), .out(Iout7 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX0 (.in(Iin_d0_d1 ), .Iout0 (Iatree7_in0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX1 (.in(Iin_d1_d1 ), .Iout0 (Iatree7_in1 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX2 (.in(Iin_d2_d1 ), .Iout0 (Iatree7_in2 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX3 (.in(Iin_d3_d1 ), .Iout0 (Iin_tX3_out0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX4 (.in(Iin_d4_d1 ), .Iout0 (Iin_tX4_out0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_tX5 (.in(Iin_d5_d1 ), .Iout0 (Iin_tX5_out0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX0 (.in(Iin_d0_d0 ), .Iout0 (Iatree6_in0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX1 (.in(Iin_d1_d0 ), .Iout0 (Iatree5_in1 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX2 (.in(Iin_d2_d0 ), .Iout0 (Iatree3_in2 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX3 (.in(Iin_d3_d0 ), .Iout0 (Iatree7_in3 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX4 (.in(Iin_d4_d0 ), .Iout0 (Iatree7_in4 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_38_4 Iin_fX5 (.in(Iin_d5_d0 ), .Iout0 (Iatree7_in5 ), .vdd(vdd), .vss(vss));
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endmodule |