93 lines
5.2 KiB
Verilog
93 lines
5.2 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_34_715_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , Iout8 , Iout9 , Iout10 , Iout11 , Iout12 , Iout13 , Iout14 , Ifinal_refresh_d0_d0 , Ifinal_refresh_d0_d1 , Ifinal_refresh_d1_d0 , Ifinal_refresh_d1_d1 , Ifinal_refresh_d2_d0 , Ifinal_refresh_d2_d1 , Ifinal_refresh_d3_d0 , Ifinal_refresh_d3_d1 , vdd, vss);
|
|
input vdd;
|
|
input vss;
|
|
input Iin_d0_d0 ;
|
|
input Iin_d0_d1 ;
|
|
input Iin_d1_d0 ;
|
|
input Iin_d1_d1 ;
|
|
input Iin_d2_d0 ;
|
|
input Iin_d2_d1 ;
|
|
input Iin_d3_d0 ;
|
|
input Iin_d3_d1 ;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// -- signals ---
|
|
wire Iin_d2_d0 ;
|
|
output Ifinal_refresh_d0_d0 ;
|
|
wire Iin_d2_d1 ;
|
|
wire Iin_d0_d1 ;
|
|
output Iout8 ;
|
|
output Iout13 ;
|
|
output Ifinal_refresh_d1_d1 ;
|
|
output Iout9 ;
|
|
output Ifinal_refresh_d3_d1 ;
|
|
wire Iin_d0_d0 ;
|
|
output Iout10 ;
|
|
output Ifinal_refresh_d0_d1 ;
|
|
output Ifinal_refresh_d2_d0 ;
|
|
output Iout11 ;
|
|
output Iout6 ;
|
|
output Iout5 ;
|
|
output Iout4 ;
|
|
output Iout3 ;
|
|
wire Iin_d1_d1 ;
|
|
output Iout12 ;
|
|
output Iout2 ;
|
|
output Ifinal_refresh_d3_d0 ;
|
|
wire Iin_d3_d0 ;
|
|
output Iout1 ;
|
|
output Iout0 ;
|
|
wire Iin_d3_d1 ;
|
|
output Ifinal_refresh_d1_d0 ;
|
|
output Ifinal_refresh_d2_d1 ;
|
|
output Iout14 ;
|
|
wire Iin_d1_d0 ;
|
|
output Iout7 ;
|
|
|
|
// --- instances
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree1 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout1 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree2 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout2 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree3 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout3 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree4 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout4 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree5 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout5 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree6 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout6 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree7 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d0 ), .out(Iout7 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree8 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout8 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree9 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout9 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree10 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout10 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree11 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout11 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree12 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout12 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree13 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout13 ), .vdd(vdd), .vss(vss));
|
|
tmpl_0_0dataflow__neuro_0_0andtree_34_4 Iatree14 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d1 ), .Iin3 (Ifinal_refresh_d3_d1 ), .out(Iout14 ), .vdd(vdd), .vss(vss));
|
|
BUF_X12 Iin_tX0 (.y(Ifinal_refresh_d0_d1 ), .a(Iin_d0_d1 ), .vdd(vdd), .vss(vss));
|
|
BUF_X12 Iin_tX1 (.y(Ifinal_refresh_d1_d1 ), .a(Iin_d1_d1 ), .vdd(vdd), .vss(vss));
|
|
BUF_X12 Iin_tX2 (.y(Ifinal_refresh_d2_d1 ), .a(Iin_d2_d1 ), .vdd(vdd), .vss(vss));
|
|
BUF_X12 Iin_tX3 (.y(Ifinal_refresh_d3_d1 ), .a(Iin_d3_d1 ), .vdd(vdd), .vss(vss));
|
|
BUF_X12 Iin_fX0 (.y(Ifinal_refresh_d0_d0 ), .a(Iin_d0_d0 ), .vdd(vdd), .vss(vss));
|
|
BUF_X12 Iin_fX1 (.y(Ifinal_refresh_d1_d0 ), .a(Iin_d1_d0 ), .vdd(vdd), .vss(vss));
|
|
BUF_X12 Iin_fX2 (.y(Ifinal_refresh_d2_d0 ), .a(Iin_d2_d0 ), .vdd(vdd), .vss(vss));
|
|
BUF_X12 Iin_fX3 (.y(Ifinal_refresh_d3_d0 ), .a(Iin_d3_d0 ), .vdd(vdd), .vss(vss));
|
|
endmodule |