actlib_dataflow_neuro/test/unit_tests/texel_dualcore_glue_slimreg/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf_314_4/netlist/verilog.v

module tmpl_0_0dataflow__neuro_0_0sigbuf_314_4(in, Iout0 , vdd, vss); 
   input vdd;
   input vss;
   input in;
   

// -- signals ---
   wire in;
   output Iout0 ;

// --- instances
BUF_X4 Ibuf4  (.y(Iout0 ), .a(in), .vdd(vdd), .vss(vss));
endmodule