actlib_dataflow_neuro/test/unit_tests/texel_dualcore_glue_slimreg/split_modules/tmpl_0_0dataflow__neuro_0_0vtree_323_4/netlist/verilog.v

module tmpl_0_0dataflow__neuro_0_0vtree_323_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iin_d4_d0 , Iin_d4_d1 , Iin_d5_d0 , Iin_d5_d1 , Iin_d6_d0 , Iin_d6_d1 , Iin_d7_d0 , Iin_d7_d1 , Iin_d8_d0 , Iin_d8_d1 , Iin_d9_d0 , Iin_d9_d1 , Iin_d10_d0 , Iin_d10_d1 , Iin_d11_d0 , Iin_d11_d1 , Iin_d12_d0 , Iin_d12_d1 , Iin_d13_d0 , Iin_d13_d1 , Iin_d14_d0 , Iin_d14_d1 , Iin_d15_d0 , Iin_d15_d1 , Iin_d16_d0 , Iin_d16_d1 , Iin_d17_d0 , Iin_d17_d1 , Iin_d18_d0 , Iin_d18_d1 , Iin_d19_d0 , Iin_d19_d1 , Iin_d20_d0 , Iin_d20_d1 , Iin_d21_d0 , Iin_d21_d1 , Iin_d22_d0 , Iin_d22_d1 , out, vdd, vss); 
   input vdd;
   input vss;
   input Iin_d0_d0 ;
   input Iin_d0_d1 ;
   input Iin_d1_d0 ;
   input Iin_d1_d1 ;
   input Iin_d2_d0 ;
   input Iin_d2_d1 ;
   input Iin_d3_d0 ;
   input Iin_d3_d1 ;
   input Iin_d4_d0 ;
   input Iin_d4_d1 ;
   input Iin_d5_d0 ;
   input Iin_d5_d1 ;
   input Iin_d6_d0 ;
   input Iin_d6_d1 ;
   input Iin_d7_d0 ;
   input Iin_d7_d1 ;
   input Iin_d8_d0 ;
   input Iin_d8_d1 ;
   input Iin_d9_d0 ;
   input Iin_d9_d1 ;
   input Iin_d10_d0 ;
   input Iin_d10_d1 ;
   input Iin_d11_d0 ;
   input Iin_d11_d1 ;
   input Iin_d12_d0 ;
   input Iin_d12_d1 ;
   input Iin_d13_d0 ;
   input Iin_d13_d1 ;
   input Iin_d14_d0 ;
   input Iin_d14_d1 ;
   input Iin_d15_d0 ;
   input Iin_d15_d1 ;
   input Iin_d16_d0 ;
   input Iin_d16_d1 ;
   input Iin_d17_d0 ;
   input Iin_d17_d1 ;
   input Iin_d18_d0 ;
   input Iin_d18_d1 ;
   input Iin_d19_d0 ;
   input Iin_d19_d1 ;
   input Iin_d20_d0 ;
   input Iin_d20_d1 ;
   input Iin_d21_d0 ;
   input Iin_d21_d1 ;
   input Iin_d22_d0 ;
   input Iin_d22_d1 ;
   output out;

// -- signals ---
   wire Iin_d4_d0 ;
   wire Ict_in15 ;
   wire Ict_in13 ;
   wire Ict_in1 ;
   wire Iin_d16_d1 ;
   wire Ict_in22 ;
   wire Ict_in5 ;
   wire Iin_d22_d0 ;
   wire Iin_d2_d1 ;
   wire Iin_d1_d1 ;
   wire Ict_in9 ;
   wire Iin_d18_d1 ;
   wire Iin_d6_d0 ;
   wire Iin_d1_d0 ;
   wire Ict_in21 ;
   wire Iin_d22_d1 ;
   wire Iin_d9_d0 ;
   wire Iin_d7_d1 ;
   wire Iin_d0_d0 ;
   wire Iin_d14_d0 ;
   wire Iin_d4_d1 ;
   wire Iin_d3_d1 ;
   wire Iin_d15_d1 ;
   wire Ict_in19 ;
   wire Ict_in10 ;
   wire Iin_d20_d0 ;
   wire Iin_d3_d0 ;
   wire Iin_d2_d0 ;
   wire Iin_d0_d1 ;
   wire Ict_in8 ;
   wire Iin_d17_d1 ;
   wire Iin_d5_d0 ;
   wire Ict_in2 ;
   wire Ict_in6 ;
   wire Iin_d15_d0 ;
   wire Iin_d13_d0 ;
   wire Iin_d13_d1 ;
   wire Iin_d12_d1 ;
   wire Iin_d8_d0 ;
   wire Iin_d7_d0 ;
   wire out ;
   wire Iin_d21_d1 ;
   wire Iin_d20_d1 ;
   wire Iin_d12_d0 ;
   wire Iin_d11_d0 ;
   wire Ict_in11 ;
   wire Ict_in18 ;
   wire Iin_d21_d0 ;
   wire Iin_d8_d1 ;
   wire Ict_in14 ;
   wire Ict_in7 ;
   wire Iin_d18_d0 ;
   wire Iin_d16_d0 ;
   wire Iin_d9_d1 ;
   wire Iin_d5_d1 ;
   wire Iin_d6_d1 ;
   wire Ict_in4 ;
   wire Iin_d10_d0 ;
   wire Iin_d19_d0 ;
   wire Ict_in20 ;
   wire Iin_d19_d1 ;
   wire Iin_d17_d0 ;
   wire Iin_d14_d1 ;
   wire Ict_in12 ;
   wire Ict_in0 ;
   wire Iin_d11_d1 ;
   wire Ict_in17 ;
   wire Ict_in3 ;
   wire Iin_d10_d1 ;
   wire Ict_in16 ;

// --- instances
tmpl_0_0dataflow__neuro_0_0ctree_323_4 Ict  (.Iin0 (Ict_in0 ), .Iin1 (Ict_in1 ), .Iin2 (Ict_in2 ), .Iin3 (Ict_in3 ), .Iin4 (Ict_in4 ), .Iin5 (Ict_in5 ), .Iin6 (Ict_in6 ), .Iin7 (Ict_in7 ), .Iin8 (Ict_in8 ), .Iin9 (Ict_in9 ), .Iin10 (Ict_in10 ), .Iin11 (Ict_in11 ), .Iin12 (Ict_in12 ), .Iin13 (Ict_in13 ), .Iin14 (Ict_in14 ), .Iin15 (Ict_in15 ), .Iin16 (Ict_in16 ), .Iin17 (Ict_in17 ), .Iin18 (Ict_in18 ), .Iin19 (Ict_in19 ), .Iin20 (Ict_in20 ), .Iin21 (Ict_in21 ), .Iin22 (Ict_in22 ), .out(out), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf0  (.y(Ict_in0 ), .a(Iin_d0_d1 ), .b(Iin_d0_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf1  (.y(Ict_in1 ), .a(Iin_d1_d1 ), .b(Iin_d1_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf2  (.y(Ict_in2 ), .a(Iin_d2_d1 ), .b(Iin_d2_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf3  (.y(Ict_in3 ), .a(Iin_d3_d1 ), .b(Iin_d3_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf4  (.y(Ict_in4 ), .a(Iin_d4_d1 ), .b(Iin_d4_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf5  (.y(Ict_in5 ), .a(Iin_d5_d1 ), .b(Iin_d5_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf6  (.y(Ict_in6 ), .a(Iin_d6_d1 ), .b(Iin_d6_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf7  (.y(Ict_in7 ), .a(Iin_d7_d1 ), .b(Iin_d7_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf8  (.y(Ict_in8 ), .a(Iin_d8_d1 ), .b(Iin_d8_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf9  (.y(Ict_in9 ), .a(Iin_d9_d1 ), .b(Iin_d9_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf10  (.y(Ict_in10 ), .a(Iin_d10_d1 ), .b(Iin_d10_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf11  (.y(Ict_in11 ), .a(Iin_d11_d1 ), .b(Iin_d11_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf12  (.y(Ict_in12 ), .a(Iin_d12_d1 ), .b(Iin_d12_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf13  (.y(Ict_in13 ), .a(Iin_d13_d1 ), .b(Iin_d13_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf14  (.y(Ict_in14 ), .a(Iin_d14_d1 ), .b(Iin_d14_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf15  (.y(Ict_in15 ), .a(Iin_d15_d1 ), .b(Iin_d15_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf16  (.y(Ict_in16 ), .a(Iin_d16_d1 ), .b(Iin_d16_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf17  (.y(Ict_in17 ), .a(Iin_d17_d1 ), .b(Iin_d17_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf18  (.y(Ict_in18 ), .a(Iin_d18_d1 ), .b(Iin_d18_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf19  (.y(Ict_in19 ), .a(Iin_d19_d1 ), .b(Iin_d19_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf20  (.y(Ict_in20 ), .a(Iin_d20_d1 ), .b(Iin_d20_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf21  (.y(Ict_in21 ), .a(Iin_d21_d1 ), .b(Iin_d21_d0 ), .vdd(vdd), .vss(vss));
OR2_X1 IOR2_tf22  (.y(Ict_in22 ), .a(Iin_d22_d1 ), .b(Iin_d22_d0 ), .vdd(vdd), .vss(vss));
endmodule