115 lines
5.2 KiB
Plaintext
115 lines
5.2 KiB
Plaintext
/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/cell_lib_async.act";
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import "../../dataflow_neuro/cell_lib_std.act";
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import "../../dataflow_neuro/treegates.act";
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import "../../dataflow_neuro/primitives.act";
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import "../../dataflow_neuro/coders.act";
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// import tmpl::dataflow_neuro;
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// import tmpl::dataflow_neuro;
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import std::channel;
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open std::channel;
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namespace tmpl {
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namespace dataflow_neuro {
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// Circuit for storing, reading and writing registers using AER
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// The block has the parameters:
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// lognw -> log2(number of words), parameters you can store
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// wl -> word length, length of each word
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// N_dly_cfg -> the number of config bits in the ACK delay line
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// The block has the pins:
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// in -> input data,
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// - the first bit is write/read_B
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// - the next lognw bits describe the location,
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// - the last wl the word to write
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// data -> the data saved in the flip flop, sized wl x nw
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export template<pint lognw,wl,N_dly_cfg>
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defproc register_rw (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
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bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
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pint nw = 1<<lognw;
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//Validation of the input
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Mx1of2<1+lognw+wl> _in_temp;
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(i:1+lognw+wl:_in_temp.d[i] = in.d.d[i];)
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vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
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sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
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// Generation of the fake clock pulse
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delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
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INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
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sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
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// Sending back to the ackowledge
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delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
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sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
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//Reset Buffers
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bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
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BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
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sigbuf<nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
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// Creating the different flip flop arrays
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bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
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andtree<lognw> atree[nw];
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AND2_X1 and_encoder[nw];
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sigbuf<wl> clock_buffer[nw];
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DFFQ_R_X1 ff[nw*wl];
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pint bitval;
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(k:nw:atree[k].supply = supply;)
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(word_idx:nw:
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// Decoding the bit pattern to understand which word we are looking at
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(pin_idx:lognw:
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bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
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[bitval = 1 ->
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atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
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[] bitval = 0 ->
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atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
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[]bitval >= 2 -> {false : "fuck"};
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]
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)
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// Activating the fake clock for the right word
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atree[word_idx].out = _out_encoder[word_idx];
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and_encoder[word_idx].a = _out_encoder[word_idx];
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and_encoder[word_idx].b = _clock;
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and_encoder[word_idx].y = _clock_word_temp[word_idx];
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and_encoder[word_idx].vdd = supply.vdd;
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and_encoder[word_idx].vss = supply.vss;
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clock_buffer[word_idx].in = _clock_word_temp[word_idx];
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clock_buffer[word_idx].supply = supply;
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// Describing all the FF and their connection
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(bit_idx:wl:
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ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
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ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
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ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
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ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
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ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
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ff[bit_idx+word_idx*(wl)].vss = supply.vss;
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)
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)
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}
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}}
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