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register_write works

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This commit is contained in:
M. Mastella 2022-03-07 16:36:01 +01:00
parent ad318259a5
commit e49866323c
8 changed files with 598 additions and 837 deletions
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16
dataflow_neuro/cell_lib_std.act
View File

@ -373,22 +373,22 @@ namespace tmpl {
}
sizing { _en{-2}; y{-2,2} }
}
export defproc DFFQ_R_X1 (bool? clk, reset_B, d; bool! q; bool? vdd,vss)
export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q; bool? vdd,vss)
{
bool _clk, __clk, _mqi,_mqib,_sqi,_sqib;
bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;
prs {
// Creating delayed versions of the clock
clk => _clk-
_clk => __clk-
clk_B => _clk_B-
_clk_B => __clk_B-
(~d & ~_clk)|(~reset_B)|(~__clk&~_mqi) -> _mqib+
(d & __clk)|(reset_B & _mqi & _clk) -> _mqib-
(~d & ~_clk_B)|(~reset_B)|(~__clk_B&~_mqi) -> _mqib+
((d & __clk_B)|(_mqi & _clk_B))&reset_B -> _mqib-
_mqib => _mqi-
(~_mqi &~__clk)|(~reset_B)|(~_sqi&~_clk) -> _sqib+
(_mqi &_clk)|(_sqi&__clk&reset_B) -> _sqib-
(~_mqi &~__clk_B)|(~reset_B)|(~_sqi&~_clk_B) -> _sqib+
((_mqi &_clk_B)|(_sqi&__clk_B))&reset_B -> _sqib-
_sqib => _sqi-
_sqib => q-

86
dataflow_neuro/registers.act
View File

@ -41,72 +41,72 @@ namespace tmpl {
namespace dataflow_neuro {
// Circuit for storing, reading and writing registers using AER
// The block has the parameters:
// log_nw -> log2(number of words), parameters you can store
// lognw -> log2(number of words), parameters you can store
// wl -> word length, length of each word
// N_dly_cfg -> the number of config bits in the ACK delay line
// The block has the pins:
// in -> input data,
// - the first bit is write/read_B
// - the next log_nw bits describe the location,
// - the next lognw bits describe the location,
// - the last wl the word to write
// data -> the data saved in the flip flop, sized wl x nw
export template<pint log_nw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+log_nw+wl> in; d1of<wl> data[2<<log_nw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock;
pint _nw = 2<<log_nw;
export template<pint lognw,wl,N_dly_cfg>
defproc register_rw (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
pint nw = 1<<lognw;
//Validation of the input
Mx1of2<1+log_nw+wl> _in_temp;
(i:1+log_nw+wl:_in_temp.d[i] = in.d.d[i];)
vtree<1+log_nw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
Mx1of2<1+lognw+wl> _in_temp;
(i:1+lognw+wl:_in_temp.d[i] = in.d.d[i];)
vtree<1+lognw+wl> val_input(.in = _in_temp,.out = _in_v_temp, .supply = supply);
sigbuf_1output<4> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
// Generation of the fake clock pulse
delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
// Sending back to the ackowledge
delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
//Reset Buffers
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[_nw*wl];
bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<_nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
sigbuf<nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
// Creating the different flip flop arrays
bool _out_encoder[_nw],_clock_word_temp[_nw],_clock_word[_nw],_clock_buffer_out[_nw*wl];
andtree<log_nw> atree[_nw];
AND2_X1 and_encoder[_nw];
sigbuf<wl> clock_buffer[_nw];
DFFQ_R_X1 ff[_nw*wl];
pint _bitval;
(k:_nw:atree[k].supply = supply;)
(_word_idx:_nw:
bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
andtree<lognw> atree[nw];
AND2_X1 and_encoder[nw];
sigbuf<wl> clock_buffer[nw];
DFFQ_R_X1 ff[nw*wl];
pint bitval;
(k:nw:atree[k].supply = supply;)
(word_idx:nw:
// Decoding the bit pattern to understand which word we are looking at
(pin_idx:log_nw:
_bitval = (_word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
[_bitval = 1 ->
atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
[] _bitval = 0 ->
atree[_word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
[]_bitval >= 2 -> {false : "fuck"};
(pin_idx:lognw:
bitval = (word_idx & ( 1 << pin_idx )) >> pin_idx; // Get binary digit of integer i, column j
[bitval = 1 ->
atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].t;
[] bitval = 0 ->
atree[word_idx].in[pin_idx] = in.d.d[pin_idx+wl].f;
[]bitval >= 2 -> {false : "fuck"};
]
)
// Activating the fake clock for the right word
atree[_word_idx].out = _out_encoder[_word_idx];
and_encoder[_word_idx].a = _out_encoder[_word_idx];
and_encoder[_word_idx].b = _clock;
and_encoder[_word_idx].y = _clock_word_temp[_word_idx];
and_encoder[_word_idx].vdd = supply.vdd;
and_encoder[_word_idx].vss = supply.vss;
clock_buffer[_word_idx].in = _clock_word_temp[_word_idx];
clock_buffer[_word_idx].supply = supply;
atree[word_idx].out = _out_encoder[word_idx];
and_encoder[word_idx].a = _out_encoder[word_idx];
and_encoder[word_idx].b = _clock;
and_encoder[word_idx].y = _clock_word_temp[word_idx];
and_encoder[word_idx].vdd = supply.vdd;
and_encoder[word_idx].vss = supply.vss;
clock_buffer[word_idx].in = _clock_word_temp[word_idx];
clock_buffer[word_idx].supply = supply;
// Describing all the FF and their connection
(_bit_idx:wl:
clock_buffer[_word_idx].out[_bit_idx] = _clock_buffer_out[_bit_idx*(1+_word_idx)];
// ff[_bit_idx*(1+_word_idx)].clk = _clock_buffer_out[_bit_idx*(1+_word_idx)];
// ff[_bit_idx*(1+_word_idx)].d = in.d.d[_bit_idx+1+log_nw].t;
// ff[_bit_idx*(1+_word_idx)].q = data[_word_idx].d[_bit_idx];
// ff[_bit_idx*(1+_word_idx)].reset_B = _reset_mem_BXX[_bit_idx*(1+_word_idx)];
// ff[_bit_idx*(1+_word_idx)].vdd = supply.vdd;
// ff[_bit_idx*(1+_word_idx)].vss = supply.vss;
(bit_idx:wl:
ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
ff[bit_idx+word_idx*(wl)].vss = supply.vss;
)
)
}

76
test/unit_tests/flipflop/run/prsim.out
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@ -1,35 +1,57 @@
t.ff._mqib t.clk t.d t.q t.ff._sqib t.ff._sqi t.ff.__clk t.ff._mqi t.ff._clk
[0] start test
1 t.d : 0
1 Reset : 0
1 t.clk : 0
7093 t.ff._mqib : 1 [by t.d:=0]
7095 t.ff._mqi : 0 [by t.ff._mqib:=1]
1 t.d : 0
3 t.ff._mqib : 1 [by t.d:=0]
4756 t.ff._mqi : 0 [by t.ff._mqib:=1]
5893 t.ff._sqib : 1 [by t.ff._mqi:=0]
6007 t.ff._sqi : 0 [by t.ff._sqib:=1]
7093 t._reset_B : 1 [by Reset:=0]
10468 t.ff._clk : 1 [by t.clk:=0]
11605 t.ff.__clk : 0 [by t.ff._clk:=1]
11848 t.ff._sqib : 1 [by t.ff._mqi:=0]
11962 t.ff._sqi : 0 [by t.ff._sqib:=1]
77214 t.q : 0 [by t.ff._sqib:=1]
12194 t.ff.__clk : 0 [by t.ff._clk:=1]
71259 t.q : 0 [by t.ff._sqib:=1]
77214 Reset : 0
78940 t._reset_B : 1 [by Reset:=0]
[1] reset completed
78940 t.clk : 1
78979 t.ff._clk : 0 [by t.clk:=1]
78994 t.ff.__clk : 1 [by t.ff._clk:=0]
71259 t.clk : 1
71298 t.ff._clk : 0 [by t.clk:=1]
71313 t.ff.__clk : 1 [by t.ff._clk:=0]
[2] tested d = 0, clk rise
78994 t.clk : 0
79485 t.ff._clk : 1 [by t.clk:=0]
79498 t.ff.__clk : 0 [by t.ff._clk:=1]
79498 t.d : 1
79498 t.clk : 1
79538 t.ff._clk : 0 [by t.clk:=1]
79953 t.ff.__clk : 1 [by t.ff._clk:=0]
79973 t.ff._mqib : 0 [by t.ff.__clk:=1]
86034 t.ff._mqi : 1 [by t.ff._mqib:=0]
86034 t.clk : 0
86081 t.ff._clk : 1 [by t.clk:=0]
86097 t.ff.__clk : 0 [by t.ff._clk:=1]
130179 t.ff._sqib : 0 [by t.ff._clk:=1]
130183 t.q : 1 [by t.ff._sqib:=0]
143903 t.ff._sqi : 1 [by t.ff._sqib:=0]
71313 t.clk : 0
71804 t.ff._clk : 1 [by t.clk:=0]
71817 t.ff.__clk : 0 [by t.ff._clk:=1]
71817 t.d : 1
71817 t.clk : 1
71857 t.ff._clk : 0 [by t.clk:=1]
72272 t.ff.__clk : 1 [by t.ff._clk:=0]
72292 t.ff._mqib : 0 [by t.ff.__clk:=1]
78353 t.ff._mqi : 1 [by t.ff._mqib:=0]
78353 t.d : 0
78353 t.clk : 0
WARNING: unstable `t.ff._mqib'+
>> cause: t.ff._clk (val: 1)
78369 t.ff._clk : 1 [by t.clk:=0]
WARNING: weak-interference `t.ff._mqi'
>> cause: t.ff._mqib (val: X)
>> time: 78400
78400 t.ff._mqib : X [by t.ff._clk:=1]
78404 t.ff._mqib : 0 [by t.ff._clk:=1]
WARNING: weak-unstable `t.ff._sqib'-
>> cause: t.ff._mqi (val: X)
>> time: 87529
87529 t.ff._mqi : X [by t.ff._mqib:=0]
87544 t.ff._mqi : 1 [by t.ff._mqib:=0]
WARNING: weak-interference `t.ff._sqi'
>> cause: t.ff._sqib (val: X)
>> time: 92093
WARNING: weak-interference `t.q'
>> cause: t.ff._sqib (val: X)
>> time: 92093
92093 t.ff._sqib : X [by t.ff._mqi:=1]
92148 t.q : X [by t.ff._sqib:=X]
122467 t.ff.__clk : 0 [by t.ff._clk:=1]
129024 t.ff._sqi : X [by t.ff._sqib:=X]
135341 t.ff._sqib : 0 [by t.ff._mqi:=1]
165121 t.q : 1 [by t.ff._sqib:=0]
186994 t.ff._sqi : 1 [by t.ff._sqib:=0]
[3] tested d = 1, clk rise and fall

5
test/unit_tests/flipflop/test.prsim
View File

@ -1,13 +1,13 @@
watchall
system "echo '[0] start test'"
set Reset 1
set Reset 0
set t.d 0
set t.clk 0
cycle
status X
mode run
assert t.q 0
set Reset 0
cycle
assert t.q 0
system "echo '[1] reset completed'"
@ -21,6 +21,7 @@ set t.d 1
cycle
set t.clk 1
cycle
set t.d 0
assert t.q 0
set t.clk 0
cycle

589
test/unit_tests/register_write/run/prsim.out
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File diff suppressed because one or more lines are too long

652
test/unit_tests/register_write/run/test.prs
View File

@ -13,34 +13,18 @@
= "t.data[1].d[0]" "t.registers.data[1].d[0]"
= "t.data[2].d[0]" "t.registers.data[2].d[0]"
= "t.data[3].d[0]" "t.registers.data[3].d[0]"
= "t.data[4].d[0]" "t.registers.data[4].d[0]"
= "t.data[5].d[0]" "t.registers.data[5].d[0]"
= "t.data[6].d[0]" "t.registers.data[6].d[0]"
= "t.data[7].d[0]" "t.registers.data[7].d[0]"
= "t.data[0].d[1]" "t.registers.data[0].d[1]"
= "t.data[1].d[1]" "t.registers.data[1].d[1]"
= "t.data[2].d[1]" "t.registers.data[2].d[1]"
= "t.data[3].d[1]" "t.registers.data[3].d[1]"
= "t.data[4].d[1]" "t.registers.data[4].d[1]"
= "t.data[5].d[1]" "t.registers.data[5].d[1]"
= "t.data[6].d[1]" "t.registers.data[6].d[1]"
= "t.data[7].d[1]" "t.registers.data[7].d[1]"
= "t.registers._clock_temp" "t.registers.clk_X.in"
= "t.registers._clock_temp" "t.registers.inv_clk.a"
= "t.registers._clock_temp" "t.registers.clk_dly.out"
"t.registers.reset_bufarray.buf6.a"->"t.registers.reset_bufarray.buf6._y"-
~("t.registers.reset_bufarray.buf6.a")->"t.registers.reset_bufarray.buf6._y"+
"t.registers.reset_bufarray.buf6._y"->"t.registers.reset_bufarray.buf6.y"-
~("t.registers.reset_bufarray.buf6._y")->"t.registers.reset_bufarray.buf6.y"+
= "t.registers.reset_bufarray.supply.vdd" "t.registers.reset_bufarray.buf6.vdd"
= "t.registers.reset_bufarray.supply.vss" "t.registers.reset_bufarray.buf6.vss"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[15]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[14]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[13]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[12]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[11]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[10]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[9]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[8]"
"t.registers.reset_bufarray.buf3.a"->"t.registers.reset_bufarray.buf3._y"-
~("t.registers.reset_bufarray.buf3.a")->"t.registers.reset_bufarray.buf3._y"+
"t.registers.reset_bufarray.buf3._y"->"t.registers.reset_bufarray.buf3.y"-
~("t.registers.reset_bufarray.buf3._y")->"t.registers.reset_bufarray.buf3.y"+
= "t.registers.reset_bufarray.supply.vdd" "t.registers.reset_bufarray.buf3.vdd"
= "t.registers.reset_bufarray.supply.vss" "t.registers.reset_bufarray.buf3.vss"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[7]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[6]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[5]"
@ -48,232 +32,134 @@
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[3]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[2]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[1]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.buf6.y"
= "t.registers.reset_bufarray.in" "t.registers.reset_bufarray.buf6.a"
"t.registers.ff[0].clk"->"t.registers.ff[0]._clk"-
~("t.registers.ff[0].clk")->"t.registers.ff[0]._clk"+
"t.registers.ff[0]._clk"->"t.registers.ff[0].__clk"-
~("t.registers.ff[0]._clk")->"t.registers.ff[0].__clk"+
~"t.registers.ff[0].d"&~"t.registers.ff[0]._clk"|~"t.registers.ff[0].reset_B"|~"t.registers.ff[0].__clk"&~"t.registers.ff[0]._mqi"->"t.registers.ff[0]._mqib"+
"t.registers.ff[0].d"&"t.registers.ff[0].__clk"|"t.registers.ff[0].reset_B"&"t.registers.ff[0]._mqi"&"t.registers.ff[0]._clk"->"t.registers.ff[0]._mqib"-
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.buf3.y"
= "t.registers.reset_bufarray.in" "t.registers.reset_bufarray.buf3.a"
"t.registers.ff[0].clk_B"->"t.registers.ff[0]._clk_B"-
~("t.registers.ff[0].clk_B")->"t.registers.ff[0]._clk_B"+
"t.registers.ff[0]._clk_B"->"t.registers.ff[0].__clk_B"-
~("t.registers.ff[0]._clk_B")->"t.registers.ff[0].__clk_B"+
~"t.registers.ff[0].d"&~"t.registers.ff[0]._clk_B"|~"t.registers.ff[0].reset_B"|~"t.registers.ff[0].__clk_B"&~"t.registers.ff[0]._mqi"->"t.registers.ff[0]._mqib"+
("t.registers.ff[0].d"&"t.registers.ff[0].__clk_B"|"t.registers.ff[0]._mqi"&"t.registers.ff[0]._clk_B")&"t.registers.ff[0].reset_B"->"t.registers.ff[0]._mqib"-
"t.registers.ff[0]._mqib"->"t.registers.ff[0]._mqi"-
~("t.registers.ff[0]._mqib")->"t.registers.ff[0]._mqi"+
~"t.registers.ff[0]._mqi"&~"t.registers.ff[0].__clk"|~"t.registers.ff[0].reset_B"|~"t.registers.ff[0]._sqi"&~"t.registers.ff[0]._clk"->"t.registers.ff[0]._sqib"+
"t.registers.ff[0]._mqi"&"t.registers.ff[0]._clk"|"t.registers.ff[0]._sqi"&"t.registers.ff[0].__clk"&"t.registers.ff[0].reset_B"->"t.registers.ff[0]._sqib"-
~"t.registers.ff[0]._mqi"&~"t.registers.ff[0].__clk_B"|~"t.registers.ff[0].reset_B"|~"t.registers.ff[0]._sqi"&~"t.registers.ff[0]._clk_B"->"t.registers.ff[0]._sqib"+
("t.registers.ff[0]._mqi"&"t.registers.ff[0]._clk_B"|"t.registers.ff[0]._sqi"&"t.registers.ff[0].__clk_B")&"t.registers.ff[0].reset_B"->"t.registers.ff[0]._sqib"-
"t.registers.ff[0]._sqib"->"t.registers.ff[0]._sqi"-
~("t.registers.ff[0]._sqib")->"t.registers.ff[0]._sqi"+
"t.registers.ff[0]._sqib"->"t.registers.ff[0].q"-
~("t.registers.ff[0]._sqib")->"t.registers.ff[0].q"+
"t.registers.ff[1].clk"->"t.registers.ff[1]._clk"-
~("t.registers.ff[1].clk")->"t.registers.ff[1]._clk"+
"t.registers.ff[1]._clk"->"t.registers.ff[1].__clk"-
~("t.registers.ff[1]._clk")->"t.registers.ff[1].__clk"+
~"t.registers.ff[1].d"&~"t.registers.ff[1]._clk"|~"t.registers.ff[1].reset_B"|~"t.registers.ff[1].__clk"&~"t.registers.ff[1]._mqi"->"t.registers.ff[1]._mqib"+
"t.registers.ff[1].d"&"t.registers.ff[1].__clk"|"t.registers.ff[1].reset_B"&"t.registers.ff[1]._mqi"&"t.registers.ff[1]._clk"->"t.registers.ff[1]._mqib"-
"t.registers.ff[1].clk_B"->"t.registers.ff[1]._clk_B"-
~("t.registers.ff[1].clk_B")->"t.registers.ff[1]._clk_B"+
"t.registers.ff[1]._clk_B"->"t.registers.ff[1].__clk_B"-
~("t.registers.ff[1]._clk_B")->"t.registers.ff[1].__clk_B"+
~"t.registers.ff[1].d"&~"t.registers.ff[1]._clk_B"|~"t.registers.ff[1].reset_B"|~"t.registers.ff[1].__clk_B"&~"t.registers.ff[1]._mqi"->"t.registers.ff[1]._mqib"+
("t.registers.ff[1].d"&"t.registers.ff[1].__clk_B"|"t.registers.ff[1]._mqi"&"t.registers.ff[1]._clk_B")&"t.registers.ff[1].reset_B"->"t.registers.ff[1]._mqib"-
"t.registers.ff[1]._mqib"->"t.registers.ff[1]._mqi"-
~("t.registers.ff[1]._mqib")->"t.registers.ff[1]._mqi"+
~"t.registers.ff[1]._mqi"&~"t.registers.ff[1].__clk"|~"t.registers.ff[1].reset_B"|~"t.registers.ff[1]._sqi"&~"t.registers.ff[1]._clk"->"t.registers.ff[1]._sqib"+
"t.registers.ff[1]._mqi"&"t.registers.ff[1]._clk"|"t.registers.ff[1]._sqi"&"t.registers.ff[1].__clk"&"t.registers.ff[1].reset_B"->"t.registers.ff[1]._sqib"-
~"t.registers.ff[1]._mqi"&~"t.registers.ff[1].__clk_B"|~"t.registers.ff[1].reset_B"|~"t.registers.ff[1]._sqi"&~"t.registers.ff[1]._clk_B"->"t.registers.ff[1]._sqib"+
("t.registers.ff[1]._mqi"&"t.registers.ff[1]._clk_B"|"t.registers.ff[1]._sqi"&"t.registers.ff[1].__clk_B")&"t.registers.ff[1].reset_B"->"t.registers.ff[1]._sqib"-
"t.registers.ff[1]._sqib"->"t.registers.ff[1]._sqi"-
~("t.registers.ff[1]._sqib")->"t.registers.ff[1]._sqi"+
"t.registers.ff[1]._sqib"->"t.registers.ff[1].q"-
~("t.registers.ff[1]._sqib")->"t.registers.ff[1].q"+
"t.registers.ff[2].clk"->"t.registers.ff[2]._clk"-
~("t.registers.ff[2].clk")->"t.registers.ff[2]._clk"+
"t.registers.ff[2]._clk"->"t.registers.ff[2].__clk"-
~("t.registers.ff[2]._clk")->"t.registers.ff[2].__clk"+
~"t.registers.ff[2].d"&~"t.registers.ff[2]._clk"|~"t.registers.ff[2].reset_B"|~"t.registers.ff[2].__clk"&~"t.registers.ff[2]._mqi"->"t.registers.ff[2]._mqib"+
"t.registers.ff[2].d"&"t.registers.ff[2].__clk"|"t.registers.ff[2].reset_B"&"t.registers.ff[2]._mqi"&"t.registers.ff[2]._clk"->"t.registers.ff[2]._mqib"-
"t.registers.ff[2].clk_B"->"t.registers.ff[2]._clk_B"-
~("t.registers.ff[2].clk_B")->"t.registers.ff[2]._clk_B"+
"t.registers.ff[2]._clk_B"->"t.registers.ff[2].__clk_B"-
~("t.registers.ff[2]._clk_B")->"t.registers.ff[2].__clk_B"+
~"t.registers.ff[2].d"&~"t.registers.ff[2]._clk_B"|~"t.registers.ff[2].reset_B"|~"t.registers.ff[2].__clk_B"&~"t.registers.ff[2]._mqi"->"t.registers.ff[2]._mqib"+
("t.registers.ff[2].d"&"t.registers.ff[2].__clk_B"|"t.registers.ff[2]._mqi"&"t.registers.ff[2]._clk_B")&"t.registers.ff[2].reset_B"->"t.registers.ff[2]._mqib"-
"t.registers.ff[2]._mqib"->"t.registers.ff[2]._mqi"-
~("t.registers.ff[2]._mqib")->"t.registers.ff[2]._mqi"+
~"t.registers.ff[2]._mqi"&~"t.registers.ff[2].__clk"|~"t.registers.ff[2].reset_B"|~"t.registers.ff[2]._sqi"&~"t.registers.ff[2]._clk"->"t.registers.ff[2]._sqib"+
"t.registers.ff[2]._mqi"&"t.registers.ff[2]._clk"|"t.registers.ff[2]._sqi"&"t.registers.ff[2].__clk"&"t.registers.ff[2].reset_B"->"t.registers.ff[2]._sqib"-
~"t.registers.ff[2]._mqi"&~"t.registers.ff[2].__clk_B"|~"t.registers.ff[2].reset_B"|~"t.registers.ff[2]._sqi"&~"t.registers.ff[2]._clk_B"->"t.registers.ff[2]._sqib"+
("t.registers.ff[2]._mqi"&"t.registers.ff[2]._clk_B"|"t.registers.ff[2]._sqi"&"t.registers.ff[2].__clk_B")&"t.registers.ff[2].reset_B"->"t.registers.ff[2]._sqib"-
"t.registers.ff[2]._sqib"->"t.registers.ff[2]._sqi"-
~("t.registers.ff[2]._sqib")->"t.registers.ff[2]._sqi"+
"t.registers.ff[2]._sqib"->"t.registers.ff[2].q"-
~("t.registers.ff[2]._sqib")->"t.registers.ff[2].q"+
"t.registers.ff[3].clk"->"t.registers.ff[3]._clk"-
~("t.registers.ff[3].clk")->"t.registers.ff[3]._clk"+
"t.registers.ff[3]._clk"->"t.registers.ff[3].__clk"-
~("t.registers.ff[3]._clk")->"t.registers.ff[3].__clk"+
~"t.registers.ff[3].d"&~"t.registers.ff[3]._clk"|~"t.registers.ff[3].reset_B"|~"t.registers.ff[3].__clk"&~"t.registers.ff[3]._mqi"->"t.registers.ff[3]._mqib"+
"t.registers.ff[3].d"&"t.registers.ff[3].__clk"|"t.registers.ff[3].reset_B"&"t.registers.ff[3]._mqi"&"t.registers.ff[3]._clk"->"t.registers.ff[3]._mqib"-
"t.registers.ff[3].clk_B"->"t.registers.ff[3]._clk_B"-
~("t.registers.ff[3].clk_B")->"t.registers.ff[3]._clk_B"+
"t.registers.ff[3]._clk_B"->"t.registers.ff[3].__clk_B"-
~("t.registers.ff[3]._clk_B")->"t.registers.ff[3].__clk_B"+
~"t.registers.ff[3].d"&~"t.registers.ff[3]._clk_B"|~"t.registers.ff[3].reset_B"|~"t.registers.ff[3].__clk_B"&~"t.registers.ff[3]._mqi"->"t.registers.ff[3]._mqib"+
("t.registers.ff[3].d"&"t.registers.ff[3].__clk_B"|"t.registers.ff[3]._mqi"&"t.registers.ff[3]._clk_B")&"t.registers.ff[3].reset_B"->"t.registers.ff[3]._mqib"-
"t.registers.ff[3]._mqib"->"t.registers.ff[3]._mqi"-
~("t.registers.ff[3]._mqib")->"t.registers.ff[3]._mqi"+
~"t.registers.ff[3]._mqi"&~"t.registers.ff[3].__clk"|~"t.registers.ff[3].reset_B"|~"t.registers.ff[3]._sqi"&~"t.registers.ff[3]._clk"->"t.registers.ff[3]._sqib"+
"t.registers.ff[3]._mqi"&"t.registers.ff[3]._clk"|"t.registers.ff[3]._sqi"&"t.registers.ff[3].__clk"&"t.registers.ff[3].reset_B"->"t.registers.ff[3]._sqib"-
~"t.registers.ff[3]._mqi"&~"t.registers.ff[3].__clk_B"|~"t.registers.ff[3].reset_B"|~"t.registers.ff[3]._sqi"&~"t.registers.ff[3]._clk_B"->"t.registers.ff[3]._sqib"+
("t.registers.ff[3]._mqi"&"t.registers.ff[3]._clk_B"|"t.registers.ff[3]._sqi"&"t.registers.ff[3].__clk_B")&"t.registers.ff[3].reset_B"->"t.registers.ff[3]._sqib"-
"t.registers.ff[3]._sqib"->"t.registers.ff[3]._sqi"-
~("t.registers.ff[3]._sqib")->"t.registers.ff[3]._sqi"+
"t.registers.ff[3]._sqib"->"t.registers.ff[3].q"-
~("t.registers.ff[3]._sqib")->"t.registers.ff[3].q"+
"t.registers.ff[4].clk"->"t.registers.ff[4]._clk"-
~("t.registers.ff[4].clk")->"t.registers.ff[4]._clk"+
"t.registers.ff[4]._clk"->"t.registers.ff[4].__clk"-
~("t.registers.ff[4]._clk")->"t.registers.ff[4].__clk"+
~"t.registers.ff[4].d"&~"t.registers.ff[4]._clk"|~"t.registers.ff[4].reset_B"|~"t.registers.ff[4].__clk"&~"t.registers.ff[4]._mqi"->"t.registers.ff[4]._mqib"+
"t.registers.ff[4].d"&"t.registers.ff[4].__clk"|"t.registers.ff[4].reset_B"&"t.registers.ff[4]._mqi"&"t.registers.ff[4]._clk"->"t.registers.ff[4]._mqib"-
"t.registers.ff[4].clk_B"->"t.registers.ff[4]._clk_B"-
~("t.registers.ff[4].clk_B")->"t.registers.ff[4]._clk_B"+
"t.registers.ff[4]._clk_B"->"t.registers.ff[4].__clk_B"-
~("t.registers.ff[4]._clk_B")->"t.registers.ff[4].__clk_B"+
~"t.registers.ff[4].d"&~"t.registers.ff[4]._clk_B"|~"t.registers.ff[4].reset_B"|~"t.registers.ff[4].__clk_B"&~"t.registers.ff[4]._mqi"->"t.registers.ff[4]._mqib"+
("t.registers.ff[4].d"&"t.registers.ff[4].__clk_B"|"t.registers.ff[4]._mqi"&"t.registers.ff[4]._clk_B")&"t.registers.ff[4].reset_B"->"t.registers.ff[4]._mqib"-
"t.registers.ff[4]._mqib"->"t.registers.ff[4]._mqi"-
~("t.registers.ff[4]._mqib")->"t.registers.ff[4]._mqi"+
~"t.registers.ff[4]._mqi"&~"t.registers.ff[4].__clk"|~"t.registers.ff[4].reset_B"|~"t.registers.ff[4]._sqi"&~"t.registers.ff[4]._clk"->"t.registers.ff[4]._sqib"+
"t.registers.ff[4]._mqi"&"t.registers.ff[4]._clk"|"t.registers.ff[4]._sqi"&"t.registers.ff[4].__clk"&"t.registers.ff[4].reset_B"->"t.registers.ff[4]._sqib"-
~"t.registers.ff[4]._mqi"&~"t.registers.ff[4].__clk_B"|~"t.registers.ff[4].reset_B"|~"t.registers.ff[4]._sqi"&~"t.registers.ff[4]._clk_B"->"t.registers.ff[4]._sqib"+
("t.registers.ff[4]._mqi"&"t.registers.ff[4]._clk_B"|"t.registers.ff[4]._sqi"&"t.registers.ff[4].__clk_B")&"t.registers.ff[4].reset_B"->"t.registers.ff[4]._sqib"-
"t.registers.ff[4]._sqib"->"t.registers.ff[4]._sqi"-
~("t.registers.ff[4]._sqib")->"t.registers.ff[4]._sqi"+
"t.registers.ff[4]._sqib"->"t.registers.ff[4].q"-
~("t.registers.ff[4]._sqib")->"t.registers.ff[4].q"+
"t.registers.ff[5].clk"->"t.registers.ff[5]._clk"-
~("t.registers.ff[5].clk")->"t.registers.ff[5]._clk"+
"t.registers.ff[5]._clk"->"t.registers.ff[5].__clk"-
~("t.registers.ff[5]._clk")->"t.registers.ff[5].__clk"+
~"t.registers.ff[5].d"&~"t.registers.ff[5]._clk"|~"t.registers.ff[5].reset_B"|~"t.registers.ff[5].__clk"&~"t.registers.ff[5]._mqi"->"t.registers.ff[5]._mqib"+
"t.registers.ff[5].d"&"t.registers.ff[5].__clk"|"t.registers.ff[5].reset_B"&"t.registers.ff[5]._mqi"&"t.registers.ff[5]._clk"->"t.registers.ff[5]._mqib"-
"t.registers.ff[5].clk_B"->"t.registers.ff[5]._clk_B"-
~("t.registers.ff[5].clk_B")->"t.registers.ff[5]._clk_B"+
"t.registers.ff[5]._clk_B"->"t.registers.ff[5].__clk_B"-
~("t.registers.ff[5]._clk_B")->"t.registers.ff[5].__clk_B"+
~"t.registers.ff[5].d"&~"t.registers.ff[5]._clk_B"|~"t.registers.ff[5].reset_B"|~"t.registers.ff[5].__clk_B"&~"t.registers.ff[5]._mqi"->"t.registers.ff[5]._mqib"+
("t.registers.ff[5].d"&"t.registers.ff[5].__clk_B"|"t.registers.ff[5]._mqi"&"t.registers.ff[5]._clk_B")&"t.registers.ff[5].reset_B"->"t.registers.ff[5]._mqib"-
"t.registers.ff[5]._mqib"->"t.registers.ff[5]._mqi"-
~("t.registers.ff[5]._mqib")->"t.registers.ff[5]._mqi"+
~"t.registers.ff[5]._mqi"&~"t.registers.ff[5].__clk"|~"t.registers.ff[5].reset_B"|~"t.registers.ff[5]._sqi"&~"t.registers.ff[5]._clk"->"t.registers.ff[5]._sqib"+
"t.registers.ff[5]._mqi"&"t.registers.ff[5]._clk"|"t.registers.ff[5]._sqi"&"t.registers.ff[5].__clk"&"t.registers.ff[5].reset_B"->"t.registers.ff[5]._sqib"-
~"t.registers.ff[5]._mqi"&~"t.registers.ff[5].__clk_B"|~"t.registers.ff[5].reset_B"|~"t.registers.ff[5]._sqi"&~"t.registers.ff[5]._clk_B"->"t.registers.ff[5]._sqib"+
("t.registers.ff[5]._mqi"&"t.registers.ff[5]._clk_B"|"t.registers.ff[5]._sqi"&"t.registers.ff[5].__clk_B")&"t.registers.ff[5].reset_B"->"t.registers.ff[5]._sqib"-
"t.registers.ff[5]._sqib"->"t.registers.ff[5]._sqi"-
~("t.registers.ff[5]._sqib")->"t.registers.ff[5]._sqi"+
"t.registers.ff[5]._sqib"->"t.registers.ff[5].q"-
~("t.registers.ff[5]._sqib")->"t.registers.ff[5].q"+
"t.registers.ff[6].clk"->"t.registers.ff[6]._clk"-
~("t.registers.ff[6].clk")->"t.registers.ff[6]._clk"+
"t.registers.ff[6]._clk"->"t.registers.ff[6].__clk"-
~("t.registers.ff[6]._clk")->"t.registers.ff[6].__clk"+
~"t.registers.ff[6].d"&~"t.registers.ff[6]._clk"|~"t.registers.ff[6].reset_B"|~"t.registers.ff[6].__clk"&~"t.registers.ff[6]._mqi"->"t.registers.ff[6]._mqib"+
"t.registers.ff[6].d"&"t.registers.ff[6].__clk"|"t.registers.ff[6].reset_B"&"t.registers.ff[6]._mqi"&"t.registers.ff[6]._clk"->"t.registers.ff[6]._mqib"-
"t.registers.ff[6].clk_B"->"t.registers.ff[6]._clk_B"-
~("t.registers.ff[6].clk_B")->"t.registers.ff[6]._clk_B"+
"t.registers.ff[6]._clk_B"->"t.registers.ff[6].__clk_B"-
~("t.registers.ff[6]._clk_B")->"t.registers.ff[6].__clk_B"+
~"t.registers.ff[6].d"&~"t.registers.ff[6]._clk_B"|~"t.registers.ff[6].reset_B"|~"t.registers.ff[6].__clk_B"&~"t.registers.ff[6]._mqi"->"t.registers.ff[6]._mqib"+
("t.registers.ff[6].d"&"t.registers.ff[6].__clk_B"|"t.registers.ff[6]._mqi"&"t.registers.ff[6]._clk_B")&"t.registers.ff[6].reset_B"->"t.registers.ff[6]._mqib"-
"t.registers.ff[6]._mqib"->"t.registers.ff[6]._mqi"-
~("t.registers.ff[6]._mqib")->"t.registers.ff[6]._mqi"+
~"t.registers.ff[6]._mqi"&~"t.registers.ff[6].__clk"|~"t.registers.ff[6].reset_B"|~"t.registers.ff[6]._sqi"&~"t.registers.ff[6]._clk"->"t.registers.ff[6]._sqib"+
"t.registers.ff[6]._mqi"&"t.registers.ff[6]._clk"|"t.registers.ff[6]._sqi"&"t.registers.ff[6].__clk"&"t.registers.ff[6].reset_B"->"t.registers.ff[6]._sqib"-
~"t.registers.ff[6]._mqi"&~"t.registers.ff[6].__clk_B"|~"t.registers.ff[6].reset_B"|~"t.registers.ff[6]._sqi"&~"t.registers.ff[6]._clk_B"->"t.registers.ff[6]._sqib"+
("t.registers.ff[6]._mqi"&"t.registers.ff[6]._clk_B"|"t.registers.ff[6]._sqi"&"t.registers.ff[6].__clk_B")&"t.registers.ff[6].reset_B"->"t.registers.ff[6]._sqib"-
"t.registers.ff[6]._sqib"->"t.registers.ff[6]._sqi"-
~("t.registers.ff[6]._sqib")->"t.registers.ff[6]._sqi"+
"t.registers.ff[6]._sqib"->"t.registers.ff[6].q"-
~("t.registers.ff[6]._sqib")->"t.registers.ff[6].q"+
"t.registers.ff[7].clk"->"t.registers.ff[7]._clk"-
~("t.registers.ff[7].clk")->"t.registers.ff[7]._clk"+
"t.registers.ff[7]._clk"->"t.registers.ff[7].__clk"-
~("t.registers.ff[7]._clk")->"t.registers.ff[7].__clk"+
~"t.registers.ff[7].d"&~"t.registers.ff[7]._clk"|~"t.registers.ff[7].reset_B"|~"t.registers.ff[7].__clk"&~"t.registers.ff[7]._mqi"->"t.registers.ff[7]._mqib"+
"t.registers.ff[7].d"&"t.registers.ff[7].__clk"|"t.registers.ff[7].reset_B"&"t.registers.ff[7]._mqi"&"t.registers.ff[7]._clk"->"t.registers.ff[7]._mqib"-
"t.registers.ff[7].clk_B"->"t.registers.ff[7]._clk_B"-
~("t.registers.ff[7].clk_B")->"t.registers.ff[7]._clk_B"+
"t.registers.ff[7]._clk_B"->"t.registers.ff[7].__clk_B"-
~("t.registers.ff[7]._clk_B")->"t.registers.ff[7].__clk_B"+
~"t.registers.ff[7].d"&~"t.registers.ff[7]._clk_B"|~"t.registers.ff[7].reset_B"|~"t.registers.ff[7].__clk_B"&~"t.registers.ff[7]._mqi"->"t.registers.ff[7]._mqib"+
("t.registers.ff[7].d"&"t.registers.ff[7].__clk_B"|"t.registers.ff[7]._mqi"&"t.registers.ff[7]._clk_B")&"t.registers.ff[7].reset_B"->"t.registers.ff[7]._mqib"-
"t.registers.ff[7]._mqib"->"t.registers.ff[7]._mqi"-
~("t.registers.ff[7]._mqib")->"t.registers.ff[7]._mqi"+
~"t.registers.ff[7]._mqi"&~"t.registers.ff[7].__clk"|~"t.registers.ff[7].reset_B"|~"t.registers.ff[7]._sqi"&~"t.registers.ff[7]._clk"->"t.registers.ff[7]._sqib"+
"t.registers.ff[7]._mqi"&"t.registers.ff[7]._clk"|"t.registers.ff[7]._sqi"&"t.registers.ff[7].__clk"&"t.registers.ff[7].reset_B"->"t.registers.ff[7]._sqib"-
~"t.registers.ff[7]._mqi"&~"t.registers.ff[7].__clk_B"|~"t.registers.ff[7].reset_B"|~"t.registers.ff[7]._sqi"&~"t.registers.ff[7]._clk_B"->"t.registers.ff[7]._sqib"+
("t.registers.ff[7]._mqi"&"t.registers.ff[7]._clk_B"|"t.registers.ff[7]._sqi"&"t.registers.ff[7].__clk_B")&"t.registers.ff[7].reset_B"->"t.registers.ff[7]._sqib"-
"t.registers.ff[7]._sqib"->"t.registers.ff[7]._sqi"-
~("t.registers.ff[7]._sqib")->"t.registers.ff[7]._sqi"+
"t.registers.ff[7]._sqib"->"t.registers.ff[7].q"-
~("t.registers.ff[7]._sqib")->"t.registers.ff[7].q"+
"t.registers.ff[8].clk"->"t.registers.ff[8]._clk"-
~("t.registers.ff[8].clk")->"t.registers.ff[8]._clk"+
"t.registers.ff[8]._clk"->"t.registers.ff[8].__clk"-
~("t.registers.ff[8]._clk")->"t.registers.ff[8].__clk"+
~"t.registers.ff[8].d"&~"t.registers.ff[8]._clk"|~"t.registers.ff[8].reset_B"|~"t.registers.ff[8].__clk"&~"t.registers.ff[8]._mqi"->"t.registers.ff[8]._mqib"+
"t.registers.ff[8].d"&"t.registers.ff[8].__clk"|"t.registers.ff[8].reset_B"&"t.registers.ff[8]._mqi"&"t.registers.ff[8]._clk"->"t.registers.ff[8]._mqib"-
"t.registers.ff[8]._mqib"->"t.registers.ff[8]._mqi"-
~("t.registers.ff[8]._mqib")->"t.registers.ff[8]._mqi"+
~"t.registers.ff[8]._mqi"&~"t.registers.ff[8].__clk"|~"t.registers.ff[8].reset_B"|~"t.registers.ff[8]._sqi"&~"t.registers.ff[8]._clk"->"t.registers.ff[8]._sqib"+
"t.registers.ff[8]._mqi"&"t.registers.ff[8]._clk"|"t.registers.ff[8]._sqi"&"t.registers.ff[8].__clk"&"t.registers.ff[8].reset_B"->"t.registers.ff[8]._sqib"-
"t.registers.ff[8]._sqib"->"t.registers.ff[8]._sqi"-
~("t.registers.ff[8]._sqib")->"t.registers.ff[8]._sqi"+
"t.registers.ff[8]._sqib"->"t.registers.ff[8].q"-
~("t.registers.ff[8]._sqib")->"t.registers.ff[8].q"+
"t.registers.ff[9].clk"->"t.registers.ff[9]._clk"-
~("t.registers.ff[9].clk")->"t.registers.ff[9]._clk"+
"t.registers.ff[9]._clk"->"t.registers.ff[9].__clk"-
~("t.registers.ff[9]._clk")->"t.registers.ff[9].__clk"+
~"t.registers.ff[9].d"&~"t.registers.ff[9]._clk"|~"t.registers.ff[9].reset_B"|~"t.registers.ff[9].__clk"&~"t.registers.ff[9]._mqi"->"t.registers.ff[9]._mqib"+
"t.registers.ff[9].d"&"t.registers.ff[9].__clk"|"t.registers.ff[9].reset_B"&"t.registers.ff[9]._mqi"&"t.registers.ff[9]._clk"->"t.registers.ff[9]._mqib"-
"t.registers.ff[9]._mqib"->"t.registers.ff[9]._mqi"-
~("t.registers.ff[9]._mqib")->"t.registers.ff[9]._mqi"+
~"t.registers.ff[9]._mqi"&~"t.registers.ff[9].__clk"|~"t.registers.ff[9].reset_B"|~"t.registers.ff[9]._sqi"&~"t.registers.ff[9]._clk"->"t.registers.ff[9]._sqib"+
"t.registers.ff[9]._mqi"&"t.registers.ff[9]._clk"|"t.registers.ff[9]._sqi"&"t.registers.ff[9].__clk"&"t.registers.ff[9].reset_B"->"t.registers.ff[9]._sqib"-
"t.registers.ff[9]._sqib"->"t.registers.ff[9]._sqi"-
~("t.registers.ff[9]._sqib")->"t.registers.ff[9]._sqi"+
"t.registers.ff[9]._sqib"->"t.registers.ff[9].q"-
~("t.registers.ff[9]._sqib")->"t.registers.ff[9].q"+
"t.registers.ff[10].clk"->"t.registers.ff[10]._clk"-
~("t.registers.ff[10].clk")->"t.registers.ff[10]._clk"+
"t.registers.ff[10]._clk"->"t.registers.ff[10].__clk"-
~("t.registers.ff[10]._clk")->"t.registers.ff[10].__clk"+
~"t.registers.ff[10].d"&~"t.registers.ff[10]._clk"|~"t.registers.ff[10].reset_B"|~"t.registers.ff[10].__clk"&~"t.registers.ff[10]._mqi"->"t.registers.ff[10]._mqib"+
"t.registers.ff[10].d"&"t.registers.ff[10].__clk"|"t.registers.ff[10].reset_B"&"t.registers.ff[10]._mqi"&"t.registers.ff[10]._clk"->"t.registers.ff[10]._mqib"-
"t.registers.ff[10]._mqib"->"t.registers.ff[10]._mqi"-
~("t.registers.ff[10]._mqib")->"t.registers.ff[10]._mqi"+
~"t.registers.ff[10]._mqi"&~"t.registers.ff[10].__clk"|~"t.registers.ff[10].reset_B"|~"t.registers.ff[10]._sqi"&~"t.registers.ff[10]._clk"->"t.registers.ff[10]._sqib"+
"t.registers.ff[10]._mqi"&"t.registers.ff[10]._clk"|"t.registers.ff[10]._sqi"&"t.registers.ff[10].__clk"&"t.registers.ff[10].reset_B"->"t.registers.ff[10]._sqib"-
"t.registers.ff[10]._sqib"->"t.registers.ff[10]._sqi"-
~("t.registers.ff[10]._sqib")->"t.registers.ff[10]._sqi"+
"t.registers.ff[10]._sqib"->"t.registers.ff[10].q"-
~("t.registers.ff[10]._sqib")->"t.registers.ff[10].q"+
"t.registers.ff[11].clk"->"t.registers.ff[11]._clk"-
~("t.registers.ff[11].clk")->"t.registers.ff[11]._clk"+
"t.registers.ff[11]._clk"->"t.registers.ff[11].__clk"-
~("t.registers.ff[11]._clk")->"t.registers.ff[11].__clk"+
~"t.registers.ff[11].d"&~"t.registers.ff[11]._clk"|~"t.registers.ff[11].reset_B"|~"t.registers.ff[11].__clk"&~"t.registers.ff[11]._mqi"->"t.registers.ff[11]._mqib"+
"t.registers.ff[11].d"&"t.registers.ff[11].__clk"|"t.registers.ff[11].reset_B"&"t.registers.ff[11]._mqi"&"t.registers.ff[11]._clk"->"t.registers.ff[11]._mqib"-
"t.registers.ff[11]._mqib"->"t.registers.ff[11]._mqi"-
~("t.registers.ff[11]._mqib")->"t.registers.ff[11]._mqi"+
~"t.registers.ff[11]._mqi"&~"t.registers.ff[11].__clk"|~"t.registers.ff[11].reset_B"|~"t.registers.ff[11]._sqi"&~"t.registers.ff[11]._clk"->"t.registers.ff[11]._sqib"+
"t.registers.ff[11]._mqi"&"t.registers.ff[11]._clk"|"t.registers.ff[11]._sqi"&"t.registers.ff[11].__clk"&"t.registers.ff[11].reset_B"->"t.registers.ff[11]._sqib"-
"t.registers.ff[11]._sqib"->"t.registers.ff[11]._sqi"-
~("t.registers.ff[11]._sqib")->"t.registers.ff[11]._sqi"+
"t.registers.ff[11]._sqib"->"t.registers.ff[11].q"-
~("t.registers.ff[11]._sqib")->"t.registers.ff[11].q"+
"t.registers.ff[12].clk"->"t.registers.ff[12]._clk"-
~("t.registers.ff[12].clk")->"t.registers.ff[12]._clk"+
"t.registers.ff[12]._clk"->"t.registers.ff[12].__clk"-
~("t.registers.ff[12]._clk")->"t.registers.ff[12].__clk"+
~"t.registers.ff[12].d"&~"t.registers.ff[12]._clk"|~"t.registers.ff[12].reset_B"|~"t.registers.ff[12].__clk"&~"t.registers.ff[12]._mqi"->"t.registers.ff[12]._mqib"+
"t.registers.ff[12].d"&"t.registers.ff[12].__clk"|"t.registers.ff[12].reset_B"&"t.registers.ff[12]._mqi"&"t.registers.ff[12]._clk"->"t.registers.ff[12]._mqib"-
"t.registers.ff[12]._mqib"->"t.registers.ff[12]._mqi"-
~("t.registers.ff[12]._mqib")->"t.registers.ff[12]._mqi"+
~"t.registers.ff[12]._mqi"&~"t.registers.ff[12].__clk"|~"t.registers.ff[12].reset_B"|~"t.registers.ff[12]._sqi"&~"t.registers.ff[12]._clk"->"t.registers.ff[12]._sqib"+
"t.registers.ff[12]._mqi"&"t.registers.ff[12]._clk"|"t.registers.ff[12]._sqi"&"t.registers.ff[12].__clk"&"t.registers.ff[12].reset_B"->"t.registers.ff[12]._sqib"-
"t.registers.ff[12]._sqib"->"t.registers.ff[12]._sqi"-
~("t.registers.ff[12]._sqib")->"t.registers.ff[12]._sqi"+
"t.registers.ff[12]._sqib"->"t.registers.ff[12].q"-
~("t.registers.ff[12]._sqib")->"t.registers.ff[12].q"+
"t.registers.ff[13].clk"->"t.registers.ff[13]._clk"-
~("t.registers.ff[13].clk")->"t.registers.ff[13]._clk"+
"t.registers.ff[13]._clk"->"t.registers.ff[13].__clk"-
~("t.registers.ff[13]._clk")->"t.registers.ff[13].__clk"+
~"t.registers.ff[13].d"&~"t.registers.ff[13]._clk"|~"t.registers.ff[13].reset_B"|~"t.registers.ff[13].__clk"&~"t.registers.ff[13]._mqi"->"t.registers.ff[13]._mqib"+
"t.registers.ff[13].d"&"t.registers.ff[13].__clk"|"t.registers.ff[13].reset_B"&"t.registers.ff[13]._mqi"&"t.registers.ff[13]._clk"->"t.registers.ff[13]._mqib"-
"t.registers.ff[13]._mqib"->"t.registers.ff[13]._mqi"-
~("t.registers.ff[13]._mqib")->"t.registers.ff[13]._mqi"+
~"t.registers.ff[13]._mqi"&~"t.registers.ff[13].__clk"|~"t.registers.ff[13].reset_B"|~"t.registers.ff[13]._sqi"&~"t.registers.ff[13]._clk"->"t.registers.ff[13]._sqib"+
"t.registers.ff[13]._mqi"&"t.registers.ff[13]._clk"|"t.registers.ff[13]._sqi"&"t.registers.ff[13].__clk"&"t.registers.ff[13].reset_B"->"t.registers.ff[13]._sqib"-
"t.registers.ff[13]._sqib"->"t.registers.ff[13]._sqi"-
~("t.registers.ff[13]._sqib")->"t.registers.ff[13]._sqi"+
"t.registers.ff[13]._sqib"->"t.registers.ff[13].q"-
~("t.registers.ff[13]._sqib")->"t.registers.ff[13].q"+
"t.registers.ff[14].clk"->"t.registers.ff[14]._clk"-
~("t.registers.ff[14].clk")->"t.registers.ff[14]._clk"+
"t.registers.ff[14]._clk"->"t.registers.ff[14].__clk"-
~("t.registers.ff[14]._clk")->"t.registers.ff[14].__clk"+
~"t.registers.ff[14].d"&~"t.registers.ff[14]._clk"|~"t.registers.ff[14].reset_B"|~"t.registers.ff[14].__clk"&~"t.registers.ff[14]._mqi"->"t.registers.ff[14]._mqib"+
"t.registers.ff[14].d"&"t.registers.ff[14].__clk"|"t.registers.ff[14].reset_B"&"t.registers.ff[14]._mqi"&"t.registers.ff[14]._clk"->"t.registers.ff[14]._mqib"-
"t.registers.ff[14]._mqib"->"t.registers.ff[14]._mqi"-
~("t.registers.ff[14]._mqib")->"t.registers.ff[14]._mqi"+
~"t.registers.ff[14]._mqi"&~"t.registers.ff[14].__clk"|~"t.registers.ff[14].reset_B"|~"t.registers.ff[14]._sqi"&~"t.registers.ff[14]._clk"->"t.registers.ff[14]._sqib"+
"t.registers.ff[14]._mqi"&"t.registers.ff[14]._clk"|"t.registers.ff[14]._sqi"&"t.registers.ff[14].__clk"&"t.registers.ff[14].reset_B"->"t.registers.ff[14]._sqib"-
"t.registers.ff[14]._sqib"->"t.registers.ff[14]._sqi"-
~("t.registers.ff[14]._sqib")->"t.registers.ff[14]._sqi"+
"t.registers.ff[14]._sqib"->"t.registers.ff[14].q"-
~("t.registers.ff[14]._sqib")->"t.registers.ff[14].q"+
"t.registers.ff[15].clk"->"t.registers.ff[15]._clk"-
~("t.registers.ff[15].clk")->"t.registers.ff[15]._clk"+
"t.registers.ff[15]._clk"->"t.registers.ff[15].__clk"-
~("t.registers.ff[15]._clk")->"t.registers.ff[15].__clk"+
~"t.registers.ff[15].d"&~"t.registers.ff[15]._clk"|~"t.registers.ff[15].reset_B"|~"t.registers.ff[15].__clk"&~"t.registers.ff[15]._mqi"->"t.registers.ff[15]._mqib"+
"t.registers.ff[15].d"&"t.registers.ff[15].__clk"|"t.registers.ff[15].reset_B"&"t.registers.ff[15]._mqi"&"t.registers.ff[15]._clk"->"t.registers.ff[15]._mqib"-
"t.registers.ff[15]._mqib"->"t.registers.ff[15]._mqi"-
~("t.registers.ff[15]._mqib")->"t.registers.ff[15]._mqi"+
~"t.registers.ff[15]._mqi"&~"t.registers.ff[15].__clk"|~"t.registers.ff[15].reset_B"|~"t.registers.ff[15]._sqi"&~"t.registers.ff[15]._clk"->"t.registers.ff[15]._sqib"+
"t.registers.ff[15]._mqi"&"t.registers.ff[15]._clk"|"t.registers.ff[15]._sqi"&"t.registers.ff[15].__clk"&"t.registers.ff[15].reset_B"->"t.registers.ff[15]._sqib"-
"t.registers.ff[15]._sqib"->"t.registers.ff[15]._sqi"-
~("t.registers.ff[15]._sqib")->"t.registers.ff[15]._sqi"+
"t.registers.ff[15]._sqib"->"t.registers.ff[15].q"-
~("t.registers.ff[15]._sqib")->"t.registers.ff[15].q"+
= "t.registers.ff[7].clk_B" "t.registers.clock_buffer[3].out[1]"
= "t.registers.ff[7].clk_B" "t.registers.clock_buffer[3].out[0]"
= "t.registers.ff[7].clk_B" "t.registers.ff[6].clk_B"
= "t.registers.ff[5].clk_B" "t.registers.clock_buffer[2].out[1]"
= "t.registers.ff[5].clk_B" "t.registers.clock_buffer[2].out[0]"
= "t.registers.ff[5].clk_B" "t.registers.ff[4].clk_B"
= "t.registers.ff[3].clk_B" "t.registers.clock_buffer[1].out[1]"
= "t.registers.ff[3].clk_B" "t.registers.clock_buffer[1].out[0]"
= "t.registers.ff[3].clk_B" "t.registers.ff[2].clk_B"
= "t.registers.ff[1].clk_B" "t.registers.clock_buffer[0].out[1]"
= "t.registers.ff[1].clk_B" "t.registers.clock_buffer[0].out[0]"
= "t.registers.ff[1].clk_B" "t.registers.ff[0].clk_B"
= "t.registers._clock_temp_inv" "t.registers.clk_X.in"
= "t.registers._clock_temp_inv" "t.registers.inv_clk.y"
= "t.registers.reset_mem_B" "t.registers.reset_buf_BXX.a"
"t.registers.clk_X.buf1.a"->"t.registers.clk_X.buf1._y"-
~("t.registers.clk_X.buf1.a")->"t.registers.clk_X.buf1._y"+
@ -337,29 +223,29 @@
= "t.registers.in.d.d[4].d[1]" "t.registers._in_temp.d[4].d[1]"
= "t.registers.in.d.d[4].d[0]" "t.registers.in.d.d[4].f"
= "t.registers.in.d.d[4].d[1]" "t.registers.in.d.d[4].t"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[5].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[4].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[1].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[0].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.in.d.d[3].f"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[7].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[6].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[3].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[2].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.in.d.d[3].t"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[6].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[4].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[2].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[0].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.in.d.d[2].f"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[7].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[5].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[3].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[1].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.in.d.d[2].t"
= "t.registers.in.d.d[1].d[0]" "t.registers.in.d.d[1].f"
= "t.registers.in.d.d[1].d[1]" "t.registers.ff[7].d"
= "t.registers.in.d.d[1].d[1]" "t.registers.ff[5].d"
= "t.registers.in.d.d[1].d[1]" "t.registers.ff[3].d"
= "t.registers.in.d.d[1].d[1]" "t.registers.ff[1].d"
= "t.registers.in.d.d[1].d[1]" "t.registers.in.d.d[1].t"
= "t.registers.in.d.d[0].d[0]" "t.registers.in.d.d[0].f"
= "t.registers.in.d.d[0].d[1]" "t.registers.ff[6].d"
= "t.registers.in.d.d[0].d[1]" "t.registers.ff[4].d"
= "t.registers.in.d.d[0].d[1]" "t.registers.ff[2].d"
= "t.registers.in.d.d[0].d[1]" "t.registers.ff[0].d"
= "t.registers.in.d.d[0].d[1]" "t.registers.in.d.d[0].t"
"t.registers.reset_buf_BX.a"->"t.registers.reset_buf_BX._y"-
~("t.registers.reset_buf_BX.a")->"t.registers.reset_buf_BX._y"+
@ -450,22 +336,14 @@
= "t.registers._reset_mem_BXX[5]" "t.registers.reset_bufarray.out[5]"
= "t.registers._reset_mem_BXX[6]" "t.registers.reset_bufarray.out[6]"
= "t.registers._reset_mem_BXX[7]" "t.registers.reset_bufarray.out[7]"
= "t.registers._reset_mem_BXX[8]" "t.registers.reset_bufarray.out[8]"
= "t.registers._reset_mem_BXX[9]" "t.registers.reset_bufarray.out[9]"
= "t.registers._reset_mem_BXX[10]" "t.registers.reset_bufarray.out[10]"
= "t.registers._reset_mem_BXX[11]" "t.registers.reset_bufarray.out[11]"
= "t.registers._reset_mem_BXX[12]" "t.registers.reset_bufarray.out[12]"
= "t.registers._reset_mem_BXX[13]" "t.registers.reset_bufarray.out[13]"
= "t.registers._reset_mem_BXX[14]" "t.registers.reset_bufarray.out[14]"
= "t.registers._reset_mem_BXX[15]" "t.registers.reset_bufarray.out[15]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[15]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[14]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[13]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[12]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[11]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[10]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[9]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[8]"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[7].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[6].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[5].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[4].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[3].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[2].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[1].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[0].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[7]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[6]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[5]"
@ -481,14 +359,6 @@
= "t.registers._out_encoder[2]" "t.registers.atree[2].out"
= "t.registers._out_encoder[3]" "t.registers.and_encoder[3].a"
= "t.registers._out_encoder[3]" "t.registers.atree[3].out"
= "t.registers._out_encoder[4]" "t.registers.and_encoder[4].a"
= "t.registers._out_encoder[4]" "t.registers.atree[4].out"
= "t.registers._out_encoder[5]" "t.registers.and_encoder[5].a"
= "t.registers._out_encoder[5]" "t.registers.atree[5].out"
= "t.registers._out_encoder[6]" "t.registers.and_encoder[6].a"
= "t.registers._out_encoder[6]" "t.registers.atree[6].out"
= "t.registers._out_encoder[7]" "t.registers.and_encoder[7].a"
= "t.registers._out_encoder[7]" "t.registers.atree[7].out"
= "t.registers._clock_word_temp[0]" "t.registers.clock_buffer[0].in"
= "t.registers._clock_word_temp[0]" "t.registers.and_encoder[0].y"
= "t.registers._clock_word_temp[1]" "t.registers.clock_buffer[1].in"
@ -497,14 +367,22 @@
= "t.registers._clock_word_temp[2]" "t.registers.and_encoder[2].y"
= "t.registers._clock_word_temp[3]" "t.registers.clock_buffer[3].in"
= "t.registers._clock_word_temp[3]" "t.registers.and_encoder[3].y"
= "t.registers._clock_word_temp[4]" "t.registers.clock_buffer[4].in"
= "t.registers._clock_word_temp[4]" "t.registers.and_encoder[4].y"
= "t.registers._clock_word_temp[5]" "t.registers.clock_buffer[5].in"
= "t.registers._clock_word_temp[5]" "t.registers.and_encoder[5].y"
= "t.registers._clock_word_temp[6]" "t.registers.clock_buffer[6].in"
= "t.registers._clock_word_temp[6]" "t.registers.and_encoder[6].y"
= "t.registers._clock_word_temp[7]" "t.registers.clock_buffer[7].in"
= "t.registers._clock_word_temp[7]" "t.registers.and_encoder[7].y"
"t.registers.and_encoder[0].a"&"t.registers.and_encoder[0].b"->"t.registers.and_encoder[0]._y"-
~("t.registers.and_encoder[0].a"&"t.registers.and_encoder[0].b")->"t.registers.and_encoder[0]._y"+
"t.registers.and_encoder[0]._y"->"t.registers.and_encoder[0].y"-
~("t.registers.and_encoder[0]._y")->"t.registers.and_encoder[0].y"+
"t.registers.and_encoder[1].a"&"t.registers.and_encoder[1].b"->"t.registers.and_encoder[1]._y"-
~("t.registers.and_encoder[1].a"&"t.registers.and_encoder[1].b")->"t.registers.and_encoder[1]._y"+
"t.registers.and_encoder[1]._y"->"t.registers.and_encoder[1].y"-
~("t.registers.and_encoder[1]._y")->"t.registers.and_encoder[1].y"+
"t.registers.and_encoder[2].a"&"t.registers.and_encoder[2].b"->"t.registers.and_encoder[2]._y"-
~("t.registers.and_encoder[2].a"&"t.registers.and_encoder[2].b")->"t.registers.and_encoder[2]._y"+
"t.registers.and_encoder[2]._y"->"t.registers.and_encoder[2].y"-
~("t.registers.and_encoder[2]._y")->"t.registers.and_encoder[2].y"+
"t.registers.and_encoder[3].a"&"t.registers.and_encoder[3].b"->"t.registers.and_encoder[3]._y"-
~("t.registers.and_encoder[3].a"&"t.registers.and_encoder[3].b")->"t.registers.and_encoder[3]._y"+
"t.registers.and_encoder[3]._y"->"t.registers.and_encoder[3].y"-
~("t.registers.and_encoder[3]._y")->"t.registers.and_encoder[3].y"+
= "t.registers._in_temp.d[0].d[0]" "t.registers._in_temp.d[0].f"
= "t.registers._in_temp.d[0].d[1]" "t.registers._in_temp.d[0].t"
= "t.registers._in_temp.d[1].d[0]" "t.registers._in_temp.d[1].f"
@ -547,48 +425,8 @@
= "t.registers._in_temp.d[4].d[1]" "t.registers.val_input.in.d[4].d[1]"
= "t.registers._reset_mem_BX" "t.registers.reset_bufarray.in"
= "t.registers._reset_mem_BX" "t.registers.reset_buf_BXX.y"
"t.registers.and_encoder[0].a"&"t.registers.and_encoder[0].b"->"t.registers.and_encoder[0]._y"-
~("t.registers.and_encoder[0].a"&"t.registers.and_encoder[0].b")->"t.registers.and_encoder[0]._y"+
"t.registers.and_encoder[0]._y"->"t.registers.and_encoder[0].y"-
~("t.registers.and_encoder[0]._y")->"t.registers.and_encoder[0].y"+
"t.registers.and_encoder[1].a"&"t.registers.and_encoder[1].b"->"t.registers.and_encoder[1]._y"-
~("t.registers.and_encoder[1].a"&"t.registers.and_encoder[1].b")->"t.registers.and_encoder[1]._y"+
"t.registers.and_encoder[1]._y"->"t.registers.and_encoder[1].y"-
~("t.registers.and_encoder[1]._y")->"t.registers.and_encoder[1].y"+
"t.registers.and_encoder[2].a"&"t.registers.and_encoder[2].b"->"t.registers.and_encoder[2]._y"-
~("t.registers.and_encoder[2].a"&"t.registers.and_encoder[2].b")->"t.registers.and_encoder[2]._y"+
"t.registers.and_encoder[2]._y"->"t.registers.and_encoder[2].y"-
~("t.registers.and_encoder[2]._y")->"t.registers.and_encoder[2].y"+
"t.registers.and_encoder[3].a"&"t.registers.and_encoder[3].b"->"t.registers.and_encoder[3]._y"-
~("t.registers.and_encoder[3].a"&"t.registers.and_encoder[3].b")->"t.registers.and_encoder[3]._y"+
"t.registers.and_encoder[3]._y"->"t.registers.and_encoder[3].y"-
~("t.registers.and_encoder[3]._y")->"t.registers.and_encoder[3].y"+
"t.registers.and_encoder[4].a"&"t.registers.and_encoder[4].b"->"t.registers.and_encoder[4]._y"-
~("t.registers.and_encoder[4].a"&"t.registers.and_encoder[4].b")->"t.registers.and_encoder[4]._y"+
"t.registers.and_encoder[4]._y"->"t.registers.and_encoder[4].y"-
~("t.registers.and_encoder[4]._y")->"t.registers.and_encoder[4].y"+
"t.registers.and_encoder[5].a"&"t.registers.and_encoder[5].b"->"t.registers.and_encoder[5]._y"-
~("t.registers.and_encoder[5].a"&"t.registers.and_encoder[5].b")->"t.registers.and_encoder[5]._y"+
"t.registers.and_encoder[5]._y"->"t.registers.and_encoder[5].y"-
~("t.registers.and_encoder[5]._y")->"t.registers.and_encoder[5].y"+
"t.registers.and_encoder[6].a"&"t.registers.and_encoder[6].b"->"t.registers.and_encoder[6]._y"-
~("t.registers.and_encoder[6].a"&"t.registers.and_encoder[6].b")->"t.registers.and_encoder[6]._y"+
"t.registers.and_encoder[6]._y"->"t.registers.and_encoder[6].y"-
~("t.registers.and_encoder[6]._y")->"t.registers.and_encoder[6].y"+
"t.registers.and_encoder[7].a"&"t.registers.and_encoder[7].b"->"t.registers.and_encoder[7]._y"-
~("t.registers.and_encoder[7].a"&"t.registers.and_encoder[7].b")->"t.registers.and_encoder[7]._y"+
"t.registers.and_encoder[7]._y"->"t.registers.and_encoder[7].y"-
~("t.registers.and_encoder[7]._y")->"t.registers.and_encoder[7].y"+
= "t.registers._in_a_temp" "t.registers.ack_input_X.in"
= "t.registers._in_a_temp" "t.registers.ack_dly.out"
= "t.registers.supply.vss" "t.registers.clock_buffer[7].supply.vss"
= "t.registers.supply.vdd" "t.registers.clock_buffer[7].supply.vdd"
= "t.registers.supply.vss" "t.registers.clock_buffer[6].supply.vss"
= "t.registers.supply.vdd" "t.registers.clock_buffer[6].supply.vdd"
= "t.registers.supply.vss" "t.registers.clock_buffer[5].supply.vss"
= "t.registers.supply.vdd" "t.registers.clock_buffer[5].supply.vdd"
= "t.registers.supply.vss" "t.registers.clock_buffer[4].supply.vss"
= "t.registers.supply.vdd" "t.registers.clock_buffer[4].supply.vdd"
= "t.registers.supply.vss" "t.registers.clock_buffer[3].supply.vss"
= "t.registers.supply.vdd" "t.registers.clock_buffer[3].supply.vdd"
= "t.registers.supply.vss" "t.registers.clock_buffer[2].supply.vss"
@ -597,14 +435,6 @@
= "t.registers.supply.vdd" "t.registers.clock_buffer[1].supply.vdd"
= "t.registers.supply.vss" "t.registers.clock_buffer[0].supply.vss"
= "t.registers.supply.vdd" "t.registers.clock_buffer[0].supply.vdd"
= "t.registers.supply.vss" "t.registers.atree[7].supply.vss"
= "t.registers.supply.vdd" "t.registers.atree[7].supply.vdd"
= "t.registers.supply.vss" "t.registers.atree[6].supply.vss"
= "t.registers.supply.vdd" "t.registers.atree[6].supply.vdd"
= "t.registers.supply.vss" "t.registers.atree[5].supply.vss"
= "t.registers.supply.vdd" "t.registers.atree[5].supply.vdd"
= "t.registers.supply.vss" "t.registers.atree[4].supply.vss"
= "t.registers.supply.vdd" "t.registers.atree[4].supply.vdd"
= "t.registers.supply.vss" "t.registers.atree[3].supply.vss"
= "t.registers.supply.vdd" "t.registers.atree[3].supply.vdd"
= "t.registers.supply.vss" "t.registers.atree[2].supply.vss"
@ -627,30 +457,50 @@
= "t.registers.supply.vdd" "t.registers.val_input_X.supply.vdd"
= "t.registers.supply.vss" "t.registers.val_input.supply.vss"
= "t.registers.supply.vdd" "t.registers.val_input.supply.vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[7].vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[6].vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[5].vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[4].vdd"
= "t.registers.supply.vdd" "t.registers.ff[7].vdd"
= "t.registers.supply.vdd" "t.registers.ff[6].vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[3].vdd"
= "t.registers.supply.vdd" "t.registers.ff[5].vdd"
= "t.registers.supply.vdd" "t.registers.ff[4].vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[2].vdd"
= "t.registers.supply.vdd" "t.registers.ff[3].vdd"
= "t.registers.supply.vdd" "t.registers.ff[2].vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[1].vdd"
= "t.registers.supply.vdd" "t.registers.ff[1].vdd"
= "t.registers.supply.vdd" "t.registers.ff[0].vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[0].vdd"
= "t.registers.supply.vdd" "t.registers.reset_buf_BXX.vdd"
= "t.registers.supply.vdd" "t.registers.reset_buf_BX.vdd"
= "t.registers.supply.vss" "t.registers.and_encoder[7].vss"
= "t.registers.supply.vss" "t.registers.and_encoder[6].vss"
= "t.registers.supply.vss" "t.registers.and_encoder[5].vss"
= "t.registers.supply.vss" "t.registers.and_encoder[4].vss"
= "t.registers.supply.vdd" "t.registers.inv_clk.vdd"
= "t.registers.supply.vss" "t.registers.ff[7].vss"
= "t.registers.supply.vss" "t.registers.ff[6].vss"
= "t.registers.supply.vss" "t.registers.and_encoder[3].vss"
= "t.registers.supply.vss" "t.registers.ff[5].vss"
= "t.registers.supply.vss" "t.registers.ff[4].vss"
= "t.registers.supply.vss" "t.registers.and_encoder[2].vss"
= "t.registers.supply.vss" "t.registers.ff[3].vss"
= "t.registers.supply.vss" "t.registers.ff[2].vss"
= "t.registers.supply.vss" "t.registers.and_encoder[1].vss"
= "t.registers.supply.vss" "t.registers.ff[1].vss"
= "t.registers.supply.vss" "t.registers.ff[0].vss"
= "t.registers.supply.vss" "t.registers.and_encoder[0].vss"
= "t.registers.supply.vss" "t.registers.reset_buf_BXX.vss"
= "t.registers.supply.vss" "t.registers.reset_buf_BX.vss"
= "t.registers.supply.vss" "t.registers.inv_clk.vss"
= "t.registers.dly_cfg[0]" "t.registers.ack_dly.s[0]"
= "t.registers.dly_cfg[1]" "t.registers.ack_dly.s[1]"
= "t.registers.dly_cfg[0]" "t.registers.clk_dly.s[0]"
= "t.registers.dly_cfg[1]" "t.registers.clk_dly.s[1]"
"t.registers.inv_clk.a"->"t.registers.inv_clk.y"-
~("t.registers.inv_clk.a")->"t.registers.inv_clk.y"+
= "t.registers.data[3].d[0]" "t.registers.ff[6].q"
= "t.registers.data[3].d[1]" "t.registers.ff[7].q"
= "t.registers.data[2].d[0]" "t.registers.ff[4].q"
= "t.registers.data[2].d[1]" "t.registers.ff[5].q"
= "t.registers.data[1].d[0]" "t.registers.ff[2].q"
= "t.registers.data[1].d[1]" "t.registers.ff[3].q"
= "t.registers.data[0].d[0]" "t.registers.ff[0].q"
= "t.registers.data[0].d[1]" "t.registers.ff[1].q"
"t.registers.val_input_X.buf1.a"->"t.registers.val_input_X.buf1._y"-
~("t.registers.val_input_X.buf1.a")->"t.registers.val_input_X.buf1._y"+
"t.registers.val_input_X.buf1._y"->"t.registers.val_input_X.buf1.y"-
@ -667,30 +517,54 @@
= "t.registers.ack_input_X.supply.vss" "t.registers.ack_input_X.buf1.vss"
= "t.registers.ack_input_X.out" "t.registers.ack_input_X.buf1.y"
= "t.registers.ack_input_X.in" "t.registers.ack_input_X.buf1.a"
= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[8]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[7].out[1]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[7].out[0]"
= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[7]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[6].out[1]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[6].out[0]"
= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[6]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[5].out[1]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[5].out[0]"
= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[5]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[4].out[1]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[4].out[0]"
= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[4]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[3].out[1]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[3].out[0]"
= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[3]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[2].out[1]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[2].out[0]"
= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[2]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[1].out[1]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[1].out[0]"
= "t.registers._clock_buffer_out[0]" "t.registers._clock_buffer_out[1]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[0].out[1]"
= "t.registers._clock_buffer_out[0]" "t.registers.clock_buffer[0].out[0]"
= "t.registers.atree[0].supply.vdd" "t.registers.atree[0].and2s[0].vdd"
= "t.registers.atree[0].supply.vss" "t.registers.atree[0].and2s[0].vss"
"t.registers.atree[0].and2s[0].a"&"t.registers.atree[0].and2s[0].b"->"t.registers.atree[0].and2s[0]._y"-
~("t.registers.atree[0].and2s[0].a"&"t.registers.atree[0].and2s[0].b")->"t.registers.atree[0].and2s[0]._y"+
"t.registers.atree[0].and2s[0]._y"->"t.registers.atree[0].and2s[0].y"-
~("t.registers.atree[0].and2s[0]._y")->"t.registers.atree[0].and2s[0].y"+
= "t.registers.atree[0].in[0]" "t.registers.atree[0].and2s[0].a"
= "t.registers.atree[0].in[0]" "t.registers.atree[0].tmp[0]"
= "t.registers.atree[0].in[1]" "t.registers.atree[0].and2s[0].b"
= "t.registers.atree[0].in[1]" "t.registers.atree[0].tmp[1]"
= "t.registers.atree[0].out" "t.registers.atree[0].and2s[0].y"
= "t.registers.atree[0].out" "t.registers.atree[0].tmp[2]"
= "t.registers.atree[1].supply.vdd" "t.registers.atree[1].and2s[0].vdd"
= "t.registers.atree[1].supply.vss" "t.registers.atree[1].and2s[0].vss"
"t.registers.atree[1].and2s[0].a"&"t.registers.atree[1].and2s[0].b"->"t.registers.atree[1].and2s[0]._y"-
~("t.registers.atree[1].and2s[0].a"&"t.registers.atree[1].and2s[0].b")->"t.registers.atree[1].and2s[0]._y"+
"t.registers.atree[1].and2s[0]._y"->"t.registers.atree[1].and2s[0].y"-
~("t.registers.atree[1].and2s[0]._y")->"t.registers.atree[1].and2s[0].y"+
= "t.registers.atree[1].in[0]" "t.registers.atree[1].and2s[0].a"
= "t.registers.atree[1].in[0]" "t.registers.atree[1].tmp[0]"
= "t.registers.atree[1].in[1]" "t.registers.atree[1].and2s[0].b"
= "t.registers.atree[1].in[1]" "t.registers.atree[1].tmp[1]"
= "t.registers.atree[1].out" "t.registers.atree[1].and2s[0].y"
= "t.registers.atree[1].out" "t.registers.atree[1].tmp[2]"
= "t.registers.atree[2].supply.vdd" "t.registers.atree[2].and2s[0].vdd"
= "t.registers.atree[2].supply.vss" "t.registers.atree[2].and2s[0].vss"
"t.registers.atree[2].and2s[0].a"&"t.registers.atree[2].and2s[0].b"->"t.registers.atree[2].and2s[0]._y"-
~("t.registers.atree[2].and2s[0].a"&"t.registers.atree[2].and2s[0].b")->"t.registers.atree[2].and2s[0]._y"+
"t.registers.atree[2].and2s[0]._y"->"t.registers.atree[2].and2s[0].y"-
~("t.registers.atree[2].and2s[0]._y")->"t.registers.atree[2].and2s[0].y"+
= "t.registers.atree[2].in[0]" "t.registers.atree[2].and2s[0].a"
= "t.registers.atree[2].in[0]" "t.registers.atree[2].tmp[0]"
= "t.registers.atree[2].in[1]" "t.registers.atree[2].and2s[0].b"
= "t.registers.atree[2].in[1]" "t.registers.atree[2].tmp[1]"
= "t.registers.atree[2].out" "t.registers.atree[2].and2s[0].y"
= "t.registers.atree[2].out" "t.registers.atree[2].tmp[2]"
= "t.registers.atree[3].supply.vdd" "t.registers.atree[3].and2s[0].vdd"
= "t.registers.atree[3].supply.vss" "t.registers.atree[3].and2s[0].vss"
"t.registers.atree[3].and2s[0].a"&"t.registers.atree[3].and2s[0].b"->"t.registers.atree[3].and2s[0]._y"-
~("t.registers.atree[3].and2s[0].a"&"t.registers.atree[3].and2s[0].b")->"t.registers.atree[3].and2s[0]._y"+
"t.registers.atree[3].and2s[0]._y"->"t.registers.atree[3].and2s[0].y"-
~("t.registers.atree[3].and2s[0]._y")->"t.registers.atree[3].and2s[0].y"+
= "t.registers.atree[3].in[0]" "t.registers.atree[3].and2s[0].a"
= "t.registers.atree[3].in[0]" "t.registers.atree[3].tmp[0]"
= "t.registers.atree[3].in[1]" "t.registers.atree[3].and2s[0].b"
= "t.registers.atree[3].in[1]" "t.registers.atree[3].tmp[1]"
= "t.registers.atree[3].out" "t.registers.atree[3].and2s[0].y"
= "t.registers.atree[3].out" "t.registers.atree[3].tmp[2]"
~"t.registers.val_input.ct.C2Els[0].c1"&~"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"+
"t.registers.val_input.ct.C2Els[0].c1"&"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"-
"t.registers.val_input.ct.C2Els[0]._y"->"t.registers.val_input.ct.C2Els[0].y"-
@ -882,102 +756,6 @@
~("t.registers.reset_buf_BXX.a")->"t.registers.reset_buf_BXX._y"+
"t.registers.reset_buf_BXX._y"->"t.registers.reset_buf_BXX.y"-
~("t.registers.reset_buf_BXX._y")->"t.registers.reset_buf_BXX.y"+
= "t.registers.atree[0].supply.vdd" "t.registers.atree[0].and2s[0].vdd"
= "t.registers.atree[0].supply.vss" "t.registers.atree[0].and2s[0].vss"
"t.registers.atree[0].and2s[0].a"&"t.registers.atree[0].and2s[0].b"->"t.registers.atree[0].and2s[0]._y"-
~("t.registers.atree[0].and2s[0].a"&"t.registers.atree[0].and2s[0].b")->"t.registers.atree[0].and2s[0]._y"+
"t.registers.atree[0].and2s[0]._y"->"t.registers.atree[0].and2s[0].y"-
~("t.registers.atree[0].and2s[0]._y")->"t.registers.atree[0].and2s[0].y"+
= "t.registers.atree[0].in[0]" "t.registers.atree[0].and2s[0].a"
= "t.registers.atree[0].in[0]" "t.registers.atree[0].tmp[0]"
= "t.registers.atree[0].in[1]" "t.registers.atree[0].and2s[0].b"
= "t.registers.atree[0].in[1]" "t.registers.atree[0].tmp[1]"
= "t.registers.atree[0].out" "t.registers.atree[0].and2s[0].y"
= "t.registers.atree[0].out" "t.registers.atree[0].tmp[2]"
= "t.registers.atree[1].supply.vdd" "t.registers.atree[1].and2s[0].vdd"
= "t.registers.atree[1].supply.vss" "t.registers.atree[1].and2s[0].vss"
"t.registers.atree[1].and2s[0].a"&"t.registers.atree[1].and2s[0].b"->"t.registers.atree[1].and2s[0]._y"-
~("t.registers.atree[1].and2s[0].a"&"t.registers.atree[1].and2s[0].b")->"t.registers.atree[1].and2s[0]._y"+
"t.registers.atree[1].and2s[0]._y"->"t.registers.atree[1].and2s[0].y"-
~("t.registers.atree[1].and2s[0]._y")->"t.registers.atree[1].and2s[0].y"+
= "t.registers.atree[1].in[0]" "t.registers.atree[1].and2s[0].a"
= "t.registers.atree[1].in[0]" "t.registers.atree[1].tmp[0]"
= "t.registers.atree[1].in[1]" "t.registers.atree[1].and2s[0].b"
= "t.registers.atree[1].in[1]" "t.registers.atree[1].tmp[1]"
= "t.registers.atree[1].out" "t.registers.atree[1].and2s[0].y"
= "t.registers.atree[1].out" "t.registers.atree[1].tmp[2]"
= "t.registers.atree[2].supply.vdd" "t.registers.atree[2].and2s[0].vdd"
= "t.registers.atree[2].supply.vss" "t.registers.atree[2].and2s[0].vss"
"t.registers.atree[2].and2s[0].a"&"t.registers.atree[2].and2s[0].b"->"t.registers.atree[2].and2s[0]._y"-
~("t.registers.atree[2].and2s[0].a"&"t.registers.atree[2].and2s[0].b")->"t.registers.atree[2].and2s[0]._y"+
"t.registers.atree[2].and2s[0]._y"->"t.registers.atree[2].and2s[0].y"-
~("t.registers.atree[2].and2s[0]._y")->"t.registers.atree[2].and2s[0].y"+
= "t.registers.atree[2].in[0]" "t.registers.atree[2].and2s[0].a"
= "t.registers.atree[2].in[0]" "t.registers.atree[2].tmp[0]"
= "t.registers.atree[2].in[1]" "t.registers.atree[2].and2s[0].b"
= "t.registers.atree[2].in[1]" "t.registers.atree[2].tmp[1]"
= "t.registers.atree[2].out" "t.registers.atree[2].and2s[0].y"
= "t.registers.atree[2].out" "t.registers.atree[2].tmp[2]"
= "t.registers.atree[3].supply.vdd" "t.registers.atree[3].and2s[0].vdd"
= "t.registers.atree[3].supply.vss" "t.registers.atree[3].and2s[0].vss"
"t.registers.atree[3].and2s[0].a"&"t.registers.atree[3].and2s[0].b"->"t.registers.atree[3].and2s[0]._y"-
~("t.registers.atree[3].and2s[0].a"&"t.registers.atree[3].and2s[0].b")->"t.registers.atree[3].and2s[0]._y"+
"t.registers.atree[3].and2s[0]._y"->"t.registers.atree[3].and2s[0].y"-
~("t.registers.atree[3].and2s[0]._y")->"t.registers.atree[3].and2s[0].y"+
= "t.registers.atree[3].in[0]" "t.registers.atree[3].and2s[0].a"
= "t.registers.atree[3].in[0]" "t.registers.atree[3].tmp[0]"
= "t.registers.atree[3].in[1]" "t.registers.atree[3].and2s[0].b"
= "t.registers.atree[3].in[1]" "t.registers.atree[3].tmp[1]"
= "t.registers.atree[3].out" "t.registers.atree[3].and2s[0].y"
= "t.registers.atree[3].out" "t.registers.atree[3].tmp[2]"
= "t.registers.atree[4].supply.vdd" "t.registers.atree[4].and2s[0].vdd"
= "t.registers.atree[4].supply.vss" "t.registers.atree[4].and2s[0].vss"
"t.registers.atree[4].and2s[0].a"&"t.registers.atree[4].and2s[0].b"->"t.registers.atree[4].and2s[0]._y"-
~("t.registers.atree[4].and2s[0].a"&"t.registers.atree[4].and2s[0].b")->"t.registers.atree[4].and2s[0]._y"+
"t.registers.atree[4].and2s[0]._y"->"t.registers.atree[4].and2s[0].y"-
~("t.registers.atree[4].and2s[0]._y")->"t.registers.atree[4].and2s[0].y"+
= "t.registers.atree[4].in[0]" "t.registers.atree[4].and2s[0].a"
= "t.registers.atree[4].in[0]" "t.registers.atree[4].tmp[0]"
= "t.registers.atree[4].in[1]" "t.registers.atree[4].and2s[0].b"
= "t.registers.atree[4].in[1]" "t.registers.atree[4].tmp[1]"
= "t.registers.atree[4].out" "t.registers.atree[4].and2s[0].y"
= "t.registers.atree[4].out" "t.registers.atree[4].tmp[2]"
= "t.registers.atree[5].supply.vdd" "t.registers.atree[5].and2s[0].vdd"
= "t.registers.atree[5].supply.vss" "t.registers.atree[5].and2s[0].vss"
"t.registers.atree[5].and2s[0].a"&"t.registers.atree[5].and2s[0].b"->"t.registers.atree[5].and2s[0]._y"-
~("t.registers.atree[5].and2s[0].a"&"t.registers.atree[5].and2s[0].b")->"t.registers.atree[5].and2s[0]._y"+
"t.registers.atree[5].and2s[0]._y"->"t.registers.atree[5].and2s[0].y"-
~("t.registers.atree[5].and2s[0]._y")->"t.registers.atree[5].and2s[0].y"+
= "t.registers.atree[5].in[0]" "t.registers.atree[5].and2s[0].a"
= "t.registers.atree[5].in[0]" "t.registers.atree[5].tmp[0]"
= "t.registers.atree[5].in[1]" "t.registers.atree[5].and2s[0].b"
= "t.registers.atree[5].in[1]" "t.registers.atree[5].tmp[1]"
= "t.registers.atree[5].out" "t.registers.atree[5].and2s[0].y"
= "t.registers.atree[5].out" "t.registers.atree[5].tmp[2]"
= "t.registers.atree[6].supply.vdd" "t.registers.atree[6].and2s[0].vdd"
= "t.registers.atree[6].supply.vss" "t.registers.atree[6].and2s[0].vss"
"t.registers.atree[6].and2s[0].a"&"t.registers.atree[6].and2s[0].b"->"t.registers.atree[6].and2s[0]._y"-
~("t.registers.atree[6].and2s[0].a"&"t.registers.atree[6].and2s[0].b")->"t.registers.atree[6].and2s[0]._y"+
"t.registers.atree[6].and2s[0]._y"->"t.registers.atree[6].and2s[0].y"-
~("t.registers.atree[6].and2s[0]._y")->"t.registers.atree[6].and2s[0].y"+
= "t.registers.atree[6].in[0]" "t.registers.atree[6].and2s[0].a"
= "t.registers.atree[6].in[0]" "t.registers.atree[6].tmp[0]"
= "t.registers.atree[6].in[1]" "t.registers.atree[6].and2s[0].b"
= "t.registers.atree[6].in[1]" "t.registers.atree[6].tmp[1]"
= "t.registers.atree[6].out" "t.registers.atree[6].and2s[0].y"
= "t.registers.atree[6].out" "t.registers.atree[6].tmp[2]"
= "t.registers.atree[7].supply.vdd" "t.registers.atree[7].and2s[0].vdd"
= "t.registers.atree[7].supply.vss" "t.registers.atree[7].and2s[0].vss"
"t.registers.atree[7].and2s[0].a"&"t.registers.atree[7].and2s[0].b"->"t.registers.atree[7].and2s[0]._y"-
~("t.registers.atree[7].and2s[0].a"&"t.registers.atree[7].and2s[0].b")->"t.registers.atree[7].and2s[0]._y"+
"t.registers.atree[7].and2s[0]._y"->"t.registers.atree[7].and2s[0].y"-
~("t.registers.atree[7].and2s[0]._y")->"t.registers.atree[7].and2s[0].y"+
= "t.registers.atree[7].in[0]" "t.registers.atree[7].and2s[0].a"
= "t.registers.atree[7].in[0]" "t.registers.atree[7].tmp[0]"
= "t.registers.atree[7].in[1]" "t.registers.atree[7].and2s[0].b"
= "t.registers.atree[7].in[1]" "t.registers.atree[7].tmp[1]"
= "t.registers.atree[7].out" "t.registers.atree[7].and2s[0].y"
= "t.registers.atree[7].out" "t.registers.atree[7].tmp[2]"
"t.registers.clock_buffer[0].buf1.a"->"t.registers.clock_buffer[0].buf1._y"-
~("t.registers.clock_buffer[0].buf1.a")->"t.registers.clock_buffer[0].buf1._y"+
"t.registers.clock_buffer[0].buf1._y"->"t.registers.clock_buffer[0].buf1.y"-
@ -1014,49 +792,9 @@
= "t.registers.clock_buffer[3].out[0]" "t.registers.clock_buffer[3].out[1]"
= "t.registers.clock_buffer[3].out[0]" "t.registers.clock_buffer[3].buf1.y"
= "t.registers.clock_buffer[3].in" "t.registers.clock_buffer[3].buf1.a"
"t.registers.clock_buffer[4].buf1.a"->"t.registers.clock_buffer[4].buf1._y"-
~("t.registers.clock_buffer[4].buf1.a")->"t.registers.clock_buffer[4].buf1._y"+
"t.registers.clock_buffer[4].buf1._y"->"t.registers.clock_buffer[4].buf1.y"-
~("t.registers.clock_buffer[4].buf1._y")->"t.registers.clock_buffer[4].buf1.y"+
= "t.registers.clock_buffer[4].supply.vdd" "t.registers.clock_buffer[4].buf1.vdd"
= "t.registers.clock_buffer[4].supply.vss" "t.registers.clock_buffer[4].buf1.vss"
= "t.registers.clock_buffer[4].out[0]" "t.registers.clock_buffer[4].out[1]"
= "t.registers.clock_buffer[4].out[0]" "t.registers.clock_buffer[4].buf1.y"
= "t.registers.clock_buffer[4].in" "t.registers.clock_buffer[4].buf1.a"
"t.registers.clock_buffer[5].buf1.a"->"t.registers.clock_buffer[5].buf1._y"-
~("t.registers.clock_buffer[5].buf1.a")->"t.registers.clock_buffer[5].buf1._y"+
"t.registers.clock_buffer[5].buf1._y"->"t.registers.clock_buffer[5].buf1.y"-
~("t.registers.clock_buffer[5].buf1._y")->"t.registers.clock_buffer[5].buf1.y"+
= "t.registers.clock_buffer[5].supply.vdd" "t.registers.clock_buffer[5].buf1.vdd"
= "t.registers.clock_buffer[5].supply.vss" "t.registers.clock_buffer[5].buf1.vss"
= "t.registers.clock_buffer[5].out[0]" "t.registers.clock_buffer[5].out[1]"
= "t.registers.clock_buffer[5].out[0]" "t.registers.clock_buffer[5].buf1.y"
= "t.registers.clock_buffer[5].in" "t.registers.clock_buffer[5].buf1.a"
"t.registers.clock_buffer[6].buf1.a"->"t.registers.clock_buffer[6].buf1._y"-
~("t.registers.clock_buffer[6].buf1.a")->"t.registers.clock_buffer[6].buf1._y"+
"t.registers.clock_buffer[6].buf1._y"->"t.registers.clock_buffer[6].buf1.y"-
~("t.registers.clock_buffer[6].buf1._y")->"t.registers.clock_buffer[6].buf1.y"+
= "t.registers.clock_buffer[6].supply.vdd" "t.registers.clock_buffer[6].buf1.vdd"
= "t.registers.clock_buffer[6].supply.vss" "t.registers.clock_buffer[6].buf1.vss"
= "t.registers.clock_buffer[6].out[0]" "t.registers.clock_buffer[6].out[1]"
= "t.registers.clock_buffer[6].out[0]" "t.registers.clock_buffer[6].buf1.y"
= "t.registers.clock_buffer[6].in" "t.registers.clock_buffer[6].buf1.a"
"t.registers.clock_buffer[7].buf1.a"->"t.registers.clock_buffer[7].buf1._y"-
~("t.registers.clock_buffer[7].buf1.a")->"t.registers.clock_buffer[7].buf1._y"+
"t.registers.clock_buffer[7].buf1._y"->"t.registers.clock_buffer[7].buf1.y"-
~("t.registers.clock_buffer[7].buf1._y")->"t.registers.clock_buffer[7].buf1.y"+
= "t.registers.clock_buffer[7].supply.vdd" "t.registers.clock_buffer[7].buf1.vdd"
= "t.registers.clock_buffer[7].supply.vss" "t.registers.clock_buffer[7].buf1.vss"
= "t.registers.clock_buffer[7].out[0]" "t.registers.clock_buffer[7].out[1]"
= "t.registers.clock_buffer[7].out[0]" "t.registers.clock_buffer[7].buf1.y"
= "t.registers.clock_buffer[7].in" "t.registers.clock_buffer[7].buf1.a"
= "t.registers._in_v_temp" "t.registers.clk_dly.in"
= "t.registers._in_v_temp" "t.registers.val_input_X.in"
= "t.registers._in_v_temp" "t.registers.val_input.out"
= "t.registers._clock" "t.registers.and_encoder[7].b"
= "t.registers._clock" "t.registers.and_encoder[6].b"
= "t.registers._clock" "t.registers.and_encoder[5].b"
= "t.registers._clock" "t.registers.and_encoder[4].b"
= "t.registers._clock" "t.registers.and_encoder[3].b"
= "t.registers._clock" "t.registers.and_encoder[2].b"
= "t.registers._clock" "t.registers.and_encoder[1].b"

2
test/unit_tests/register_write/test.act
View File

@ -31,7 +31,7 @@ import globals;
open tmpl::dataflow_neuro;
// 2 bits encoder, 2 bits long words, 2 delays????
defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[2<<2]; bool? dly_cfg[2]){
defproc register_test (avMx1of2<1+2+2> in; d1of<2> data[1<<2]; bool? dly_cfg[2]){
register_rw<2,2,2> registers(.in=in,.data = data);
//Low active Reset

9
test/unit_tests/register_write/test.prsim
View File

@ -1,13 +1,12 @@
watchall
system "echo '[0] start test'"
set Reset 1
set-qdi-channel-neutral "t.in" 5
set t.data[0].d[0] 0
set t.data[0].d[1] 0
set t.data[1].d[0] 0
set t.data[1].d[1] 0
set Reset 0
cycle
status X
mode run
@ -16,7 +15,6 @@ assert t.data[0].d[0] 0
assert t.data[0].d[1] 0
assert t.data[1].d[0] 0
assert t.data[1].d[1] 0
set Reset 0
cycle
system "echo '[1] reset completed'"
# Set delay config lines
@ -28,14 +26,15 @@ system "echo '[2] delay line set'"
set-qdi-channel-valid "t.in" 5 3
cycle
assert-qdi-channel-valid "t.in" 5 3
assert t.registers._clock 1
assert t.registers._clock 0
assert t.registers._out_encoder[0] 1
assert t.registers._out_encoder[1] 0
assert t.registers._out_encoder[2] 0
assert t.registers._out_encoder[3] 0
cycle
set-qdi-channel-neutral "t.in" 5
cycle
assert t.registers._clock 0
assert t.registers._clock 1
assert t.registers.ff[0].q 1
assert t.registers.ff[1].q 1
system "echo '[3] clock checked'"