686 lines
29 KiB
Verilog
686 lines
29 KiB
Verilog
//
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// Verilog module for: BUF_X6<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
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output y;
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input a;
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// -- signals ---
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reg y;
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wire a;
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reg _y;
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// --- instances
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endmodule
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//
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// Verilog module for: sigbuf<15>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
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input in;
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output \out[0] ;
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// -- signals ---
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wire in;
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reg \out[0] ;
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// --- instances
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_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6 (.y(\out[0] ), .a(in));
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endmodule
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//
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// Verilog module for: A_3C_RB_X4<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
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output y;
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input c1;
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input c2;
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input c3;
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input pr_B;
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input sr_B;
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// -- signals ---
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wire sr_B;
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wire pr_B;
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wire c3;
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wire c1;
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reg _y;
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reg y;
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wire c2;
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// --- instances
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endmodule
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//
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// Verilog module for: BUF_X4<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
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output y;
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input a;
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// -- signals ---
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reg _y;
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wire a;
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reg y;
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// --- instances
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endmodule
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//
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// Verilog module for: INV_X1<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
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output y;
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input a;
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// -- signals ---
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reg y;
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wire a;
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// --- instances
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endmodule
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//
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// Verilog module for: A_2C_B_X1<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
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output y;
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input c1;
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input c2;
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// -- signals ---
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reg y;
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reg _y;
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wire c2;
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wire c1;
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// --- instances
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endmodule
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//
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// Verilog module for: A_3C_B_X1<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
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output y;
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input c1;
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input c2;
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input c3;
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// -- signals ---
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reg _y;
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reg y;
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wire c3;
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wire c1;
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wire c2;
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// --- instances
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endmodule
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//
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// Verilog module for: ctree<15>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
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input \in[0] ;
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input \in[1] ;
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input \in[2] ;
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input \in[3] ;
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input \in[4] ;
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input \in[5] ;
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input \in[6] ;
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input \in[7] ;
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input \in[8] ;
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input \in[9] ;
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input \in[10] ;
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input \in[11] ;
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input \in[12] ;
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input \in[13] ;
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input \in[14] ;
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output out;
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// -- signals ---
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wire \in[4] ;
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wire \in[11] ;
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wire \in[12] ;
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reg \tmp[21] ;
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wire \in[3] ;
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reg out;
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reg \tmp[23] ;
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wire \in[6] ;
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wire \in[0] ;
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reg \tmp[18] ;
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wire \in[10] ;
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reg \tmp[15] ;
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reg \tmp[16] ;
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wire \in[13] ;
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wire \in[1] ;
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wire \in[9] ;
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wire \in[2] ;
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wire \in[5] ;
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reg \tmp[24] ;
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wire \in[14] ;
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reg \tmp[19] ;
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wire \in[7] ;
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reg \tmp[22] ;
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reg \tmp[20] ;
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wire \in[8] ;
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reg \tmp[17] ;
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// --- instances
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
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endmodule
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//
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// Verilog module for: OR2_X1<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
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output y;
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input a;
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input b;
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// -- signals ---
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reg y;
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wire a;
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reg _y;
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wire b;
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// --- instances
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endmodule
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//
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// Verilog module for: vtree<15>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
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input \in.d[0].d[0] ;
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input \in.d[0].d[1] ;
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input \in.d[1].d[0] ;
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input \in.d[1].d[1] ;
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input \in.d[2].d[0] ;
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input \in.d[2].d[1] ;
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input \in.d[3].d[0] ;
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input \in.d[3].d[1] ;
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input \in.d[4].d[0] ;
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input \in.d[4].d[1] ;
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input \in.d[5].d[0] ;
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input \in.d[5].d[1] ;
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input \in.d[6].d[0] ;
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input \in.d[6].d[1] ;
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input \in.d[7].d[0] ;
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input \in.d[7].d[1] ;
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input \in.d[8].d[0] ;
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input \in.d[8].d[1] ;
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input \in.d[9].d[0] ;
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input \in.d[9].d[1] ;
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input \in.d[10].d[0] ;
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input \in.d[10].d[1] ;
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input \in.d[11].d[0] ;
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input \in.d[11].d[1] ;
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input \in.d[12].d[0] ;
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input \in.d[12].d[1] ;
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input \in.d[13].d[0] ;
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input \in.d[13].d[1] ;
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input \in.d[14].d[0] ;
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input \in.d[14].d[1] ;
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output out;
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// -- signals ---
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reg \ct.in[14] ;
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reg \ct.in[13] ;
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wire \in.d[7].d[0] ;
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wire \in.d[1].d[0] ;
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wire \in.d[0].d[0] ;
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reg \ct.in[4] ;
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reg out;
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wire \in.d[10].d[0] ;
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wire \in.d[4].d[1] ;
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reg \ct.in[3] ;
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wire \in.d[9].d[1] ;
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wire \in.d[1].d[1] ;
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wire \in.d[2].d[0] ;
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wire \in.d[10].d[1] ;
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reg \ct.in[8] ;
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wire \in.d[12].d[0] ;
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wire \in.d[5].d[0] ;
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wire \in.d[4].d[0] ;
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reg \ct.in[10] ;
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reg \ct.in[0] ;
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wire \in.d[11].d[0] ;
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wire \in.d[7].d[1] ;
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wire \in.d[3].d[1] ;
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reg \ct.in[11] ;
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reg \ct.in[2] ;
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reg \ct.in[9] ;
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wire \in.d[13].d[0] ;
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wire \in.d[14].d[1] ;
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wire \in.d[11].d[1] ;
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wire \in.d[13].d[1] ;
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wire \in.d[0].d[1] ;
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reg \ct.in[1] ;
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wire \in.d[14].d[0] ;
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wire \in.d[12].d[1] ;
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wire \in.d[9].d[0] ;
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wire \in.d[2].d[1] ;
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reg \ct.in[5] ;
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wire \in.d[5].d[1] ;
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reg \ct.in[12] ;
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reg \ct.in[6] ;
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wire \in.d[3].d[0] ;
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wire \in.d[8].d[0] ;
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wire \in.d[8].d[1] ;
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reg \ct.in[7] ;
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wire \in.d[6].d[0] ;
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wire \in.d[6].d[1] ;
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// --- instances
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_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
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endmodule
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//
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// Verilog module for: A_1C1P_X1<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
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output y;
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input c1;
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input p1;
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// -- signals ---
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reg y;
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wire c1;
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wire p1;
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// --- instances
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endmodule
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//
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// Verilog module for: BUF_X1<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
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output y;
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input a;
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// -- signals ---
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reg y;
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wire a;
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reg _y;
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// --- instances
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endmodule
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//
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// Verilog module for: A_2C1N_RB_X4<>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
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output y;
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input c1;
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input c2;
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input n1;
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input pr_B;
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input sr_B;
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// -- signals ---
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reg y;
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wire pr_B;
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wire c2;
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wire n1;
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wire c1;
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reg _y;
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wire sr_B;
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// --- instances
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endmodule
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//
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// Verilog module for: buffer<15>
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//
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module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
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input \in.d.d[0].d[0] ;
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input \in.d.d[0].d[1] ;
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input \in.d.d[1].d[0] ;
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input \in.d.d[1].d[1] ;
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input \in.d.d[2].d[0] ;
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input \in.d.d[2].d[1] ;
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input \in.d.d[3].d[0] ;
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input \in.d.d[3].d[1] ;
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input \in.d.d[4].d[0] ;
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input \in.d.d[4].d[1] ;
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input \in.d.d[5].d[0] ;
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input \in.d.d[5].d[1] ;
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input \in.d.d[6].d[0] ;
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input \in.d.d[6].d[1] ;
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input \in.d.d[7].d[0] ;
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input \in.d.d[7].d[1] ;
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input \in.d.d[8].d[0] ;
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input \in.d.d[8].d[1] ;
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input \in.d.d[9].d[0] ;
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input \in.d.d[9].d[1] ;
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input \in.d.d[10].d[0] ;
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input \in.d.d[10].d[1] ;
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input \in.d.d[11].d[0] ;
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input \in.d.d[11].d[1] ;
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input \in.d.d[12].d[0] ;
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input \in.d.d[12].d[1] ;
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input \in.d.d[13].d[0] ;
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input \in.d.d[13].d[1] ;
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input \in.d.d[14].d[0] ;
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input \in.d.d[14].d[1] ;
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output \in.a ;
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output \in.v ;
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output \out.d.d[0].d[0] ;
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output \out.d.d[0].d[1] ;
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output \out.d.d[1].d[0] ;
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output \out.d.d[1].d[1] ;
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output \out.d.d[2].d[0] ;
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output \out.d.d[2].d[1] ;
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output \out.d.d[3].d[0] ;
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output \out.d.d[3].d[1] ;
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output \out.d.d[4].d[0] ;
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output \out.d.d[4].d[1] ;
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output \out.d.d[5].d[0] ;
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output \out.d.d[5].d[1] ;
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output \out.d.d[6].d[0] ;
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output \out.d.d[6].d[1] ;
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output \out.d.d[7].d[0] ;
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output \out.d.d[7].d[1] ;
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output \out.d.d[8].d[0] ;
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output \out.d.d[8].d[1] ;
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output \out.d.d[9].d[0] ;
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output \out.d.d[9].d[1] ;
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output \out.d.d[10].d[0] ;
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output \out.d.d[10].d[1] ;
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output \out.d.d[11].d[0] ;
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output \out.d.d[11].d[1] ;
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output \out.d.d[12].d[0] ;
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output \out.d.d[12].d[1] ;
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output \out.d.d[13].d[0] ;
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output \out.d.d[13].d[1] ;
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output \out.d.d[14].d[0] ;
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output \out.d.d[14].d[1] ;
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input \out.a ;
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input \out.v ;
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input reset_B;
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// -- signals ---
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reg \out.d.d[8].d[0] ;
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reg \out.d.d[6].d[1] ;
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reg \out.d.d[5].d[1] ;
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reg \_en_X_f[0] ;
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wire \in.d.d[14].d[0] ;
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wire \in.d.d[12].d[1] ;
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reg \out.d.d[12].d[1] ;
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wire \in.d.d[5].d[0] ;
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reg \out.d.d[11].d[0] ;
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reg \out.d.d[7].d[0] ;
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reg _reset_BX;
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reg \_reset_BXX[0] ;
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wire \in.d.d[14].d[1] ;
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wire \in.d.d[10].d[1] ;
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wire \in.d.d[2].d[0] ;
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wire \out.a ;
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reg \out.d.d[0].d[0] ;
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wire \in.d.d[0].d[0] ;
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reg \out.d.d[10].d[1] ;
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wire \in.d.d[11].d[0] ;
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wire \in.d.d[7].d[1] ;
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wire \in.d.d[3].d[1] ;
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reg _in_v;
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reg \in.v ;
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reg _out_a_B;
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wire \in.d.d[9].d[1] ;
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wire \in.d.d[9].d[0] ;
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wire \in.d.d[4].d[1] ;
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reg \out.d.d[10].d[0] ;
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wire \in.d.d[1].d[1] ;
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wire \in.d.d[12].d[0] ;
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wire \in.d.d[1].d[0] ;
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reg \_out_a_BX_f[0] ;
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reg \out.d.d[3].d[1] ;
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reg \out.d.d[0].d[1] ;
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reg \out.d.d[2].d[1] ;
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reg \out.d.d[4].d[1] ;
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wire reset_B;
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wire \in.d.d[8].d[0] ;
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reg \out.d.d[12].d[0] ;
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wire \in.d.d[5].d[1] ;
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reg \out.d.d[9].d[0] ;
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reg \out.d.d[7].d[1] ;
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reg \_out_a_BX_t[0] ;
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wire \in.d.d[10].d[0] ;
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reg \out.d.d[1].d[0] ;
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wire \in.d.d[6].d[0] ;
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wire \in.d.d[7].d[0] ;
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wire \in.d.d[13].d[1] ;
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wire \out.v ;
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reg \out.d.d[2].d[0] ;
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wire \in.d.d[13].d[0] ;
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wire \in.d.d[11].d[1] ;
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wire \in.d.d[6].d[1] ;
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reg \out.d.d[3].d[0] ;
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reg \out.d.d[11].d[1] ;
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reg \out.d.d[9].d[1] ;
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wire \in.d.d[3].d[0] ;
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reg _en;
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reg \out.d.d[13].d[0] ;
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reg \out.d.d[5].d[0] ;
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reg \in.a ;
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reg \out.d.d[14].d[0] ;
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reg \out.d.d[4].d[0] ;
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wire \in.d.d[8].d[1] ;
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reg \out.d.d[13].d[1] ;
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reg \out.d.d[8].d[1] ;
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reg \out.d.d[14].d[1] ;
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wire \in.d.d[2].d[1] ;
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reg \out.d.d[6].d[0] ;
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wire \in.d.d[4].d[0] ;
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reg \out.d.d[1].d[1] ;
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reg \_en_X_t[0] ;
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wire \in.d.d[0].d[1] ;
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// --- instances
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_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
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_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf (.y(\in.v ), .a(_in_v));
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_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv (.y(_out_a_B), .a(\out.a ));
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_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
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_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ));
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_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf (.y(_reset_BX), .a(reset_B));
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_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
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endmodule
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//
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// Verilog module for: buffer_15<>
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//
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module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
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input \in.d.d[0].d[0] ;
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input \in.d.d[0].d[1] ;
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input \in.d.d[1].d[0] ;
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input \in.d.d[1].d[1] ;
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input \in.d.d[2].d[0] ;
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input \in.d.d[2].d[1] ;
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input \in.d.d[3].d[0] ;
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input \in.d.d[3].d[1] ;
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input \in.d.d[4].d[0] ;
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input \in.d.d[4].d[1] ;
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input \in.d.d[5].d[0] ;
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input \in.d.d[5].d[1] ;
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input \in.d.d[6].d[0] ;
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input \in.d.d[6].d[1] ;
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input \in.d.d[7].d[0] ;
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input \in.d.d[7].d[1] ;
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input \in.d.d[8].d[0] ;
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input \in.d.d[8].d[1] ;
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input \in.d.d[9].d[0] ;
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input \in.d.d[9].d[1] ;
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input \in.d.d[10].d[0] ;
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input \in.d.d[10].d[1] ;
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input \in.d.d[11].d[0] ;
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input \in.d.d[11].d[1] ;
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input \in.d.d[12].d[0] ;
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input \in.d.d[12].d[1] ;
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input \in.d.d[13].d[0] ;
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input \in.d.d[13].d[1] ;
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input \in.d.d[14].d[0] ;
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input \in.d.d[14].d[1] ;
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output \in.a ;
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output \in.v ;
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output \out.d.d[0].d[0] ;
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output \out.d.d[0].d[1] ;
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output \out.d.d[1].d[0] ;
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output \out.d.d[1].d[1] ;
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output \out.d.d[2].d[0] ;
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output \out.d.d[2].d[1] ;
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output \out.d.d[3].d[0] ;
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output \out.d.d[3].d[1] ;
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output \out.d.d[4].d[0] ;
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output \out.d.d[4].d[1] ;
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output \out.d.d[5].d[0] ;
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output \out.d.d[5].d[1] ;
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output \out.d.d[6].d[0] ;
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output \out.d.d[6].d[1] ;
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output \out.d.d[7].d[0] ;
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output \out.d.d[7].d[1] ;
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output \out.d.d[8].d[0] ;
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output \out.d.d[8].d[1] ;
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output \out.d.d[9].d[0] ;
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output \out.d.d[9].d[1] ;
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output \out.d.d[10].d[0] ;
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output \out.d.d[10].d[1] ;
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output \out.d.d[11].d[0] ;
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output \out.d.d[11].d[1] ;
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output \out.d.d[12].d[0] ;
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output \out.d.d[12].d[1] ;
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output \out.d.d[13].d[0] ;
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output \out.d.d[13].d[1] ;
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output \out.d.d[14].d[0] ;
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output \out.d.d[14].d[1] ;
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input \out.a ;
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input \out.v ;
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// -- signals ---
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reg \out.d.d[2].d[1] ;
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wire \in.d.d[10].d[0] ;
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reg \out.d.d[1].d[0] ;
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wire \in.d.d[10].d[1] ;
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wire \in.d.d[4].d[0] ;
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reg \out.d.d[10].d[1] ;
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wire \in.d.d[13].d[0] ;
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reg \out.d.d[13].d[0] ;
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reg \out.d.d[9].d[1] ;
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wire \in.d.d[2].d[1] ;
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reg \out.d.d[2].d[0] ;
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reg \out.d.d[0].d[0] ;
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reg \out.d.d[14].d[0] ;
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reg \out.d.d[5].d[0] ;
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reg \in.a ;
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reg _reset_B;
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wire \out.v ;
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wire \out.a ;
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reg \out.d.d[4].d[0] ;
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wire \in.d.d[9].d[1] ;
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wire \in.d.d[3].d[0] ;
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wire \in.d.d[11].d[0] ;
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wire \in.d.d[2].d[0] ;
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reg \out.d.d[6].d[0] ;
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reg \out.d.d[13].d[1] ;
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reg \out.d.d[10].d[0] ;
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reg \out.d.d[7].d[1] ;
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wire \in.d.d[12].d[1] ;
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wire \in.d.d[6].d[1] ;
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reg \out.d.d[7].d[0] ;
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reg \out.d.d[3].d[0] ;
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wire \in.d.d[1].d[0] ;
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reg \out.d.d[14].d[1] ;
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reg \out.d.d[8].d[0] ;
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wire \in.d.d[13].d[1] ;
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wire \in.d.d[7].d[0] ;
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reg \out.d.d[12].d[0] ;
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wire \in.d.d[8].d[1] ;
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reg \out.d.d[4].d[1] ;
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wire \in.d.d[14].d[0] ;
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wire \in.d.d[5].d[1] ;
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wire \in.d.d[1].d[1] ;
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wire \in.d.d[9].d[0] ;
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wire \in.d.d[14].d[1] ;
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reg \out.d.d[11].d[0] ;
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reg \out.d.d[6].d[1] ;
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wire \in.d.d[12].d[0] ;
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wire \in.d.d[7].d[1] ;
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reg \out.d.d[0].d[1] ;
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wire \in.d.d[11].d[1] ;
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wire \in.d.d[8].d[0] ;
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wire \in.d.d[5].d[0] ;
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reg \out.d.d[1].d[1] ;
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reg \in.v ;
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wire \in.d.d[0].d[1] ;
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wire \in.d.d[0].d[0] ;
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reg \out.d.d[5].d[1] ;
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reg \out.d.d[8].d[1] ;
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reg \out.d.d[3].d[1] ;
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wire \in.d.d[6].d[0] ;
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reg \out.d.d[11].d[1] ;
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wire \in.d.d[3].d[1] ;
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reg \out.d.d[12].d[1] ;
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wire \in.d.d[4].d[1] ;
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reg \out.d.d[9].d[0] ;
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// --- instances
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_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
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endmodule
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