17 lines
427 B
Verilog
17 lines
427 B
Verilog
module tmpl_0_0dataflow__neuro_0_0delay__chain_33_4(out, in, vdd, vss);
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input vdd;
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input vss;
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output out;
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input in;
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// -- signals ---
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wire Idly1_a ;
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wire out ;
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wire Idly2_a ;
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wire in;
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// --- instances
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DLY4_X1 Idly0 (.y(Idly1_a ), .a(in), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly1 (.y(Idly2_a ), .a(Idly1_a ), .vdd(vdd), .vss(vss));
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DLY4_X1 Idly2 (.y(out), .a(Idly2_a ), .vdd(vdd), .vss(vss));
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endmodule |