35 lines
1.1 KiB
Verilog
35 lines
1.1 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0vtree_34_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , out, vdd, vss);
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input vdd;
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input vss;
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input Iin_d0_d0 ;
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input Iin_d0_d1 ;
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input Iin_d1_d0 ;
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input Iin_d1_d1 ;
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input Iin_d2_d0 ;
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input Iin_d2_d1 ;
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input Iin_d3_d0 ;
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input Iin_d3_d1 ;
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output out;
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// -- signals ---
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wire Iin_d2_d0 ;
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wire Iin_d0_d0 ;
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wire out ;
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wire Iin_d1_d1 ;
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wire Iin_d3_d1 ;
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wire Ict_in0 ;
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wire Iin_d1_d0 ;
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wire Ict_in2 ;
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wire Iin_d3_d0 ;
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wire Ict_in1 ;
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wire Iin_d0_d1 ;
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wire Iin_d2_d1 ;
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wire Ict_in3 ;
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// --- instances
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tmpl_0_0dataflow__neuro_0_0ctree_34_4 Ict (.Iin0 (Ict_in0 ), .Iin1 (Ict_in1 ), .Iin2 (Ict_in2 ), .Iin3 (Ict_in3 ), .out(out), .vdd(vdd), .vss(vss));
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OR2_X1 IOR2_tf0 (.y(Ict_in0 ), .a(Iin_d0_d1 ), .b(Iin_d0_d0 ), .vdd(vdd), .vss(vss));
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OR2_X1 IOR2_tf1 (.y(Ict_in1 ), .a(Iin_d1_d1 ), .b(Iin_d1_d0 ), .vdd(vdd), .vss(vss));
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OR2_X1 IOR2_tf2 (.y(Ict_in2 ), .a(Iin_d2_d1 ), .b(Iin_d2_d0 ), .vdd(vdd), .vss(vss));
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OR2_X1 IOR2_tf3 (.y(Ict_in3 ), .a(Iin_d3_d1 ), .b(Iin_d3_d0 ), .vdd(vdd), .vss(vss));
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endmodule |