117 lines
4.0 KiB
Plaintext
117 lines
4.0 KiB
Plaintext
/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/cell_lib_async.act";
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import "../../dataflow_neuro/cell_lib_std.act";
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import "../../dataflow_neuro/treegates.act";
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import "../../dataflow_neuro/primitives.act";
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// import tmpl::dataflow_neuro;
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// import tmpl::dataflow_neuro;
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import std::channel;
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open std::channel;
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namespace tmpl {
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namespace dataflow_neuro {
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/**
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* 2D decoder which uses a configurable delay from the VCtrees to buffer ack.
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* Nx is the x size of the decoder array
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* NxC is the number of wires in the x channel.
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* Thus NxC should be something like NxC = ceil(log2(Nx))
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* but my guess is that we can't do logs...
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* N_dly_cfg is the number of config bits in the ACK delay line,
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* with all bits high corresponding to 2**N_dly_cfg -1 DLY1_X4 cells.
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*/
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export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
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defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny],
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dly_cfg[N_dly_cfg], reset_B; power supply) {
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// Buffer to recieve concat(x,y) address packet
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buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
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// NEED TO BUFFER OUTPUTS FROM BUFFER I RECKON
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// Validity trees
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vtree<NxC> vtree_x (.supply = supply);
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vtree<NyC> vtree_y (.supply = supply);
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(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
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(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
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(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
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(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
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// Delay ack line. Ack line is delayed (but not the val)
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A_2C_B_X1 C2el(.c1 = vtree_x.out, .c2 = vtree_y.out, .vdd = supply.vdd, .vss = supply.vss);
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addr_buf.out.v = C2el.y;
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// delayprog<N_dly_cfg> dly(.in = tielow.y, .s = dly_cfg, .supply = supply);
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delayprog<N_dly_cfg> dly(.in = C2el.y, .s = dly_cfg, .supply = supply);
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// ACK MAY HAVE BEEN DISCONNECTED HERE
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// FOR TESTING PURPOSES
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// !!!!!!!!!!!!!!!!
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dly.out = addr_buf.out.a;
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// ACK MAY HAVE BEEN DISCONNECTED HERE
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// FOR TESTING PURPOSES
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// !!!!!!!!!!!!!!!!
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// AND trees
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pint bitval;
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andtree<NxC> atree_x[Nx];
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(k:0..Nx-1:atree_x[k].supply = supply;)
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(i:0..Nx-1:
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(j:0..NxC-1:
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bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
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[bitval = 1 ->
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atree_x[i].in[j] = addr_buf.out.d.d[j].t;
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[]bitval = 0 ->
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atree_x[i].in[j] = addr_buf.out.d.d[j].f;
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[]bitval >= 2 -> {false : "fuck"};
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]
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atree_x[i].out = outx[i];
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)
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)
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andtree<NyC> atree_y[Ny];
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(k:0..Ny-1:atree_y[k].supply = supply;)
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(i:0..Ny-1:
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(j:0..NyC-1:
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bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
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[bitval = 1 ->
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atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].t;
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[]bitval = 0 ->
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atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].f;
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]
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atree_y[i].out = outy[i];
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)
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)
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}
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}
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} |