actlib_dataflow_neuro/Fixing_Verilog.ipynb

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import re

with open('/home/p305119/libraries/xp018/actlib_dataflow_neuro/test/unit_tests/texel_small.v') as f:
    veri = f.read()
    
"remove all std/acell modules"

    
mod = re.findall(r'(?<=\n)module [^A-Z(]*[A-Z][A-Z0-9_]*\([\s\S]*?endmodule', veri)

for i in mod: 
    
    veri = veri.replace(i, "")
    

std = re.findall(r'((\S*)(TBUF\d*|INV|N?AND\d|N?OR\d|TIELO|TIEHI|MUX\d|OAI\d*|AOI\d*|(?<!T)BUF\d*|DLY\d*|KEEP\d*)(__X\d))', veri)

"""replace all stdcell names"""

for j in list(set(std)):
        veri = veri.replace(j[0], j[2] + j[3][1:])
        
        
keep = re.findall(r'((\S*)(KEEP\d*)())', veri)

"""Replace all KEEPs"""

for j in list(set(keep)):
        veri = veri.replace(j[0], j[2] + j[3][1:])
        
        
acell = re.findall(r'(\S*)(A_[1234CPNRSUB_]{2,12}(_X\d)?\b(?=[^<>]))', veri)

for j in list(set(acell)):
    veri = veri.replace(j[0] + j[1], j[1].replace('__', '_'))
    
    
arb = re.findall(r'(\S*)(ARBITER)', veri)

for j in list(set(arb)):
    veri = veri.replace(j[0] + j[1], 'ARBITER')
    
   
pullu = re.findall(r'(\S*)(PULLUP__X4)', veri)

for j in list(set(pullu)):
    veri = veri.replace(j[0] + j[1], 'PULLUP_X4')
    
    
pulld = re.findall(r'(\S*)(PULLDOWN__X4)', veri)

for j in list(set(pulld)):
    veri = veri.replace(j[0] + j[1], 'PULLDOWN_X4')
    
veri = veri.replace('));', '), .vdd(vdd), .vss(vss));')

vddvss = re.findall(r'(?<=\n)(module [\([\s\S]*?;)', veri)

for j in list(set(vddvss)):
    veri = veri.replace(j, j[:-2] + ", vdd, vss); \n   input vdd;\n   input vss;")
    
# veri = veri.replace('[', '')
veri = veri.replace('_0_0t', 't')

hierac = re.findall(r'(\\\S* )', veri)

for j in list(set(hierac)):
    temp = j.replace(']', '')
    temp = temp.replace('[', '')
    temp = temp.replace('.', '_')
    temp = temp.replace('\\', 'I')
    
    veri = veri.replace(j, temp)
    
    
with open('/home/p305119/libraries/xp018/actlib_dataflow_neuro/test/unit_tests/texel_small_clean.v', 'w') as w:
    w.write(veri)

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