Upload files to "SPI2Slave_T4"

SPI2Slave_T4/SPI2Slave_T4.h

@@ -0,0 +1,49 @@
+#if !defined(_SPI2Slave_T4_H_)
+#define _SPI2Slave_T4_H_
+
+#include <Arduino.h>
+#include <circular_buffer.h>
+#include <SPI.h>
+
+typedef enum SPI_BITS {
+  SPI_8_BITS = 8,
+  SPI_16_BITS = 16,
+  SPI_32_BITS = 32,
+} SPI_BITS;
+
+typedef void (*_SPI_ptr)();
+
+#define SPI2Slave_T4_CLASS template<SPIClass* port = nullptr, SPI_BITS bits = SPI_8_BITS>
+#define SPI2Slave_T4_FUNC template<SPIClass* port, SPI_BITS bits>
+#define SPI2Slave_T4_OPT SPI2Slave_T4<port, bits>
+
+extern SPIClass SPI;
+
+class SPI2Slave_T4_Base {
+  public:
+    virtual void SLAVE_ISR();
+};
+
+static SPI2Slave_T4_Base* _LPSPI1 = nullptr;
+
+SPI2Slave_T4_CLASS class SPI2Slave_T4 : public SPI2Slave_T4_Base {
+  public:
+    SPI2Slave_T4();
+    void begin();
+    uint32_t transmitErrors();
+    void onReceive(_SPI_ptr handler) { _spihandler = handler; }
+    bool active();
+    bool available();
+    void pushr(uint32_t data);
+    uint32_t popr();
+
+  private:
+    _SPI_ptr _spihandler = nullptr;
+    void SLAVE_ISR();
+    int _portnum = 0;
+    uint32_t nvic_irq = 0;
+    uint32_t transmit_errors = 0;
+};
+
+#include "SPI2Slave_T4.tpp"
+#endif

SPI2Slave_T4/SPI2Slave_T4.tpp

@@ -0,0 +1,123 @@
+#define SLAVE_CR     spiAddr[4]   // Control Register			LPSPIx_CR	Control register (reset/enable)
+#define SLAVE_FCR    spiAddr[22]  // FIFO Control Register		FIFO Control
+#define SLAVE_IER    spiAddr[6]   // Interrupt Enable Register	Interrupt Enable
+#define SLAVE_CFGR0  spiAddr[8]   // Config Register 0			Config 0 (master/slave, PCS)
+#define SLAVE_CFGR1  spiAddr[9]   // Config Register 1			Config 1 (enable bits, masks)
+#define SLAVE_TDR    spiAddr[25]  // Transmit Data Register		Transmit Data
+#define SLAVE_RDR    spiAddr[29]  // Receive Data Register		Receive Data
+#define SLAVE_SR     spiAddr[5]   // Status Register			Status register (TX, RX flags)
+#define SLAVE_TCR_REFRESH spiAddr[24] = (0UL << 27) | LPSPI_TCR_FRAMESZ(bits - 1) // Transmit Command Register
+
+#define SLAVE_PORT_ADDR volatile uint32_t *spiAddr = &(*(volatile uint32_t*)(0x40394000 + (0x4000 * _portnum)))
+
+#define SLAVE_PINS_ADDR volatile uint32_t *spiAddr = &(*(volatile uint32_t*)(0x401F84EC + (_portnum * 0x10)))
+
+void lpspi1_slave_isr() {
+  _LPSPI1->SLAVE_ISR();
+}
+
+
+SPI2Slave_T4_FUNC SPI2Slave_T4_OPT::SPI2Slave_T4() {
+  if ( port == &SPI2 ) {
+	  
+	_LPSPI1 = this;
+    _portnum = 0;
+    
+   CCM_CCGR1 |= (3UL << 0);
+    nvic_irq = 32 + _portnum;
+    _VectorsRam[16 + nvic_irq] = lpspi1_slave_isr;
+
+    /* Alternate pins not broken out on Teensy 4.0/4.1 for LPSPI1 */
+    SLAVE_PINS_ADDR;
+    spiAddr[0] = 0; /* PCS0_SELECT_INPUT */
+    spiAddr[1] = 0; /* SCK_SELECT_INPUT */
+    spiAddr[2] = 0; /* SDI_SELECT_INPUT */
+    spiAddr[3] = 0; /* SDO_SELECT_INPUT */
+    
+    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 0x4; /* ALT4 pin 43  SPI2  LPSPI1 SDO  (MOSI) */
+    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 0x4; /* ALT4 pin 42  SPI2  LPSPI1 SDI  (MISO) */
+    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 0x4; /* ALT4 pin 45  SPI2  LPSPI1 SCK  (CLK) */
+    IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 0x4; /* ALT4 pin 44  SPI2  LPSPI1 PCS0 (CS) */
+  } 
+}
+
+
+SPI2Slave_T4_FUNC bool SPI2Slave_T4_OPT::active() {
+  SLAVE_PORT_ADDR;
+  return ( !(SLAVE_SR & (1UL << 9)) ) ? 1 : 0;
+}
+
+
+SPI2Slave_T4_FUNC bool SPI2Slave_T4_OPT::available() {
+  SLAVE_PORT_ADDR;
+  return ( (SLAVE_SR & (1UL << 8)) ) ? 1 : 0;
+}
+
+
+SPI2Slave_T4_FUNC void SPI2Slave_T4_OPT::pushr(uint32_t data) {
+  SLAVE_PORT_ADDR;
+  SLAVE_TDR = data;
+}
+
+
+SPI2Slave_T4_FUNC uint32_t SPI2Slave_T4_OPT::popr() {
+  SLAVE_PORT_ADDR;
+  uint32_t data = SLAVE_RDR;
+  SLAVE_SR = (1UL << 8); /* Clear WCF */
+  return data;
+}
+
+extern uint8_t spiRx[256];
+extern volatile int spiRxIdx;
+
+SPI2Slave_T4_FUNC void __attribute__((section(".fustrun"))) SPI2Slave_T4_OPT::SLAVE_ISR() {
+
+  SLAVE_PORT_ADDR;
+
+#if 0
+  if ( _spihandler ) {
+    _spihandler();
+    SLAVE_SR = 0x3F00;
+    asm volatile ("dsb");
+    return;
+  }
+#endif
+
+  if ( SLAVE_SR & (1UL << 11) ) {
+    /* transmit error, clear flag, check cabling */
+    SLAVE_SR = (1UL << 11);
+    transmit_errors++;
+  }
+  if ( (SLAVE_SR & (1UL << 1)) ) {
+    spiRx[spiRxIdx] = SLAVE_RDR;
+    if (spiRxIdx < 255) spiRxIdx++;
+    SLAVE_SR = (1UL << 1);
+  }
+
+  if ( (SLAVE_SR & (1UL << 0)) ) {
+    SLAVE_TDR = 0x34;
+  }
+
+   if ( (SLAVE_SR & (1UL << 9)) ) {
+    spiRxComplete = 1;
+  }
+
+  SLAVE_SR = 0x3F00;
+  asm volatile ("dsb");
+}
+
+SPI2Slave_T4_FUNC void SPI2Slave_T4_OPT::begin() {
+  SLAVE_PORT_ADDR;
+  SLAVE_CR = LPSPI_CR_RST; /* resets the SPI controller (clears all state) */
+  SLAVE_CR = 0; /* Disable Module to safely configure it*/
+  SLAVE_FCR = 0;    //x10001; /* 1x watermark for RX and TX */
+  SLAVE_IER = 0x01 | 0x200; /* Interrupt enable bits ---- Bit 0 (0x01): Receive Data Full interrupt ---- Bit 9 (0x200): Transmit Data Empty interrupt*/
+  SLAVE_CFGR0 = 0; /* These config register affect master/slave mode, clock polarity, chip select behavior, and more ---- 0 is valid for simple slave mode */
+  SLAVE_CFGR1 = 0; /* These config register affect master/slave mode, clock polarity, chip select behavior, and more ---- 0 is valid for simple slave mode */
+  SLAVE_CR |= LPSPI_CR_MEN | LPSPI_CR_DBGEN; /* Re-enable the SPI module (MEN = Module Enable) ---- Allow SPI to work in debug mode (when stepping through code)*/
+  SLAVE_SR = 0x3F00; /* Clear status register */
+  SLAVE_TCR_REFRESH; /* Sets the Transfer Control Register */
+  SLAVE_TDR = 0x0; /* dummy data, must populate initial TX slot */
+  NVIC_ENABLE_IRQ(nvic_irq);  /* Enables the interrupt for the selected SPI peripheral */
+  NVIC_SET_PRIORITY(nvic_irq, 1); /* Sets priority so it can respond in time */
+}