132 lines
4.7 KiB
C++
132 lines
4.7 KiB
C++
#define SLAVE_CR spiAddr[4] // Control Register LPSPIx_CR Control register (reset/enable)
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#define SLAVE_FCR spiAddr[22] // FIFO Control Register FIFO Control
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#define SLAVE_IER spiAddr[6] // Interrupt Enable Register Interrupt Enable
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#define SLAVE_CFGR0 spiAddr[8] // Config Register 0 Config 0 (master/slave, PCS)
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#define SLAVE_CFGR1 spiAddr[9] // Config Register 1 Config 1 (enable bits, masks)
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#define SLAVE_TDR spiAddr[25] // Transmit Data Register Transmit Data
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#define SLAVE_RDR spiAddr[29] // Receive Data Register Receive Data
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#define SLAVE_SR spiAddr[5] // Status Register Status register (TX, RX flags)
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#define SLAVE_TCR_REFRESH spiAddr[24] = (0UL << 27) | LPSPI_TCR_FRAMESZ(bits - 1) // Transmit Command Register
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#define SLAVE_PORT_ADDR volatile uint32_t *spiAddr = &(*(volatile uint32_t*)(0x40394000 + (0x4000 * _portnum)))
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#define SLAVE_PINS_ADDR volatile uint32_t *spiAddr = &(*(volatile uint32_t*)(0x401F84EC + (_portnum * 0x10)))
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void lpspi1_slave_isr() {
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_LPSPI1->SLAVE_ISR();
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}
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SPI2Slave_T4_FUNC SPI2Slave_T4_OPT::SPI2Slave_T4() {
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if ( port == &SPI2 ) {
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_LPSPI1 = this;
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_portnum = 0;
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CCM_CCGR1 |= (3UL << 0);
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nvic_irq = 32 + _portnum;
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_VectorsRam[16 + nvic_irq] = lpspi1_slave_isr;
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/* Alternate pins not broken out on Teensy 4.0/4.1 for LPSPI1 */
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SLAVE_PINS_ADDR;
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spiAddr[0] = 0; /* PCS0_SELECT_INPUT */
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spiAddr[1] = 0; /* SCK_SELECT_INPUT */
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spiAddr[2] = 0; /* SDI_SELECT_INPUT */
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spiAddr[3] = 0; /* SDO_SELECT_INPUT */
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IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 0x4; /* ALT4 pin 43 SPI2 LPSPI1 SDO (MOSI) */
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IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 0x4; /* ALT4 pin 42 SPI2 LPSPI1 SDI (MISO) */
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IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 0x4; /* ALT4 pin 45 SPI2 LPSPI1 SCK (CLK) */
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IOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 0x4; /* ALT4 pin 44 SPI2 LPSPI1 PCS0 (CS) */
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}
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}
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SPI2Slave_T4_FUNC void SPI2Slave_T4_OPT::swapPins(bool enable) {
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SLAVE_PORT_ADDR;
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SLAVE_CR &= ~LPSPI_CR_MEN; /* Disable Module */
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SLAVE_CFGR1 = (SLAVE_CFGR1 & 0xFCFFFFFF) | (enable) ? (3UL << 24) : (0UL << 24);
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SLAVE_CR |= LPSPI_CR_MEN; /* Enable Module */
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}
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SPI2Slave_T4_FUNC bool SPI2Slave_T4_OPT::active() {
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SLAVE_PORT_ADDR;
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return ( !(SLAVE_SR & (1UL << 9)) ) ? 1 : 0;
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}
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SPI2Slave_T4_FUNC bool SPI2Slave_T4_OPT::available() {
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SLAVE_PORT_ADDR;
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return ( (SLAVE_SR & (1UL << 8)) ) ? 1 : 0;
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}
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SPI2Slave_T4_FUNC void SPI2Slave_T4_OPT::pushr(uint32_t data) {
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SLAVE_PORT_ADDR;
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SLAVE_TDR = data;
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}
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SPI2Slave_T4_FUNC uint32_t SPI2Slave_T4_OPT::popr() {
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SLAVE_PORT_ADDR;
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uint32_t data = SLAVE_RDR;
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SLAVE_SR = (1UL << 8); /* Clear WCF */
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return data;
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}
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extern uint8_t spiRx[256];
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extern volatile int spiRxIdx;
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SPI2Slave_T4_FUNC void __attribute__((section(".fustrun"))) SPI2Slave_T4_OPT::SLAVE_ISR() {
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SLAVE_PORT_ADDR;
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#if 0
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if ( _spihandler ) {
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_spihandler();
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SLAVE_SR = 0x3F00;
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asm volatile ("dsb");
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return;
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}
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#endif
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if ( SLAVE_SR & (1UL << 11) ) {
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/* transmit error, clear flag, check cabling */
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SLAVE_SR = (1UL << 11);
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transmit_errors++;
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}
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if ( (SLAVE_SR & (1UL << 1)) ) {
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spiRx[spiRxIdx] = SLAVE_RDR;
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if (spiRxIdx < 256) spiRxIdx++;
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SLAVE_SR = (1UL << 1);
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}
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if ( (SLAVE_SR & (1UL << 0)) ) {
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SLAVE_TDR = 0x34;
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}
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if ( (SLAVE_SR & (1UL << 9)) ) {
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spiRxComplete = 1;
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}
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SLAVE_SR = 0x3F00;
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asm volatile ("dsb");
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}
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SPI2Slave_T4_FUNC void SPI2Slave_T4_OPT::begin() {
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SLAVE_PORT_ADDR;
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SLAVE_CR = LPSPI_CR_RST; /* resets the SPI controller (clears all state) */
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SLAVE_CR = 0; /* Disable Module to safely configure it*/
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SLAVE_FCR = 0; //x10001; /* 1x watermark for RX and TX */
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SLAVE_IER = 0x01 | 0x200; /* Interrupt enable bits ---- Bit 0 (0x01): Receive Data Full interrupt ---- Bit 9 (0x200): Transmit Data Empty interrupt*/
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SLAVE_CFGR0 = 0; /* These config register affect master/slave mode, clock polarity, chip select behavior, and more ---- 0 is valid for simple slave mode */
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SLAVE_CFGR1 = 0; /* These config register affect master/slave mode, clock polarity, chip select behavior, and more ---- 0 is valid for simple slave mode */
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SLAVE_CR |= LPSPI_CR_MEN | LPSPI_CR_DBGEN; /* Re-enable the SPI module (MEN = Module Enable) ---- Allow SPI to work in debug mode (when stepping through code)*/
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SLAVE_SR = 0x3F00; /* Clear status register */
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SLAVE_TCR_REFRESH; /* Sets the Transfer Control Register */
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SLAVE_TDR = 0x0; /* dummy data, must populate initial TX slot */
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NVIC_ENABLE_IRQ(nvic_irq); /* Enables the interrupt for the selected SPI peripheral */
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NVIC_SET_PRIORITY(nvic_irq, 1); /* Sets priority so it can respond in time */
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}
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