added initial version of actsim support
This commit is contained in:
parent
952cf050c8
commit
3f8293e16a
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@ -40,3 +40,6 @@ ASSURA/
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ncvlog.log
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ConnectedPinsLog.txt
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UnconnectedPinsLog.txt
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*.os
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*.csv
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*.so
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@ -0,0 +1,34 @@
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#-------------------------------------------------------------------------
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#
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# Copyright (c) 2018 Rajit Manohar
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; either version 2
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# of the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor,
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# Boston, MA 02110-1301, USA.
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#
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#-------------------------------------------------------------------------
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TARGETLIBS=actsim_test_bench_lib.so
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TARGETCONF=actsim_test_bench_lib.conf
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SHOBJS=test_bench_lib.os
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SRCS= $(SHOBJS:.os=.c)
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include $(ACT_HOME)/scripts/Makefile.std
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$(TARGETLIBS): $(SHOBJS)
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$(ACT_HOME)/scripts/linkso $(TARGETLIBS) $(SHOBJS)
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@ -0,0 +1,19 @@
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begin sim
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begin extern
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string_tablex libs "test_bench_lib"
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begin test_bench_lib
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string path "$ACT_HOME/lib/actsim_test_bench_lib.so"
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string sim::testbench::fsource_init "source_init"
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string sim::testbench::fsource_next "source_next"
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string sim::testbench::fsource_get "source_get"
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string sim::testbench::fcheck_out_of_order "check_out_of_order"
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string sim::testbench::fcheck_in_order "check_in_order"
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string sim::testbench::fcheck_next "check_next"
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string sim::testbench::fdump_to_file "dump_to_file"
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string sim::testbench::fcontrol_next "control_next"
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string sim::testbench::fcontrol_next "control_get"
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string sim::testbench::fcontrol_next "control_wait"
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end
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end
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end
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@ -0,0 +1,127 @@
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/*************************************************************************
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*
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*
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* Copyright 2022 Ole Richter - University of Groningen
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* Copyright 2022 Michele Mastella - University of Groningen
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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**************************************************************************
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*/
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namespace sim::testbench {
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function fsource_init(int verbose) : int;
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function fsource_next(int id; int sim_step) : int;
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function fsource_get(int id; int bit_width) : int;
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function fcheck_next(int id; int sim_step) : int;
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function fcheck_in_order(int id; int data) : int;
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function fcheck_out_of_order(int id; int data) : int;
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function fdump_to_file(int id; int sim_step; int data) : int;
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template<pint BIT_WIDTH;pint ID>
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defproc channel_source(chan!(int<BIT_WIDTH>) out; chan?(int) sim_step; chan!(int) done)
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{
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int current_step, t,data;
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chp {
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*[ sim_step?current_step; t := 1;
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*[ t = 1 -> t := fchannel_source_next(ID,current_step);
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[ t = 1 -> data := fchannel_source_get(ID,BIT_WIDTH); out!data ; log("send ", data, " on source ", ID)
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[] else -> done!1
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]
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]
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]
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}
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}
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template<pint BIT_WIDTH;pint ID>
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defproc channel_checker_in_order(chan?(int<BIT_WIDTH>) in; chan?(int) sim_step; chan!(int) done)
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{
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int current_step, t, check, data;
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chp {
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*[ sim_step?current_step; t := 1;
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*[ t = 1 -> t := fcheck_next(ID,current_step);
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[ t = 1 -> in?data; check := fcheck_in_order(ID,data);
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[check = 1 -> log("[success] got ",data, " on check ", ID)
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[] else -> log("[failure] got wrong ",data, " on check ", ID, " see log")
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]
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[] else -> done!1
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]
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]
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]
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}
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}
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template<pint BIT_WIDTH;pint ID>
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defproc channel_checker_out_of_order(chan?(int<BIT_WIDTH>) in; chan?(int) sim_step; chan!(int<1>) done)
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{
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int current_step, t, check, data;
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chp {
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*[ sim_step?current_step; t := 1;
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*[ t = 1 -> t := fcheck_next(ID,current_step);
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[ t = 1 -> in?data; check := fcheck_out_of_order(ID,data);
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[check = 1 -> log("[success] got ",data, " on check ", ID)
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[] else -> log("[failure] got wrong ",data, " on check ", ID, " see log")
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]
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[] else -> done!1
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]
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]
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]
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}
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}
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template<pint BIT_WIDTH;pint ID>
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defproc channel_dump(chan?(int<BIT_WIDTH>) in; chan?(int) sim_step)
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{
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int current_step, t;
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chp {
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*[ [ #sim_step -> sim_step?current_step
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| #in -> t:=fdump_to_file(ID,current_step,in)
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]
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]
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}
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}
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template<pint NUMBER_SOURCE,NUMBER_CHECKER,NUMBER_DUMP;pbool HALT_ON_FALIURE>
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defproc control(chan(int) sim_step_source[NUMBER_SOURCE]; chan(int) sim_step_checker[NUMBER_CHECKER]; chan(int) sim_step_dump[NUMBER_DUMP]; chan?(int<1>) done_source[NUMBER_SOURCE]; chan?(int<1>) done_checker[NUMBER_CHECKER])
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{
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int current_step, wait;
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int<1> t, success, failure_free;
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chp {
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t:=1;
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failure_free:=1;
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*[ t = 1 -> current_step := fcontrol_get();
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[ current_step = 0 -> skip; // reset here
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[] else ->
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(,:j:1..NUMBER_SOURCE: sim_step_source[j]!current_step),
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(,:j:1..NUMBER_CHECKER: sim_step_checker[j]!current_step),
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(,:j:1..NUMBER_DUMP: sim_step_dump[j]!current_step);
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(:j:1..NUMBER_SOURCE: done_source[j]?success; failure_free := failure_free & success);
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(:j:1..NUMBER_CHECKER: done_checker[j]?success; failure_free := failure_free & success);
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];
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wait := fcontrol_wait();
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[ wait > 0 -> skip // exec cycle
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[] else -> skip
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];
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[ HALT_ON_FALIURE & ~failure_free -> t := 0; log("stopped testbech because of failure")
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[] else -> t:=fcontrol_next()
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]
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]
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}
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}
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}
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@ -0,0 +1,466 @@
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/*************************************************************************
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*
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*
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* Copyright 2022 Ole Richter - University of Groningen
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* Copyright 2022 Michele Mastella - University of Groningen
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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**************************************************************************
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*/
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/**
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* this file contains all the helper fucntions to read the CSV test benches.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <act/actsim_ext.h>
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/**
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* the arrays are staticly allocated, like how many sources aor checks there are, they can be easily increased and recompiled
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* the defaults are thought to be fine for most smaller test benches
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* also the standard file naming and that the csv is using a ; as seperator can be changed
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*/
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#define MAX_SOURCES 100
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#define MAX_CHECKERS 100
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#define MAX_CHECKS 100000
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#define MAX_DUMP 100
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#define CSV_FORMAT "%u; %lu"
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#define CSV_WRITE_FORMAT "%d; %d\n"
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#define SOURCE_FILENAME "source_%d.csv"
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#define CHECK_FILENAME "check_%d.csv"
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#define DUMP_FILENAME "dump_%d.csv"
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#define CONTROL_FILENAME "control.csv"
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#define LOG_FILENAME "test_bench_helper.log"
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/**
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* as the testbench is calling the functions, all state variables need to be static so they are the same state whenever called
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*
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*/
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// all opened files for the text bench
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static FILE *source_file[MAX_SOURCES];
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static FILE *check_file[MAX_CHECKERS];
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static FILE *dump_file[MAX_DUMP];
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static FILE *control_file;
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// the data variable buffers, as we can only deliver one variable at a time,
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// so first is there a variable and than the varibale itself
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static unsigned int source_sim_step[MAX_SOURCES];
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static unsigned int check_sim_step[MAX_CHECKERS];
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static unsigned long source_data_buffer[MAX_SOURCES];
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static unsigned long check_data_buffer[MAX_CHECKERS][MAX_CHECKS];
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static unsigned short check_data_used[MAX_CHECKERS][MAX_CHECKS];
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static unsigned int check_data_number[MAX_CHECKERS];
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// as printing does not get dispayed in actsim, print to logfile
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static FILE *logfile = NULL;
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// show more info like words/tests read
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static int verbose = 0;
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// keep a memory at which simulation step we are in the files
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static unsigned long last_sim_step = 0;
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static unsigned int first_sim_step = 0;
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static unsigned long current_sim_step = 0;
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static unsigned long current_sim_wait = 1;
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static unsigned int check_errors = 0;
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/**
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* Init opens all the files and reads the control
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* it requires one int:
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* verbose: 0 for normal pinting, 1 for verbose printing
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* it returns true on success
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*/
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struct expr_res init (int num, struct expr_res *args)
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{
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struct expr_res t;
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t.v = 0;
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t.width = 1;
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check_errors = 0;
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logfile = fopen(LOG_FILENAME, "w");
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if (num !=1 ){
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fprintf(logfile,"[ERROR] wrong number of arguments in init"); fflush(logfile);
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return t;
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}
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verbose = args[0].v;
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fprintf(logfile,"==== initialising control ====\n"); fflush(logfile);
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control_file = fopen (CONTROL_FILENAME, "r");
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int success = 0;
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success = fscanf(control_file, CSV_FORMAT, &first_sim_step, &last_sim_step);
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if (success != 2) {
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if(ferror(source_file[args[0].v])){
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fprintf(logfile,"read error on control\n"); fflush(logfile);
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return t;
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}
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else {
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fprintf(logfile,"empty file for control\n"); fflush(logfile);
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return t;
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}
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}
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fprintf(logfile,"==== initialising source ====\n"); fflush(logfile);
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int i = 0;
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for (i = 0; i<MAX_SOURCES; i++){
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source_sim_step[i] = 0;
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char filename[255];
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snprintf(filename, 255, SOURCE_FILENAME,i);
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source_file[i] = fopen (filename, "r");
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if (source_file[i]){
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fprintf(logfile, "source id %d -> %s\n",i,filename); fflush(logfile);
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}
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}
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fprintf(logfile,"==== initialising check ====\n"); fflush(logfile);
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for (i = 0; i<MAX_CHECKERS; i++){
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check_sim_step[i] = 0;
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char filename[255];
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snprintf(filename, 255, CHECK_FILENAME,i);
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check_file[i] = fopen (filename, "r");
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if (check_file[i]){
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fprintf(logfile, "check id %d -> %s\n",i,filename); fflush(logfile);
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}
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}
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fprintf(logfile,"==== initialising done ====\n"); fflush(logfile);
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t.v = 1;
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return t;
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}
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/**
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* check_next looks if there is an other check availible in that simulation step
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* if a new simulation step is loaded all checks from this step will be cashed into the arrays
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* it requires 2 int:
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* id: the id of the checker
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* simstep: the simulation step the next test to be loaded from
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* it returns 1 if there is a check availible, 0 if not or an error occured
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*/
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struct expr_res check_next (int num, struct expr_res *args){
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struct expr_res t;
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t.v = 0 ;
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t.width = 1;
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if (num !=2 ){
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fprintf(logfile,"[ERROR] wrong number of arguments in channel_check\n"); fflush(logfile);
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return t;
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}
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if (!check_file[args[0].v]) {
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fprintf(logfile,"[ERROR] could not read check %d, file not open or does not exist\n",args[0].v); fflush(logfile);
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return t;
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}
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int step_done = 0, i = 0;
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unsigned int check_sim_step_file = 0;
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unsigned long int sim_data_file = 0;
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// check if we need to advnce one step
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if (check_sim_step[args[0].v] != args[1].v){
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// print all missed steps
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for (i = 0; i < check_data_number[args[0].v]; i++){
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if (check_data_used[args[0].v][i] == 0) {
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check_errors++;
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fprintf(logfile,"[FAILURE] missed %d on check %d - %d for simstep %d; Error count: %d\n",check_data_buffer[args[0].v],args[0].v,i,check_sim_step[args[0].v],check_errors); fflush(logfile);
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}
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}
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// load next step
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rewind(check_file[args[0].v]);
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check_sim_step[args[0].v] = args[1].v;
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unsigned int count = 0;
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// read next steps
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while (!step_done){
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int success = 0;
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success = fscanf(check_file[args[0].v], CSV_FORMAT, &check_sim_step_file, &sim_data_file);
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if (success != 2) {
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if(ferror(check_file[args[0].v])) fprintf(logfile,"read error on check %d\n",args[0].v);
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if(verbose) fprintf(logfile,"EOF on check %d\n",args[0].v); fflush(logfile);
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step_done = 1;
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}
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else if (count >= MAX_CHECKS) {
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fprintf(logfile,"[ERROR] checks for sim step %d on checker %d, exceed the maximum number of checks, increase and recompile\n",args[0].v); fflush(logfile);
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}
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else if (check_sim_step_file == check_sim_step[args[0].v]){
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check_data_buffer[args[0].v][count] = sim_data_file;
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check_data_used[args[0].v][count] = 0;
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if(verbose) fprintf(logfile,"%d check %d on %d\n",count,check_data_buffer[args[0].v][count],args[0].v); fflush(logfile);
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count++;
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}
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}
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check_data_number[args[0].v] = count;
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}
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// check if any checks have not been used yet
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for (i = 0; i < check_data_number[args[0].v]; i++){
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if (check_data_used[args[0].v][i] == 0) {
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t.v = 1 ;
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i = check_data_number[args[0].v];
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break;
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}
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}
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return t;
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}
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/**
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* check_in_order compares a word to the next avaible word in the csv,
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* check_next has to be called before
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* it requres 2 ints:
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* id: the id of the checker
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* word to check: the word to compare
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* returns 1 on success and 0 on failure
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*/
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struct expr_res check_in_order (int num, struct expr_res *args)
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{
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struct expr_res t;
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t.v = 0 ;
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t.width = 0;
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if (num !=2 ){
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fprintf(logfile,"[ERROR] wrong number of arguments in channel_check\n");
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return t;
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}
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for (int i = 0; i < check_data_number[args[0].v]; i++){
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if (check_data_used[args[0].v][i] == 0) {
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if (check_data_buffer[args[0].v][i] == args[1].v){
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fprintf(logfile,"[SUCCESS] got %d = %d on check %d - %d\n",check_data_buffer[args[0].v],args[1].v,args[0].v,i); fflush(logfile);
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t.v = 1;
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}
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else {
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check_errors++
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fprintf(logfile,"[FAILURE] expected %d got %d on check %d - %d; Error count %d\n",check_data_buffer[args[0].v],args[1].v,args[0].v,i,check_errors); fflush(logfile);
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t.v = 0;
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||||
}
|
||||
check_data_used[args[0].v][i] = 1;
|
||||
i = check_data_number[args[0].v];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
t.width = 1;
|
||||
return t;
|
||||
}
|
||||
|
||||
/**
|
||||
* check_out_of_order compares a word to the all avaible word in the csv for that step,
|
||||
* each word can only be used once.
|
||||
* check_next has to be called before
|
||||
* it requres 2 ints:
|
||||
* id: the id of the checker
|
||||
* word to check: the word to compare
|
||||
* returns 1 on success and 0 on failure
|
||||
*/
|
||||
struct expr_res check_out_of_order (int num, struct expr_res *args)
|
||||
{
|
||||
struct expr_res t;
|
||||
t.v = 0 ;
|
||||
t.width = 0;
|
||||
if (num !=2 ){
|
||||
fprintf(logfile,"[ERROR] wrong number of arguments in channel_check\n");
|
||||
return t;
|
||||
}
|
||||
for (int i = 0; i < check_data_number[args[0].v]; i++){
|
||||
if (check_data_used[args[0].v][i] == 0) {
|
||||
if (check_data_buffer[args[0].v][i] == args[1].v){
|
||||
fprintf(logfile,"[SUCCESS] got %d = %d on check %d - %d\n",check_data_buffer[args[0].v],args[1].v,args[0].v,i); fflush(logfile);
|
||||
t.v = 1;
|
||||
check_data_used[args[0].v][i] = 1;
|
||||
i = check_data_number[args[0].v];
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (t.v == 0){
|
||||
check_errors++;
|
||||
fprintf(logfile,"[FAILURE] could not find %d on check %d; Error count: %d\n",check_data_buffer[args[0].v],args[1].v,args[0].v,check_errors); fflush(logfile);
|
||||
}s
|
||||
t.width = 1;
|
||||
return t;
|
||||
}
|
||||
|
||||
/**
|
||||
* source_next looks if there is an other word availible to be send in the current simulation step
|
||||
* it loads that work into the buffer.
|
||||
* if a new simulation step is loaded the file is read from the beginning again.
|
||||
* it requires 2 int:
|
||||
* id: the id of the source
|
||||
* simstep: the simulation step the next test to be loaded from
|
||||
* it returns 1 if there is a source word availible, 0 if not or an error occured
|
||||
*/
|
||||
struct expr_res source_next (int num, struct expr_res *args)
|
||||
{
|
||||
struct expr_res t;
|
||||
t.v = 0 ;
|
||||
t.width = 0;
|
||||
if (num !=2 ){
|
||||
fprintf(logfile,"[ERROR] wrong number of arguments in channel_source_next\n"); fflush(logfile);
|
||||
return t;
|
||||
}
|
||||
if (!source_file[args[0].v]) {
|
||||
fprintf(logfile,"[ERROR] could not read source %d, file not open or does not exist\n",args[0].v); fflush(logfile);
|
||||
return t;
|
||||
}
|
||||
int step_done = 0;
|
||||
unsigned int source_sim_step_file = 0;
|
||||
unsigned long int sim_data_file = 0;
|
||||
if (source_sim_step[args[0].v] != args[1].v){
|
||||
rewind(source_file[args[0].v]);
|
||||
source_sim_step[args[0].v] = args[1].v;
|
||||
}
|
||||
while (!step_done){
|
||||
int success = 0;
|
||||
success = fscanf(source_file[args[0].v], CSV_FORMAT, &source_sim_step_file, &sim_data_file);
|
||||
if (success != 2) {
|
||||
if(ferror(source_file[args[0].v])) fprintf(logfile,"read error on source %d\n",args[0].v);
|
||||
source_data_buffer[args[0].v] = 0;
|
||||
if(verbose) fprintf(logfile,"EOF on source %d\n",args[0].v); fflush(logfile);
|
||||
t.v = 0 ;
|
||||
t.width = 1;
|
||||
return t;
|
||||
}
|
||||
if (source_sim_step_file == source_sim_step[args[0].v]){
|
||||
step_done = 1;
|
||||
source_data_buffer[args[0].v]= sim_data_file;
|
||||
if(verbose) fprintf(logfile,"read %d on source %d\n",sim_data_file,args[0].v); fflush(logfile);
|
||||
t.v = 1;
|
||||
t.width = 1;
|
||||
return t;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* source get reads the buffer and returns the word that was placed by source_next
|
||||
* it requires 2 int:
|
||||
* id: the id of the source
|
||||
* width: the number of bits the source word is supposed to have
|
||||
* it returns the next word placed by source_next
|
||||
*/
|
||||
struct expr_res source_get (int num, struct expr_res *args)
|
||||
{
|
||||
struct expr_res t;
|
||||
t.v = 0 ;
|
||||
t.width = 0;
|
||||
if (num !=2 ){
|
||||
fprintf(logfile,"[ERROR] wrong number of arguments in channel_source_get\n");
|
||||
return t;
|
||||
}
|
||||
t.v = source_data_buffer[args[0].v];
|
||||
t.width = args[1].v;
|
||||
return t;
|
||||
}
|
||||
|
||||
/**
|
||||
* dump to file writes every inforamtion it gets into a csv file.
|
||||
* the file is created and opend on the first write, to not create a lot of empty files that are not required.
|
||||
* it requires 3 ints:
|
||||
* id: the id of the dump file
|
||||
* simstep: the current simulation step
|
||||
* word: the data word to be written
|
||||
* it return 1 on success
|
||||
*/
|
||||
struct expr_res dump_to_file (int num, struct expr_res *args)
|
||||
{
|
||||
struct expr_res t;
|
||||
t.v = 0 ;
|
||||
t.width = 1;
|
||||
if (num !=3 ){
|
||||
fprintf(logfile,"[ERROR] wrong number of arguments in dump_to_file\n");
|
||||
return t;
|
||||
}
|
||||
if (!dump_file[args[0].v]){
|
||||
char filename[255];
|
||||
snprintf(filename, 255, DUMP_FILENAME,args[0].v);
|
||||
dump_file[args[0].v] = fopen(filename,"w");
|
||||
}
|
||||
if (dump_file[args[0].v]){
|
||||
fprintf(dump_file[args[0].v], CSV_WRITE_FORMAT, args[1].v, args[2].v); fflush(dump_file[args[0].v]);
|
||||
t.v = 1;
|
||||
return t;
|
||||
}
|
||||
else{
|
||||
fprintf(logfile,"[ERROR] writing failed, file not open for dump %d\n",args[0].v); fflush(logfile);
|
||||
t.v = 0;
|
||||
return t;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* control next hecks if there is a next simulation step to be loaded and if a delay needs to be triggered
|
||||
* it requires 1 ints:
|
||||
* ignored: cant have a function call without
|
||||
* it returns 1 if there is a new step
|
||||
*/
|
||||
struct expr_res control_next (int num, struct expr_res *args)
|
||||
{
|
||||
struct expr_res t;
|
||||
t.v = 0 ;
|
||||
t.width = 1;
|
||||
if (num !=1 ){
|
||||
fprintf(logfile,"[ERROR] wrong number of arguments in dump_to_file\n");
|
||||
return t;
|
||||
}
|
||||
if (current_sim_step < first_sim_step) {
|
||||
current_sim_step = first_sim_step;
|
||||
t.v = 1 ;
|
||||
}
|
||||
else if (current_sim_step >= last_sim_step){
|
||||
return t;
|
||||
}
|
||||
else {
|
||||
current_sim_step++;
|
||||
t.v = 1 ;
|
||||
}
|
||||
int step_done = 0;
|
||||
unsigned int sim_step_file = 0;
|
||||
unsigned long int sim_data_file = 0;
|
||||
while (!step_done){
|
||||
int success = 0;
|
||||
success = fscanf(control_file, CSV_FORMAT, &sim_step_file, &sim_data_file);
|
||||
if (success != 2) {
|
||||
if(ferror(control_file)) fprintf(logfile,"read error on contol\n");
|
||||
if(verbose) fprintf(logfile,"EOF on ctl\n"); fflush(logfile);
|
||||
current_sim_wait = 0;
|
||||
step_done = 1;
|
||||
}
|
||||
if (sim_step_file == current_sim_step){
|
||||
step_done = 1;
|
||||
if(verbose) fprintf(logfile,"wait %d\n",sim_data_file); fflush(logfile);
|
||||
current_sim_wait = sim_data_file;
|
||||
}
|
||||
}
|
||||
return t;
|
||||
}
|
||||
|
||||
/**
|
||||
* control_get returns the current time_step, to advance a step call control_next
|
||||
* ignores all input
|
||||
* returns the current simstep
|
||||
*/
|
||||
struct expr_res control_get (int num, struct expr_res *args)
|
||||
{
|
||||
struct expr_res t;
|
||||
t.v = current_sim_step;
|
||||
t.width = 32;
|
||||
return t;
|
||||
}
|
||||
|
||||
/**
|
||||
* control_get returns the wait time required after the current time_step, to advance a step call control_next
|
||||
* ignores all input
|
||||
* returns the current wait time
|
||||
*/
|
||||
struct expr_res control_wait (int num, struct expr_res *args)
|
||||
{
|
||||
struct expr_res t;
|
||||
t.v = current_sim_wait;
|
||||
t.width = 32;
|
||||
return t;
|
||||
}
|
||||
118
readme.md
118
readme.md
|
|
@ -1 +1,117 @@
|
|||
# function lib test bench
|
||||
# lib test bench
|
||||
|
||||
is build to load test vectors from CSV files into your actsim or mixed signal simulation.
|
||||
the library contains multiple source and check as well as dump helpers.
|
||||
|
||||
## The Concept
|
||||
|
||||
each test bench consists out of:
|
||||
|
||||
- a DUT - device under test
|
||||
- multiple sources
|
||||
- multiple checker or dumpers
|
||||
- a controller - responcible for syncronising the release of test vectors
|
||||
|
||||
the execution order of the test bench is defined by the simulation steps and the order of the test vectors inside the simulation step
|
||||
|
||||
before the test bench proceeds to the next simulation step, it waits untill
|
||||
- all sources have sent their test vectors
|
||||
- all checkes have recieved all exspeced inputs
|
||||
- the specified wait time for the simulation step has elapsed after the 2 conditions above have been satisfied.
|
||||
|
||||
|
||||
the reason the test bench lib is splitt in components is that you can assable it to your need without writing it new for evert DUT
|
||||
|
||||
the reason to load a control file is that you can run different test suits with the same test
|
||||
bench by changing the set of csv files.
|
||||
|
||||
### Limitations for verilog
|
||||
Cadence AMS:
|
||||
|
||||
\- the test vector files can contain a maximum of 2.2M rows per simulation step, as they are cached for out of order checks
|
||||
(`` `parameter integer MAX_CHECKS = 2200000; ``\`)
|
||||
|
||||
## The Control
|
||||
|
||||
a test bench includes one test bench controller that excecutes reset (verilog, prs), the
|
||||
simulation step and the time out/end of the simulation (verilog)
|
||||
|
||||
Note:
|
||||
because the controller sets the time out in verilog set your simulation time in your simulator to way more than needed, the TB will end the simulation for you!
|
||||
|
||||
this unit is called **control**, it reads a file with the name `control.csv`.
|
||||
|
||||
the csv format is, one line per simulation step:
|
||||
``` first line: <start step>, <end step> all other lines: <simulation step>, <time to wait for> ```
|
||||
|
||||
step 0 is the test initialisation - so the reset sequence - and is always
|
||||
executed, it can not be used in the test bench.
|
||||
|
||||
verilog: wait statements are in ns (default for candence AMS) but can be changed in the simulatior options.
|
||||
|
||||
actsim: 0 means no wait, any positive number is waiting untill all signals have settled "cycle" (@TODO not supported yet)
|
||||
|
||||
the controll needs to be connected to sources, checkers and dumps, with both sim_step and done (excep dump)
|
||||
|
||||
before the test bench proceeds to the next simulation step, it waits until
|
||||
- all sources have sent their test vectors
|
||||
- all checkes have recieved all exspeced inputs
|
||||
- the specified wait time for the simulation step has elapsed after the 2 conditions above have been satisfied.
|
||||
|
||||
## The Sources
|
||||
|
||||
the async sources present a word and initiate a handshake.
|
||||
|
||||
the csv format is: ``` <simulation_step>; <data to send>```
|
||||
|
||||
the file name is `source_<ID>.csv`. the ID is a variable specified during the buiding of the test bench, the numbering does not have to be consecutive.
|
||||
|
||||
for the normal sources excl. fifo/serial, the maximum vector width is assumed with 64 bits, as limited by actsim plugin system
|
||||
|
||||
the simultaion_step has to be >= 1
|
||||
|
||||
## The Checkers
|
||||
|
||||
the testers compare the in coming data to the vectors written in the csv
|
||||
file.
|
||||
|
||||
|
||||
there are different checkers:
|
||||
|
||||
- check in order: all vectors have to appear in the order of the file inside a simulation step
|
||||
- check out of order: all vector can appear in random order, but each vector can only be used once.
|
||||
|
||||
the csv format is: ``` <simulation_step>; <data to send>```
|
||||
|
||||
the file name is `check_<ID>.csv`. the ID is a variable specified during the buiding of the test bench, the numbering does not have to be consecutive.
|
||||
|
||||
for the normal checkers excl. fifo/serial, the maximum vector width is assumed with 64 bits, as limited by actsim plugin system
|
||||
|
||||
## The Dumpers
|
||||
|
||||
the dumpers just write any incomming vector to file with format:
|
||||
|
||||
the csv format is: ``` <simulation_step>; <data to send>```
|
||||
|
||||
the file name is `dump_<ID>.csv`. the ID is a variable specified during the buiding of the test bench, the numbering does not have to be consecutive.
|
||||
|
||||
the maximum vector width is assumed with 64 bits, as limited by actsim plugin system
|
||||
|
||||
## CSV file stucture and location
|
||||
|
||||
currenty the files are read and searched in the excecution folder of actsim.
|
||||
|
||||
## running actsim
|
||||
|
||||
the config file has to be included to load the test bench,
|
||||
|
||||
call `make install`
|
||||
|
||||
and after you can run ``` actsim -cnf=$ACT_HOME/tech/generic/actsim_test_bench_lib.conf <act file> <process> ```
|
||||
|
||||
## outstanding features:
|
||||
|
||||
- [ ] sources with seperate address and data buses
|
||||
- [ ] verilog files in oa structure - what to do with symbols?
|
||||
- [ ] serial sources and checkers like scanchain/fifo/spi
|
||||
- [ ] actsim PRS support (incl reset) as ref=1
|
||||
|
|
|
|||
Loading…
Reference in New Issue