bics/test_bench_lib
24
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
1 Commit 1 Branch 0 Tags
952cf050c8d98c86c1f6114b335a214ccf236528
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Ole Richter 952cf050c8 initial commit
2021-02-19 09:33:49 -05:00
.gitignore
initial commit
2021-02-19 09:33:49 -05:00
readme.md
initial commit
2021-02-19 09:33:49 -05:00

readme.md

function lib test bench

Reference in New Issue View Git Blame Copy Permalink
S
Description
This is a test bench library for use with async DUTs for both actsim CHP, actsim PRS and Cadence AMS simulations (or other verilog simulators). The test benches are supposed to be modular and are controlled by a set of CSV files.
Readme
64 KiB
Languages
C 92.3%
Makefile 7.7%