bics/test_bench_lib
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Ole Richter 952cf050c8 initial commit
2021-02-19 09:33:49 -05:00
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readme.md
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readme.md

function lib test bench

Description
This is a test bench library for use with async DUTs for both actsim CHP, actsim PRS and Cadence AMS simulations (or other verilog simulators). The test benches are supposed to be modular and are controlled by a set of CSV files.
Readme 64 KiB
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C 92.3%
Makefile 7.7%