actlib_dataflow_neuro/test/unit_tests/chip_nomap/test.prsim

watchall


set c.bd_dly_cfg[0] 1
set c.bd_dly_cfg[1] 1
set c.bd_dly_cfg[2] 1
set c.bd_dly_cfg[3] 1

set-bd-channel-neutral "c.in" 14
# set-bd-channel-neutral "c.out" 14
set c.out.a 0
set c.loopback_en 1
set Reset 1

cycle

mode run
status X
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle

set-bd-channel-valid "c.in" 14 16128
cycle
assert-bd-channel-valid "c.out" 14 16128