actlib_dataflow_neuro/test/unit_tests/texel_small/test.act

/*************************************************************************
 *
 *  This file is part of ACT dataflow neuro library.
 * It's the testing facility for cell_lib_std.act
 *
 *  Copyright (c) 2022 University of Groningen - Ole Richter  
 *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
 *  Copyright (c) 2022 University of Groningen - Michele Mastella
 *  Copyright (c) 2022 University of Groningen - Madison Cotteret
 *
 *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
 *
 *  You may redistribute and modify this documentation and make products
 *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
 *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
 *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
 *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
 *  for applicable conditions.
 *
 *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
 *
 *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
 *  these sources, You must maintain the Source Location visible in its
 *  documentation.
 *
 **************************************************************************
 */

import "../../dataflow_neuro/coders.act";
import "../../dataflow_neuro/primitives.act";
import "../../dataflow_neuro/chips.act";

import globals;
import std::data;

open std::data;


open tmpl::dataflow_neuro;

defproc chip_texel_test (bd<14> in; bd<14> out; Mx1of2<8> reg_data[16];
    bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en){

    bool _reset_B; 
    prs {
        Reset => _reset_B-
    }
    power supply;
    supply.vdd = Vdd;
    supply.vss = GND;

    pint N_IN = 14;
    
    pint N_NRN_X = 2;
    pint N_NRN_Y = 4;
    // pint NC_NRN_X = std:ceil_log2(N_NRN_X);
    // pint NC_NRN_Y = std:ceil_log2(N_NRN_Y);
    pint NC_NRN_X = 1;
    pint NC_NRN_Y = 2;

    pint N_SYN_X = 2;
    pint N_SYN_Y = 4;
    // pint NC_SYN_X = std:ceil_log2(N_SYN_X);
    // pint NC_SYN_Y = std:ceil_log2(N_SYN_Y);
    pint NC_SYN_X = 1;
    pint NC_SYN_Y = 2;

    pint N_SYN_DLY_CFG = 4;
    pint N_BD_DLY_CFG = 4;
    pint N_BD_DLY_CFG2 = 2;

    pint N_NRN_MON_X = N_NRN_X*2; // [mon,kill]*N
    pint N_NRN_MON_Y = N_NRN_Y; // [mon]*N
    // pint N_SYN_MON_X = 2;
    // pint N_SYN_MON_Y = 4;
    pint N_SYN_MON_X = N_SYN_X*4; // [mon, dev_mon, set, reset]*N
    pint N_SYN_MON_Y = N_SYN_Y; //  [mon]*N

    pint N_MON_AMZO_PER_SYN = 5;
    pint N_MON_AMZO_PER_NRN = 7;

    pint N_FLAGS_PER_SYN = 5; // Must be at least 3 (since those ones have special safety)
    pint N_FLAGS_PER_NRN = 7; // And leq than the number of bits in a reg, since have presumed only needs one.

    pint N_BUFFERS = 3;

    pint N_LINE_PD_DLY = 3;
    
    pint REG_NCA = 4;
    pint REG_M = 1<<REG_NCA;
    pint REG_NCW = 8;

    chip_texel<N_IN,
    N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
    NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
    N_SYN_DLY_CFG,
    N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
    N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,
    N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,
    N_BUFFERS,
    N_LINE_PD_DLY,
    N_BD_DLY_CFG, N_BD_DLY_CFG2,
    REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out, .reg_data = reg_data,
        .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2, .loopback_en = loopback_en,
        .reset_B = _reset_B, .supply = supply);

    // Spawn in some buffers as a conduit between neurons and synapses.
    pint N_SYNS = N_SYN_X * N_SYN_Y;
    BUF_X4 syn2nrns_r[N_SYNS];
    BUF_X4 syn2nrns_a[N_SYNS];
    (i:N_SYNS:
        syn2nrns_r[i].a = c.synapses[i].r;
        syn2nrns_r[i].y = c.neurons[i].r;
    
        syn2nrns_a[i].a = c.neurons[i].a;
        syn2nrns_a[i].y = c.synapses[i].a;
    )
    // c.synapses = c.neurons; // Connect each synapse hs to a neuron hs

}


// fifo_decoder_neurons_encoder_fifo e;
chip_texel_test c;