Merge remote-tracking branch 'origin/dev' into dev

dataflow_neuro/cell_lib_std.act

@@ -99,6 +99,18 @@ namespace tmpl {
       sizing { _y {-6,2}; y {-12,4} }
     }
 
+    /*-- delay cells --*/
+    // TODO properly
+
+    export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
+    {
+      bool _y;
+      prs {
+        a => _y-
+        _y => y-
+      }
+    }
+
       
     /*-- simple gates --*/
       

dataflow_neuro/primitives.act

@@ -585,4 +585,59 @@ namespace tmpl {
           BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
           sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
         }
+
+        // Programmable delay line.
+        // N is the number of layers,
+        // the longest layer having 2**N DLY elements
+        export template<pint N>
+        defproc delayprog (bool! y; bool? a, s[N]; power supply)
+        {
+            
+            { N >= 0 : "What?" };
+            { N < 9 : "Delay prog size is given in 2**N. Given N is too big." };
+
+
+            AND2_X1 and2[N];
+            MUX2_X1 mu2[N];
+            DLY4_X1 dly[(1<<N) -1];
+
+            bool _a[N+1]; // Holds the input to each row
+         
+            _a[0] = a;
+
+            pint i_delay;
+            i_delay = 0; // Index of the last connected delay element
+
+            (i:0..N-1:
+                // For each row
+                and2[i].a = _a[i];
+                and2[i].b = s[i];
+
+                // Delays
+                dly[i_delay].a = and2[i].y;
+                i_delay = i_delay + 1;
+                (j:1..i-1:
+                    dly[i_delay].a = dly[i_delay-1].y;
+                    i_delay = i_delay +1;
+                )
+
+                // Mux
+                mu2[i].a = _a[i];
+                mu2[i].s = s[i];
+                dly[i_delay-1].y = mu2[i].b;
+                _a[i+1] = mu2[i].y;
+            )
+
+            y = mu2[N-1].y;
+
+
+            // Connect everything to vdd/gnd
+            (i:N:and2[i].vdd = supply.vdd;)
+            (i:N:mu2[i].vdd = supply.vdd;)
+            (i:((1<<N)-1):dly[i].vdd = supply.vdd;)
+
+            (i:N:and2[i].vss = supply.vss;)
+            (i:N:mu2[i].vss = supply.vss;)
+            (i:((1<<N)-1):dly[i].vss = supply.vss;)
+        }
 }}