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Merge remote-tracking branch 'origin/dev' into dev

This commit is contained in:
Michele 2022-03-01 17:14:15 +01:00
parent 97784db492 79a96ed511
commit 018b308f61
7 changed files with 474 additions and 0 deletions
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12
dataflow_neuro/cell_lib_std.act
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@ -99,6 +99,18 @@ namespace tmpl {
sizing { _y {-6,2}; y {-12,4} } sizing { _y {-6,2}; y {-12,4} }
} }
/*-- delay cells --*/
// TODO properly
export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
{
bool _y;
prs {
a => _y-
_y => y-
}
}
/*-- simple gates --*/ /*-- simple gates --*/

55
dataflow_neuro/primitives.act
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@ -585,4 +585,59 @@ namespace tmpl {
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX); sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
} }
// Programmable delay line.
// N is the number of layers,
// the longest layer having 2**N DLY elements
export template<pint N>
defproc delayprog (bool! y; bool? a, s[N]; power supply)
{
{ N >= 0 : "What?" };
{ N < 9 : "Delay prog size is given in 2**N. Given N is too big." };
AND2_X1 and2[N];
MUX2_X1 mu2[N];
DLY4_X1 dly[(1<<N) -1];
bool _a[N+1]; // Holds the input to each row
_a[0] = a;
pint i_delay;
i_delay = 0; // Index of the last connected delay element
(i:0..N-1:
// For each row
and2[i].a = _a[i];
and2[i].b = s[i];
// Delays
dly[i_delay].a = and2[i].y;
i_delay = i_delay + 1;
(j:1..i-1:
dly[i_delay].a = dly[i_delay-1].y;
i_delay = i_delay +1;
)
// Mux
mu2[i].a = _a[i];
mu2[i].s = s[i];
dly[i_delay-1].y = mu2[i].b;
_a[i+1] = mu2[i].y;
)
y = mu2[N-1].y;
// Connect everything to vdd/gnd
(i:N:and2[i].vdd = supply.vdd;)
(i:N:mu2[i].vdd = supply.vdd;)
(i:((1<<N)-1):dly[i].vdd = supply.vdd;)
(i:N:and2[i].vss = supply.vss;)
(i:N:mu2[i].vss = supply.vss;)
(i:((1<<N)-1):dly[i].vss = supply.vss;)
}
}} }}

134
test/unit_tests/delayprog_4/run/prsim.out Normal file
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@ -0,0 +1,134 @@
t.s[2] t.dp.dly[2].a t.dp._a[1] t.dp.dly[5]._y t.s[3] t.a t.s[0] t.dp.and2[2]._y t.dp.and2[0]._y t.dp._a[3] t.dp.dly[11]._y t.dp._a[2] t.dp.and2[3]._y t.dp.mu2[0]._s t.dp.dly[9]._y t.s[1] t.dp.dly[11].y t.dp.dly[0]._y t.dp.dly[4].y t.dp.dly[6].y t.dp.dly[2]._y t.dp.dly[7]._y t.dp.dly[9].a t.dp.dly[1].y t.dp.dly[1].a t.dp.dly[4].a t.y t.dp.dly[2].y t.dp.dly[14]._y t.dp.dly[10].a t.dp.mu2[2]._s t.dp.dly[6]._y t.dp.dly[1]._y t.dp.dly[12]._y t.dp.dly[5].y t.dp.dly[8].a t.dp.dly[0].a t.dp.dly[7].a t.dp.mu2[0]._y t.dp.mu2[3]._y t.dp.mu2[1]._s t.dp.dly[11].a t.dp.dly[14].a t.dp.dly[13].a t.dp.dly[13]._y t.dp.dly[7].y t.dp.dly[8]._y t.dp.mu2[2]._y t.dp.dly[3].y t.dp.dly[14].y t.dp.dly[0].y t.dp.dly[3]._y t.dp.dly[13].y t.dp.and2[1]._y t.dp.mu2[3]._s t.dp.dly[10].y t.dp.dly[9].y t.dp.dly[4]._y t.dp.dly[12].y t.dp.dly[8].y t.dp.mu2[1]._y t.dp.dly[12].a t.dp.dly[10]._y
0
0 t.a : 0
0 t.s[3] : 1
0 t.s[1] : 1
0 t.s[0] : 1
0 t.s[2] : 1
1 t.dp.and2[0]._y : 1 [by t.a:=0]
2 t.dp.mu2[0]._s : 0 [by t.s[0]:=1]
1138 t.dp.dly[0].a : 0 [by t.dp.and2[0]._y:=1]
1252 t.dp.dly[0]._y : 1 [by t.dp.dly[0].a:=0]
4753 t.dp.mu2[2]._s : 0 [by t.s[2]:=1]
7092 t.dp.mu2[3]._s : 0 [by t.s[3]:=1]
10467 t.dp.mu2[1]._s : 0 [by t.s[1]:=1]
66618 t.dp.dly[0].y : 0 [by t.dp.dly[0]._y:=1]
68344 t.dp.mu2[0]._y : 1 [by t.dp.dly[0].y:=0]
68383 t.dp._a[1] : 0 [by t.dp.mu2[0]._y:=1]
68398 t.dp.and2[1]._y : 1 [by t.dp._a[1]:=0]
68889 t.dp.dly[1].a : 0 [by t.dp.and2[1]._y:=1]
68902 t.dp.dly[1]._y : 1 [by t.dp.dly[1].a:=0]
68942 t.dp.dly[1].y : 0 [by t.dp.dly[1]._y:=1]
69357 t.dp.mu2[1]._y : 1 [by t.dp.dly[1].y:=0]
69377 t.dp._a[2] : 0 [by t.dp.mu2[1]._y:=1]
75438 t.dp.and2[2]._y : 1 [by t.dp._a[2]:=0]
75485 t.dp.dly[2].a : 0 [by t.dp.and2[2]._y:=1]
75501 t.dp.dly[2]._y : 1 [by t.dp.dly[2].a:=0]
119599 t.dp.dly[2].y : 0 [by t.dp.dly[2]._y:=1]
133323 t.dp.dly[3]._y : 1 [by t.dp.dly[2].y:=0]
133327 t.dp.dly[3].y : 0 [by t.dp.dly[3]._y:=1]
142456 t.dp.mu2[2]._y : 1 [by t.dp.dly[3].y:=0]
142471 t.dp._a[3] : 0 [by t.dp.mu2[2]._y:=1]
185719 t.dp.and2[3]._y : 1 [by t.dp._a[3]:=0]
222650 t.dp.dly[4].a : 0 [by t.dp.and2[3]._y:=1]
222705 t.dp.dly[4]._y : 1 [by t.dp.dly[4].a:=0]
274358 t.dp.dly[4].y : 0 [by t.dp.dly[4]._y:=1]
304138 t.dp.dly[5]._y : 1 [by t.dp.dly[4].y:=0]
317987 t.dp.dly[5].y : 0 [by t.dp.dly[5]._y:=1]
342799 t.dp.dly[6]._y : 1 [by t.dp.dly[5].y:=0]
357142 t.dp.dly[6].y : 0 [by t.dp.dly[6]._y:=1]
357564 t.dp.mu2[3]._y : 1 [by t.dp.dly[6].y:=0]
406278 t.y : 0 [by t.dp.mu2[3]._y:=1]
[] setting high
406278 t.a : 1
406279 t.dp.and2[0]._y : 0 [by t.a:=1]
406280 t.dp.dly[0].a : 1 [by t.dp.and2[0]._y:=0]
426485 t.dp.dly[0]._y : 0 [by t.dp.dly[0].a:=1]
426767 t.dp.dly[0].y : 1 [by t.dp.dly[0]._y:=0]
427535 t.dp.mu2[0]._y : 0 [by t.dp.dly[0].y:=1]
427538 t.dp._a[1] : 1 [by t.dp.mu2[0]._y:=0]
449979 t.dp.and2[1]._y : 0 [by t.dp._a[1]:=1]
450530 t.dp.dly[1].a : 1 [by t.dp.and2[1]._y:=0]
451601 t.dp.dly[1]._y : 0 [by t.dp.dly[1].a:=1]
452555 t.dp.dly[1].y : 1 [by t.dp.dly[1]._y:=0]
453636 t.dp.mu2[1]._y : 0 [by t.dp.dly[1].y:=1]
508106 t.dp._a[2] : 1 [by t.dp.mu2[1]._y:=0]
509088 t.dp.and2[2]._y : 0 [by t.dp._a[2]:=1]
509106 t.dp.dly[2].a : 1 [by t.dp.and2[2]._y:=0]
513119 t.dp.dly[2]._y : 0 [by t.dp.dly[2].a:=1]
517122 t.dp.dly[2].y : 1 [by t.dp.dly[2]._y:=0]
562023 t.dp.dly[3]._y : 0 [by t.dp.dly[2].y:=1]
583607 t.dp.dly[3].y : 1 [by t.dp.dly[3]._y:=0]
588367 t.dp.mu2[2]._y : 0 [by t.dp.dly[3].y:=1]
588869 t.dp._a[3] : 1 [by t.dp.mu2[2]._y:=0]
589072 t.dp.and2[3]._y : 0 [by t.dp._a[3]:=1]
590926 t.dp.dly[4].a : 1 [by t.dp.and2[3]._y:=0]
591065 t.dp.dly[4]._y : 0 [by t.dp.dly[4].a:=1]
627411 t.dp.dly[4].y : 1 [by t.dp.dly[4]._y:=0]
627480 t.dp.dly[5]._y : 0 [by t.dp.dly[4].y:=1]
627491 t.dp.dly[5].y : 1 [by t.dp.dly[5]._y:=0]
679277 t.dp.dly[6]._y : 0 [by t.dp.dly[5].y:=1]
679481 t.dp.dly[6].y : 1 [by t.dp.dly[6]._y:=0]
679496 t.dp.mu2[3]._y : 0 [by t.dp.dly[6].y:=1]
679497 t.y : 1 [by t.dp.mu2[3]._y:=0]
[] setting low
679497 t.a : 0
679534 t.dp.and2[0]._y : 1 [by t.a:=0]
680273 t.dp.dly[0].a : 0 [by t.dp.and2[0]._y:=1]
680385 t.dp.dly[0]._y : 1 [by t.dp.dly[0].a:=0]
727897 t.dp.dly[0].y : 0 [by t.dp.dly[0]._y:=1]
727937 t.dp.mu2[0]._y : 1 [by t.dp.dly[0].y:=0]
728194 t.dp._a[1] : 0 [by t.dp.mu2[0]._y:=1]
728281 t.dp.and2[1]._y : 1 [by t.dp._a[1]:=0]
728575 t.dp.dly[1].a : 0 [by t.dp.and2[1]._y:=1]
728576 t.dp.dly[1]._y : 1 [by t.dp.dly[1].a:=0]
730382 t.dp.dly[1].y : 0 [by t.dp.dly[1]._y:=1]
732389 t.dp.mu2[1]._y : 1 [by t.dp.dly[1].y:=0]
733598 t.dp._a[2] : 0 [by t.dp.mu2[1]._y:=1]
734188 t.dp.and2[2]._y : 1 [by t.dp._a[2]:=0]
734366 t.dp.dly[2].a : 0 [by t.dp.and2[2]._y:=1]
735169 t.dp.dly[2]._y : 1 [by t.dp.dly[2].a:=0]
735333 t.dp.dly[2].y : 0 [by t.dp.dly[2]._y:=1]
737528 t.dp.dly[3]._y : 1 [by t.dp.dly[2].y:=0]
737550 t.dp.dly[3].y : 0 [by t.dp.dly[3]._y:=1]
738397 t.dp.mu2[2]._y : 1 [by t.dp.dly[3].y:=0]
768525 t.dp._a[3] : 0 [by t.dp.mu2[2]._y:=1]
768658 t.dp.and2[3]._y : 1 [by t.dp._a[3]:=0]
784320 t.dp.dly[4].a : 0 [by t.dp.and2[3]._y:=1]
784679 t.dp.dly[4]._y : 1 [by t.dp.dly[4].a:=0]
798795 t.dp.dly[4].y : 0 [by t.dp.dly[4]._y:=1]
799016 t.dp.dly[5]._y : 1 [by t.dp.dly[4].y:=0]
799023 t.dp.dly[5].y : 0 [by t.dp.dly[5]._y:=1]
799053 t.dp.dly[6]._y : 1 [by t.dp.dly[5].y:=0]
805766 t.dp.dly[6].y : 0 [by t.dp.dly[6]._y:=1]
863227 t.dp.mu2[3]._y : 1 [by t.dp.dly[6].y:=0]
863318 t.y : 0 [by t.dp.mu2[3]._y:=1]
[] setting configs low
863318 t.s[0] : 0
863318 t.s[3] : 0
863318 t.s[2] : 0
863318 t.s[1] : 0
863325 t.dp.mu2[3]._s : 1 [by t.s[3]:=0]
863424 t.dp.mu2[1]._s : 1 [by t.s[1]:=0]
865507 t.dp.mu2[0]._s : 1 [by t.s[0]:=0]
866105 t.dp.mu2[2]._s : 1 [by t.s[2]:=0]
[] setting high
866105 t.a : 1
866183 t.dp.mu2[0]._y : 0 [by t.a:=1]
866458 t.dp._a[1] : 1 [by t.dp.mu2[0]._y:=0]
885454 t.dp.mu2[1]._y : 0 [by t.dp._a[1]:=1]
885909 t.dp._a[2] : 1 [by t.dp.mu2[1]._y:=0]
885921 t.dp.mu2[2]._y : 0 [by t.dp._a[2]:=1]
886325 t.dp._a[3] : 1 [by t.dp.mu2[2]._y:=0]
886337 t.dp.mu2[3]._y : 0 [by t.dp._a[3]:=1]
892253 t.y : 1 [by t.dp.mu2[3]._y:=0]
[] setting low
892253 t.a : 0
896529 t.dp.mu2[0]._y : 1 [by t.a:=0]
899428 t.dp._a[1] : 0 [by t.dp.mu2[0]._y:=1]
903723 t.dp.mu2[1]._y : 1 [by t.dp._a[1]:=0]
903725 t.dp._a[2] : 0 [by t.dp.mu2[1]._y:=1]
908260 t.dp.mu2[2]._y : 1 [by t.dp._a[2]:=0]
909509 t.dp._a[3] : 0 [by t.dp.mu2[2]._y:=1]
913008 t.dp.mu2[3]._y : 1 [by t.dp._a[3]:=0]
913174 t.y : 0 [by t.dp.mu2[3]._y:=1]

BIN
test/unit_tests/delayprog_4/run/prsim.pdf Normal file
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Binary file not shown.

190
test/unit_tests/delayprog_4/run/test.prs Normal file
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@ -0,0 +1,190 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
= "t.y" "t.dp.y"
= "t.a" "t.dp.a"
= "t.dp.a" "t.dp.mu2[0].a"
= "t.dp.a" "t.dp.and2[0].a"
= "t.dp.a" "t.dp._a[0]"
"t.dp.and2[0].a"&"t.dp.and2[0].b"->"t.dp.and2[0]._y"-
~("t.dp.and2[0].a"&"t.dp.and2[0].b")->"t.dp.and2[0]._y"+
"t.dp.and2[0]._y"->"t.dp.and2[0].y"-
~("t.dp.and2[0]._y")->"t.dp.and2[0].y"+
"t.dp.and2[1].a"&"t.dp.and2[1].b"->"t.dp.and2[1]._y"-
~("t.dp.and2[1].a"&"t.dp.and2[1].b")->"t.dp.and2[1]._y"+
"t.dp.and2[1]._y"->"t.dp.and2[1].y"-
~("t.dp.and2[1]._y")->"t.dp.and2[1].y"+
"t.dp.and2[2].a"&"t.dp.and2[2].b"->"t.dp.and2[2]._y"-
~("t.dp.and2[2].a"&"t.dp.and2[2].b")->"t.dp.and2[2]._y"+
"t.dp.and2[2]._y"->"t.dp.and2[2].y"-
~("t.dp.and2[2]._y")->"t.dp.and2[2].y"+
"t.dp.and2[3].a"&"t.dp.and2[3].b"->"t.dp.and2[3]._y"-
~("t.dp.and2[3].a"&"t.dp.and2[3].b")->"t.dp.and2[3]._y"+
"t.dp.and2[3]._y"->"t.dp.and2[3].y"-
~("t.dp.and2[3]._y")->"t.dp.and2[3].y"+
= "t.dp.s[0]" "t.dp.mu2[0].s"
= "t.dp.s[0]" "t.dp.and2[0].b"
= "t.dp.s[1]" "t.dp.mu2[1].s"
= "t.dp.s[1]" "t.dp.and2[1].b"
= "t.dp.s[2]" "t.dp.mu2[2].s"
= "t.dp.s[2]" "t.dp.and2[2].b"
= "t.dp.s[3]" "t.dp.mu2[3].s"
= "t.dp.s[3]" "t.dp.and2[3].b"
= "t.dp.supply.vdd" "t.dp.dly[14].vdd"
= "t.dp.supply.vdd" "t.dp.dly[13].vdd"
= "t.dp.supply.vdd" "t.dp.dly[12].vdd"
= "t.dp.supply.vdd" "t.dp.dly[11].vdd"
= "t.dp.supply.vdd" "t.dp.dly[10].vdd"
= "t.dp.supply.vdd" "t.dp.dly[9].vdd"
= "t.dp.supply.vdd" "t.dp.dly[8].vdd"
= "t.dp.supply.vdd" "t.dp.dly[7].vdd"
= "t.dp.supply.vdd" "t.dp.dly[6].vdd"
= "t.dp.supply.vdd" "t.dp.dly[5].vdd"
= "t.dp.supply.vdd" "t.dp.dly[4].vdd"
= "t.dp.supply.vdd" "t.dp.dly[3].vdd"
= "t.dp.supply.vdd" "t.dp.dly[2].vdd"
= "t.dp.supply.vdd" "t.dp.dly[1].vdd"
= "t.dp.supply.vdd" "t.dp.dly[0].vdd"
= "t.dp.supply.vdd" "t.dp.mu2[3].vdd"
= "t.dp.supply.vdd" "t.dp.mu2[2].vdd"
= "t.dp.supply.vdd" "t.dp.mu2[1].vdd"
= "t.dp.supply.vdd" "t.dp.mu2[0].vdd"
= "t.dp.supply.vdd" "t.dp.and2[3].vdd"
= "t.dp.supply.vdd" "t.dp.and2[2].vdd"
= "t.dp.supply.vdd" "t.dp.and2[1].vdd"
= "t.dp.supply.vdd" "t.dp.and2[0].vdd"
= "t.dp.supply.vss" "t.dp.dly[14].vss"
= "t.dp.supply.vss" "t.dp.dly[13].vss"
= "t.dp.supply.vss" "t.dp.dly[12].vss"
= "t.dp.supply.vss" "t.dp.dly[11].vss"
= "t.dp.supply.vss" "t.dp.dly[10].vss"
= "t.dp.supply.vss" "t.dp.dly[9].vss"
= "t.dp.supply.vss" "t.dp.dly[8].vss"
= "t.dp.supply.vss" "t.dp.dly[7].vss"
= "t.dp.supply.vss" "t.dp.dly[6].vss"
= "t.dp.supply.vss" "t.dp.dly[5].vss"
= "t.dp.supply.vss" "t.dp.dly[4].vss"
= "t.dp.supply.vss" "t.dp.dly[3].vss"
= "t.dp.supply.vss" "t.dp.dly[2].vss"
= "t.dp.supply.vss" "t.dp.dly[1].vss"
= "t.dp.supply.vss" "t.dp.dly[0].vss"
= "t.dp.supply.vss" "t.dp.mu2[3].vss"
= "t.dp.supply.vss" "t.dp.mu2[2].vss"
= "t.dp.supply.vss" "t.dp.mu2[1].vss"
= "t.dp.supply.vss" "t.dp.mu2[0].vss"
= "t.dp.supply.vss" "t.dp.and2[3].vss"
= "t.dp.supply.vss" "t.dp.and2[2].vss"
= "t.dp.supply.vss" "t.dp.and2[1].vss"
= "t.dp.supply.vss" "t.dp.and2[0].vss"
"t.dp.mu2[0].s"->"t.dp.mu2[0]._s"-
~("t.dp.mu2[0].s")->"t.dp.mu2[0]._s"+
~"t.dp.mu2[0].a"&~"t.dp.mu2[0].s"|~"t.dp.mu2[0].b"&~"t.dp.mu2[0]._s"->"t.dp.mu2[0]._y"+
"t.dp.mu2[0].a"&"t.dp.mu2[0]._s"|"t.dp.mu2[0].b"&"t.dp.mu2[0].s"->"t.dp.mu2[0]._y"-
"t.dp.mu2[0]._y"->"t.dp.mu2[0].y"-
~("t.dp.mu2[0]._y")->"t.dp.mu2[0].y"+
"t.dp.mu2[1].s"->"t.dp.mu2[1]._s"-
~("t.dp.mu2[1].s")->"t.dp.mu2[1]._s"+
~"t.dp.mu2[1].a"&~"t.dp.mu2[1].s"|~"t.dp.mu2[1].b"&~"t.dp.mu2[1]._s"->"t.dp.mu2[1]._y"+
"t.dp.mu2[1].a"&"t.dp.mu2[1]._s"|"t.dp.mu2[1].b"&"t.dp.mu2[1].s"->"t.dp.mu2[1]._y"-
"t.dp.mu2[1]._y"->"t.dp.mu2[1].y"-
~("t.dp.mu2[1]._y")->"t.dp.mu2[1].y"+
"t.dp.mu2[2].s"->"t.dp.mu2[2]._s"-
~("t.dp.mu2[2].s")->"t.dp.mu2[2]._s"+
~"t.dp.mu2[2].a"&~"t.dp.mu2[2].s"|~"t.dp.mu2[2].b"&~"t.dp.mu2[2]._s"->"t.dp.mu2[2]._y"+
"t.dp.mu2[2].a"&"t.dp.mu2[2]._s"|"t.dp.mu2[2].b"&"t.dp.mu2[2].s"->"t.dp.mu2[2]._y"-
"t.dp.mu2[2]._y"->"t.dp.mu2[2].y"-
~("t.dp.mu2[2]._y")->"t.dp.mu2[2].y"+
"t.dp.mu2[3].s"->"t.dp.mu2[3]._s"-
~("t.dp.mu2[3].s")->"t.dp.mu2[3]._s"+
~"t.dp.mu2[3].a"&~"t.dp.mu2[3].s"|~"t.dp.mu2[3].b"&~"t.dp.mu2[3]._s"->"t.dp.mu2[3]._y"+
"t.dp.mu2[3].a"&"t.dp.mu2[3]._s"|"t.dp.mu2[3].b"&"t.dp.mu2[3].s"->"t.dp.mu2[3]._y"-
"t.dp.mu2[3]._y"->"t.dp.mu2[3].y"-
~("t.dp.mu2[3]._y")->"t.dp.mu2[3].y"+
"t.dp.dly[0].a"->"t.dp.dly[0]._y"-
~("t.dp.dly[0].a")->"t.dp.dly[0]._y"+
"t.dp.dly[0]._y"->"t.dp.dly[0].y"-
~("t.dp.dly[0]._y")->"t.dp.dly[0].y"+
"t.dp.dly[1].a"->"t.dp.dly[1]._y"-
~("t.dp.dly[1].a")->"t.dp.dly[1]._y"+
"t.dp.dly[1]._y"->"t.dp.dly[1].y"-
~("t.dp.dly[1]._y")->"t.dp.dly[1].y"+
"t.dp.dly[2].a"->"t.dp.dly[2]._y"-
~("t.dp.dly[2].a")->"t.dp.dly[2]._y"+
"t.dp.dly[2]._y"->"t.dp.dly[2].y"-
~("t.dp.dly[2]._y")->"t.dp.dly[2].y"+
"t.dp.dly[3].a"->"t.dp.dly[3]._y"-
~("t.dp.dly[3].a")->"t.dp.dly[3]._y"+
"t.dp.dly[3]._y"->"t.dp.dly[3].y"-
~("t.dp.dly[3]._y")->"t.dp.dly[3].y"+
"t.dp.dly[4].a"->"t.dp.dly[4]._y"-
~("t.dp.dly[4].a")->"t.dp.dly[4]._y"+
"t.dp.dly[4]._y"->"t.dp.dly[4].y"-
~("t.dp.dly[4]._y")->"t.dp.dly[4].y"+
"t.dp.dly[5].a"->"t.dp.dly[5]._y"-
~("t.dp.dly[5].a")->"t.dp.dly[5]._y"+
"t.dp.dly[5]._y"->"t.dp.dly[5].y"-
~("t.dp.dly[5]._y")->"t.dp.dly[5].y"+
"t.dp.dly[6].a"->"t.dp.dly[6]._y"-
~("t.dp.dly[6].a")->"t.dp.dly[6]._y"+
"t.dp.dly[6]._y"->"t.dp.dly[6].y"-
~("t.dp.dly[6]._y")->"t.dp.dly[6].y"+
"t.dp.dly[7].a"->"t.dp.dly[7]._y"-
~("t.dp.dly[7].a")->"t.dp.dly[7]._y"+
"t.dp.dly[7]._y"->"t.dp.dly[7].y"-
~("t.dp.dly[7]._y")->"t.dp.dly[7].y"+
"t.dp.dly[8].a"->"t.dp.dly[8]._y"-
~("t.dp.dly[8].a")->"t.dp.dly[8]._y"+
"t.dp.dly[8]._y"->"t.dp.dly[8].y"-
~("t.dp.dly[8]._y")->"t.dp.dly[8].y"+
"t.dp.dly[9].a"->"t.dp.dly[9]._y"-
~("t.dp.dly[9].a")->"t.dp.dly[9]._y"+
"t.dp.dly[9]._y"->"t.dp.dly[9].y"-
~("t.dp.dly[9]._y")->"t.dp.dly[9].y"+
"t.dp.dly[10].a"->"t.dp.dly[10]._y"-
~("t.dp.dly[10].a")->"t.dp.dly[10]._y"+
"t.dp.dly[10]._y"->"t.dp.dly[10].y"-
~("t.dp.dly[10]._y")->"t.dp.dly[10].y"+
"t.dp.dly[11].a"->"t.dp.dly[11]._y"-
~("t.dp.dly[11].a")->"t.dp.dly[11]._y"+
"t.dp.dly[11]._y"->"t.dp.dly[11].y"-
~("t.dp.dly[11]._y")->"t.dp.dly[11].y"+
"t.dp.dly[12].a"->"t.dp.dly[12]._y"-
~("t.dp.dly[12].a")->"t.dp.dly[12]._y"+
"t.dp.dly[12]._y"->"t.dp.dly[12].y"-
~("t.dp.dly[12]._y")->"t.dp.dly[12].y"+
"t.dp.dly[13].a"->"t.dp.dly[13]._y"-
~("t.dp.dly[13].a")->"t.dp.dly[13]._y"+
"t.dp.dly[13]._y"->"t.dp.dly[13].y"-
~("t.dp.dly[13]._y")->"t.dp.dly[13].y"+
"t.dp.dly[14].a"->"t.dp.dly[14]._y"-
~("t.dp.dly[14].a")->"t.dp.dly[14]._y"+
"t.dp.dly[14]._y"->"t.dp.dly[14].y"-
~("t.dp.dly[14]._y")->"t.dp.dly[14].y"+
= "t.dp.dly[6].y" "t.dp.mu2[3].b"
= "t.dp.dly[6].a" "t.dp.dly[5].y"
= "t.dp.dly[5].a" "t.dp.dly[4].y"
= "t.dp.dly[4].a" "t.dp.and2[3].y"
= "t.dp.dly[3].y" "t.dp.mu2[2].b"
= "t.dp.dly[3].a" "t.dp.dly[2].y"
= "t.dp.dly[2].a" "t.dp.and2[2].y"
= "t.dp.dly[1].y" "t.dp.mu2[1].b"
= "t.dp.dly[1].a" "t.dp.and2[1].y"
= "t.dp.dly[0].y" "t.dp.mu2[0].b"
= "t.dp.dly[0].a" "t.dp.and2[0].y"
= "t.dp._a[1]" "t.dp.mu2[1].a"
= "t.dp._a[1]" "t.dp.and2[1].a"
= "t.dp._a[1]" "t.dp.mu2[0].y"
= "t.dp._a[2]" "t.dp.mu2[2].a"
= "t.dp._a[2]" "t.dp.and2[2].a"
= "t.dp._a[2]" "t.dp.mu2[1].y"
= "t.dp._a[3]" "t.dp.mu2[3].a"
= "t.dp._a[3]" "t.dp.and2[3].a"
= "t.dp._a[3]" "t.dp.mu2[2].y"
= "t.dp.y" "t.dp.mu2[3].y"
= "t.dp.y" "t.dp._a[4]"
= "Vdd" "t.dp.supply.vdd"
= "GND" "t.dp.supply.vss"
= "t.s[0]" "t.dp.s[0]"
= "t.s[1]" "t.dp.s[1]"
= "t.s[2]" "t.dp.s[2]"
= "t.s[3]" "t.dp.s[3]"

41
test/unit_tests/delayprog_4/test.act Normal file
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@ -0,0 +1,41 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc delayprog_4 (bool? s[4], a; bool! y){
delayprog<4> dp(.a=a, .y=y, .s = s);
dp.supply.vss = GND;
dp.supply.vdd = Vdd;
}
delayprog_4 t;

42
test/unit_tests/delayprog_4/test.prsim Normal file
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watchall
system "echo '0'"
set t.a 0
set t.s[0] 1
set t.s[1] 1
set t.s[2] 1
set t.s[3] 1
cycle
mode run
assert t.y 0
system "echo '[] setting high'"
set t.a 1
cycle
assert t.y 1
system "echo '[] setting low'"
set t.a 0
cycle
assert t.y 0
system "echo '[] setting configs low'"
set t.s[0] 0
set t.s[1] 0
set t.s[2] 0
set t.s[3] 0
cycle
assert t.y 0
system "echo '[] setting high'"
set t.a 1
cycle
assert t.y 1
system "echo '[] setting low'"
set t.a 0
cycle
assert t.y 0