coders.act file init
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alexmadison
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/cell_lib_async.act";
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import "../../dataflow_neuro/cell_lib_std.act";
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import "../../dataflow_neuro/treegates.act";
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import "../../dataflow_neuro/primitives.act";
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// import tmpl::dataflow_neuro;
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// import tmpl::dataflow_neuro;
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import std::channel;
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open std::channel;
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namespace tmpl {
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namespace dataflow_neuro {
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/**
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* 2D decoder which uses a configurable delay from the VCtrees to buffer ack.
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* Nx is the x size of the decoder array
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* NxC is the number of wires in the x channel.
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* Thus NxC should be something like NxC = ceil(log2(Nx))
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* but my guess is that we can't do logs...
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* N_dly_cfg is the number of config bits in the ACK delay line,
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* with all bits high corresponding to 2**N_dly_cfg -1 DLY1_X4 cells.
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*/
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// export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
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// defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? dly_cfg[N_dly_cfg], reset_B; power supply) {
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// // Buffer to recieve concat(x,y) address packet
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// buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
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// // NEED TO BUFFER OUTPUTS FROM BUFFER I RECKON
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// // Validity trees
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// vtree<NxC> vtree_x (.power = supply);
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// vtree<NyC> vtree_y (.power = supply);
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// (i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
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// (i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
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// (i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
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// (i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
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// // Delay ack line. Ack line is delayed (but not the val)
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// A_2X_B_X1 C2el(.a = vtree_x.out, .b = vtree_y.out, .supply = supply);
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// addr_buf.out.v = C2el.y;
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// delayprog<N_dly_cfg> dly(.in = C2el.y, .s = dly_cfg, .supply = supply);
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// delayprog.out = addr_buf.out.a;
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// // AND trees
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// pint bitval;
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// andtree<NxC> atree_x[Nx];
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// (i:0..Nx-1:
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// (j:0..NxC:
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// bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
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// [bitval == 1 ->
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// atree_x[i].in[j] = addr_buf.out.d.d[j].t
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// []bitval == 0 ->
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// atree_x[i].in[j] = addr_buf.out.d.d[j].f
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// ]
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// )
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// )
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// andtree<NyC> atree_y[Ny];
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// (i:0..Ny-1:
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// (j:0..NyC:
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// bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
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// [bitval == 1 ->
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// atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].t
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// []bitval == 0 ->
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// atree_y[i].in[j] = addr_buf.out.d.d[j+NxC].f
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// ]
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// )
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// )
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// // Connect stuff to vdd/vss
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// (i:0..Nx-1:atree_x[i].supply = supply)
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// //control
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// bool _en, _reset_BX,_reset_BXX[N];
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// A_3C_RB_X4 inack_ctl(.c1=_en,.c2=in.v,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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// A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
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// BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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// sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX);
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// //validity
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// bool _in_v;
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// vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
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// BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
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// //function
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// bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B,_en_X_t[N],_en_X_f[N];
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// A_2C1N_RB_X4 f_buf_func[N];
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// A_2C1N_RB_X4 t_buf_func[N];
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// sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
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// sigbuf<N> en_buf_f(.in=_en, .out=_en_X_f, .supply=supply);
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// INV_X1 out_a_inv(.a=out.a,.y=_out_a_B);
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// sigbuf<N> out_a_B_buf_f(.in=_out_a_B,.out=_out_a_BX_t);
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// sigbuf<N> out_a_B_buf_t(.in=_out_a_B,.out=_out_a_BX_f);
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// // check if you can also do single var to array connect a=b[N]
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// // and remove them from the loop
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// (i:N:
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// f_buf_func[i].y=out.d.d[i].f;
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// t_buf_func[i].y=out.d.d[i].t;
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// f_buf_func[i].c1=_en_X_f[i];
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// t_buf_func[i].c1=_en_X_t[i];
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// f_buf_func[i].c2=_out_a_BX_f[i];
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// t_buf_func[i].c2=_out_a_BX_t[i];
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// f_buf_func[i].n1=in.d.d[i].f;
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// t_buf_func[i].n1=in.d.d[i].t;
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// f_buf_func[i].vdd=supply.vdd;
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// t_buf_func[i].vdd=supply.vdd;
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// f_buf_func[i].vss=supply.vss;
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// t_buf_func[i].vss=supply.vss;
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// t_buf_func[i].pr_B = _reset_BXX[i];
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// t_buf_func[i].sr_B = _reset_BXX[i];
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// f_buf_func[i].pr_B = _reset_BXX[i];
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// f_buf_func[i].sr_B = _reset_BXX[i];
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)
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}
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}
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}
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