Merge remote-tracking branch 'origin/dev' into dev
This commit is contained in:
commit
432ea397d1
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@ -106,7 +106,7 @@ defproc chip_texel (bd<N_IN> in, out;
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NC_NRN = NC_NRN_X + NC_NRN_Y;
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nrn_hs_2d_array<N_NRN_X,N_NRN_Y,N_LINE_PD_DLY> nrn_grid(.in = neurons,
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.supply = supply, .reset_B = reset_B);
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encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, 16> encoder(
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encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y> encoder(
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.inx = nrn_grid.outx,
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.iny = nrn_grid.outy,
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.reset_B = reset_B, .supply = supply
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@ -774,7 +774,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
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}
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export template<pint NxC, NyC, Nx, Ny, ACK_STRENGTH>
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export template<pint NxC, NyC, Nx, Ny>
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defproc encoder2d_simple(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out;
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power supply; bool reset_B) {
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@ -827,6 +827,42 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
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}
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export template<pint Nc, N>
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defproc encoder1d_simple(a1of1 in[N]; avMx1of2<Nc> out;
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power supply; bool reset_B) {
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bool _a_x, _r_x;
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bool _r_x_B;
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buffer<Nc> buf(.out = out, .supply = supply, .reset_B = reset_B);
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// Arbiters
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arbtree<N> Xarb(.supply = supply);
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Xarb.out.a = _a_x;
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Xarb.out.r = _r_x;
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// Encoders
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dualrail_encoder<Nc, N> Xenc(.supply = supply);
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// Wire up inputs to encoders and arb
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(i:N:
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Xarb.in[i].r = in[i].r;
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Xarb.in[i].a = in[i].a;
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Xenc.in[i] = in[i].a;
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)
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INV_X2 inv_buf(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
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A_2C_RB_X1 a_x_Cel(.c1 = inv_buf.y, .c2 = _r_x, .y = _a_x,
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.sr_B = reset_B, .pr_B = reset_B, .vdd = supply.vdd, .vss = supply.vss);
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// Wire up encoder to buffer
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(i:Nc:
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Xenc.out.d[i] = buf.in.d.d[i];
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)
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}
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/**
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* Neuron handshaking.
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@ -839,14 +875,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
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BUF_X2 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
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bool _en, _req;
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// A_1C2N_RB_X1 A_ack(.c1 = _en, .n1 = _req, .n2 = in.r, .y = in.a,
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// .pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
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// Switched it back
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// Because had the problem that if the req was not removed in time,
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// it would be recounted as a double spike,
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// since in.req is still high after the out has been dealt with.
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A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = _req, .y = in.a,
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.pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
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@ -858,19 +887,23 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
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INV_X2 inv_x(.a = outx.a, .y = _x_a_B, .vss = supply.vss, .vdd = supply.vdd);
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INV_X2 inv_y(.a = outy.a, .y = _y_a_B, .vss = supply.vss, .vdd = supply.vdd);
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// WARNUNG WARNUNG WARNUNG //
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// This neuron hs design has a fat timing assumption.
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// Say that the neuron has sent out both reqs, and is now receiving the acks.
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// _x_a_B and _y_a_B are then low, and _req starts to be pulled down to reset the hs.
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// However, if the line pull downs at the end of the neuron row/column are fast enough,
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// then seeing the high acks, they will pull the ack lines down. If the arbiter tree
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// is sufficiently fast enough, then it will remove the ack lines.
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// If this cell were rather tardy, then _req's pd would be cancelled midway,
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// it missed its window of opportunity to switch, and would probably make the system hang.
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// Or starts oscillating with the line pull down and goes brrrrapppppppp.
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// This issue may be somewhat unavoidable, as from a black box perspective,
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// we are giving the neuron acks, but then not listening to it at all to check
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// that it has had time to act upon these acks.
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A_2C1P1N_RB_X1 A_req(.p1 = _x_a_B, .c1 = _en, .c2 = _y_a_B, .n1 = in.r, .y = _req,
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.pr_B = _reset_BX, .sr_B = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
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// // y_req pull up
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// NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
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// A_1P_U_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
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// // x_req pull up
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// NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
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// A_1P_U_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
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// Better version with fewer timing assumptions
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// Core change is that the out acks stop the pullups without any delay.
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// y_req pull up
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bool _reqB;
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INV_X1 req_inv(.a = _req, .y = _reqB, .vdd= supply.vdd, .vss = supply.vss);
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@ -54,7 +54,7 @@ defproc buffer_register(avMx1of2<N> in; Mx1of2<N> out; bool? out_v, flush,
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//control
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bool _en, _reset_BX,_reset_BXX[N];
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bool _en, _reset_BX[N];
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bool _in_aB;
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bool _reset;
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@ -63,11 +63,10 @@ bool _resetX[N];
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// Reset sigs
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INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss);
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sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply);
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BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd, .vss=supply.vss);
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sigbuf<N> resetB_bufarray(.in=_reset_BX, .out=_reset_BXX);
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sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
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A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB,
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.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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.pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss);
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INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss);
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@ -77,7 +76,6 @@ INV_X1 flush_inv(.a = flush, .y = _flushB);
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sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply);
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_en = _in_aB;
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//validity
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bool _in_v;
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vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
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@ -85,11 +83,8 @@ BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
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//function
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bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B;
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// bool _en_X_t[N],_en_X_f[N];
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A_1C2N_SB_X4 f_buf_func[N];
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A_1C2N_RB_X4 t_buf_func[N];
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// sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
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// sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
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sigbuf<N*2> en_buf(.in=_en, .supply=supply);
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(i:N:
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f_buf_func[i].y=out.d[i].f;
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@ -108,23 +103,21 @@ sigbuf<N*2> en_buf(.in=_en, .supply=supply);
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t_buf_func[i].vss=supply.vss;
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f_buf_func[i].pr = _resetX[i];
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f_buf_func[i].sr = _resetX[i];
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t_buf_func[i].pr_B = _reset_BXX[i];
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t_buf_func[i].sr_B = _reset_BXX[i];
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t_buf_func[i].pr_B = _reset_BX[i];
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t_buf_func[i].sr_B = _reset_BX[i];
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)
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}
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/**
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* A single register made out of A cells.
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* last bit is whether to read or write.
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* MSB is whether to read or write.
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* Currently only handles writing.
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*/
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export template<pint N>
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defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out;
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bool? reset_B; power supply) {
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// BIG TODO
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// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
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bool _en2;
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bool _w;
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@ -189,65 +182,71 @@ AND2_X1 gandalf_f[N];
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* Input packets should be
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* [-addr-][-word-][r/w]
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*/
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export template<pint NcA, NcW, M>
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defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
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bool? reset_B; power supply) {
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// BIG TODO
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// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
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vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
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.supply = supply);
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// UNUSED
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// UNUSED
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// UNUSED
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// UNUSED
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// export template<pint NcA, NcW, M>
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// defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
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// bool? reset_B; power supply) {
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// // BIG TODO
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// // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
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// vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
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// .supply = supply);
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// Address decoder
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decoder_dualrail<NcA, M> decoder(.supply = supply);
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(i:NcA:
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decoder.in.d[i] = in.d.d[i];
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)
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// // Address decoder
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// decoder_dualrail<NcA, M> decoder(.supply = supply);
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// (i:NcA:
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// decoder.in.d[i] = in.d.d[i];
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// )
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// OrTree over acks from all registers
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ortree<M> ack_ortree(.supply = supply);
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// // OrTree over acks from all registers
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// ortree<M> ack_ortree(.supply = supply);
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// C element handling in ack
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A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
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.vss = supply.vss, .vdd = supply.vdd);
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// // C element handling in ack
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// A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
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// .vss = supply.vss, .vdd = supply.vdd);
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// Write bit selector
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bool _w = in.d.d[NcA+NcW].t;
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A_2C_B_X1 write_selectors[M];
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(i:M:
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write_selectors[i].c1 = _w;
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write_selectors[i].c2 = decoder.out[i];
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write_selectors[i].vdd = supply.vdd;
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write_selectors[i].vss = supply.vss;
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)
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// // Write bit selector
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// bool _w = in.d.d[NcA+NcW].t;
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// A_2C_B_X1 write_selectors[M];
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// (i:M:
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// write_selectors[i].c1 = _w;
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// write_selectors[i].c2 = decoder.out[i];
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||||
// write_selectors[i].vdd = supply.vdd;
|
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// write_selectors[i].vss = supply.vss;
|
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// )
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// Registers
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register_acells<NcW> registers[M];
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TIELO_X1 tielow_writebit_f[M];
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(i:M:
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// Connect each register to word inputs.
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(j:NcW:
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registers[i].in.d.d[j] = in.d.d[j + NcA];
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)
|
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// // Registers
|
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// register_acells<NcW> registers[M];
|
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// TIELO_X1 tielow_writebit_f[M];
|
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// (i:M:
|
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// // Connect each register to word inputs.
|
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// (j:NcW:
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// registers[i].in.d.d[j] = in.d.d[j + NcA];
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// )
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// Connect the (selected) write bit
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registers[i].in.d.d[NcW].t = write_selectors[i].y;
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tielow_writebit_f[i].vdd = supply.vdd;
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tielow_writebit_f[i].vss = supply.vss;
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registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
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// // Connect the (selected) write bit
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// registers[i].in.d.d[NcW].t = write_selectors[i].y;
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// tielow_writebit_f[i].vdd = supply.vdd;
|
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// tielow_writebit_f[i].vss = supply.vss;
|
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// registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
|
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|
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// Connect to ack ortree
|
||||
registers[i].in.a = ack_ortree.in[i];
|
||||
// // Connect to ack ortree
|
||||
// registers[i].in.a = ack_ortree.in[i];
|
||||
|
||||
// Connect outputs
|
||||
data[i] = registers[i].out;
|
||||
// // Connect outputs
|
||||
// data[i] = registers[i].out;
|
||||
|
||||
registers[i].supply = supply;
|
||||
registers[i].reset_B = reset_B;
|
||||
)
|
||||
// registers[i].supply = supply;
|
||||
// registers[i].reset_B = reset_B;
|
||||
// )
|
||||
|
||||
}
|
||||
// }
|
||||
|
||||
/**
|
||||
* Array of registers made out of A-cells
|
||||
|
|
@ -287,8 +286,9 @@ A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ac
|
|||
// Bit to join the acks either from read or write
|
||||
bool _read_ack;
|
||||
_read_ack = out.a;
|
||||
OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack, .y = in.a,
|
||||
OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack,
|
||||
.vdd = supply.vdd, .vss = supply.vss);
|
||||
A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
|
||||
|
||||
// Write bit selector
|
||||
bool _w = in.d.d[NcA+NcW].t;
|
||||
|
|
|
|||
|
|
@ -55,7 +55,10 @@ fi
|
|||
cd "unit_tests"
|
||||
|
||||
# run all test except single one is specified
|
||||
if [ ! -z $2 ]; then
|
||||
if [ ! -z $3 ]; then
|
||||
numberofruns=$2+$3
|
||||
iteration=$3
|
||||
elif [ ! -z $2 ]; then
|
||||
numberofruns=$2
|
||||
fi
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,268 @@
|
|||
random_seed 99
|
||||
initialize
|
||||
load-scm "helper.scm"
|
||||
random
|
||||
set GND 0
|
||||
set Vdd 1
|
||||
set Reset 1
|
||||
|
||||
mode reset
|
||||
cycle
|
||||
status U
|
||||
watchall
|
||||
|
||||
system "echo '[] Set Reset 1'"
|
||||
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
set Reset 1
|
||||
|
||||
cycle
|
||||
status X
|
||||
system "echo '[] Set Reset 0'"
|
||||
set Reset 0
|
||||
cycle
|
||||
status X
|
||||
|
||||
|
||||
|
||||
system "echo '[] Neuron 5 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 1
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 5
|
||||
assert e.in[5].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.a 1
|
||||
set e.out.v 1
|
||||
cycle
|
||||
assert e.in[5].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 1 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 1
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 1
|
||||
assert e.in[1].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.v 1
|
||||
set e.out.a 1
|
||||
cycle
|
||||
assert e.in[1].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 5 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 1
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 5
|
||||
assert e.in[5].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.a 1
|
||||
set e.out.v 1
|
||||
cycle
|
||||
assert e.in[5].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 1 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 1
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 1
|
||||
assert e.in[1].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.v 1
|
||||
set e.out.a 1
|
||||
cycle
|
||||
assert e.in[1].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 5 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 1
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 5
|
||||
assert e.in[5].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.a 1
|
||||
set e.out.v 1
|
||||
cycle
|
||||
assert e.in[5].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 1 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 1
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 1
|
||||
assert e.in[1].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.v 1
|
||||
set e.out.a 1
|
||||
cycle
|
||||
assert e.in[1].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 6 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 1
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 6
|
||||
assert e.in[6].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.a 1
|
||||
set e.out.v 1
|
||||
cycle
|
||||
assert e.in[6].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 1 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 1
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 1
|
||||
assert e.in[1].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.v 1
|
||||
set e.out.a 1
|
||||
cycle
|
||||
assert e.in[1].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,54 @@
|
|||
/*************************************************************************
|
||||
*
|
||||
* This file is part of ACT dataflow neuro library.
|
||||
* It's the testing facility for cell_lib_std.act
|
||||
*
|
||||
* Copyright (c) 2022 University of Groningen - Ole Richter
|
||||
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
|
||||
* Copyright (c) 2022 University of Groningen - Michele Mastella
|
||||
* Copyright (c) 2022 University of Groningen - Madison Cotteret
|
||||
*
|
||||
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
|
||||
*
|
||||
* You may redistribute and modify this documentation and make products
|
||||
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
||||
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
|
||||
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
|
||||
* for applicable conditions.
|
||||
*
|
||||
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
|
||||
*
|
||||
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
|
||||
* these sources, You must maintain the Source Location visible in its
|
||||
* documentation.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
import "../../dataflow_neuro/coders.act";
|
||||
import globals;
|
||||
import std::data;
|
||||
|
||||
open std::data;
|
||||
|
||||
open tmpl::dataflow_neuro;
|
||||
|
||||
defproc encoder1d_simple_test(a1of1 in[7]; avMx1of2<3> out){
|
||||
power supply;
|
||||
supply.vss = GND;
|
||||
supply.vdd = Vdd;
|
||||
|
||||
bool _reset_B;
|
||||
prs {
|
||||
Reset => _reset_B-
|
||||
}
|
||||
|
||||
encoder1d_simple<3,7> e(.in = in, .supply = supply, .reset_B = _reset_B);
|
||||
|
||||
fifo<3, 5> fifo_post(.in = e.out, .out = out, .supply = supply, .reset_B = _reset_B);
|
||||
|
||||
|
||||
}
|
||||
|
||||
encoder1d_simple_test e;
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
watchall
|
||||
|
||||
system "echo '[] Set Reset 1'"
|
||||
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
set Reset 1
|
||||
|
||||
cycle
|
||||
status X
|
||||
system "echo '[] Set Reset 0'"
|
||||
set Reset 0
|
||||
cycle
|
||||
status X
|
||||
|
||||
|
||||
|
||||
system "echo '[] Neuron 5 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 1
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 5
|
||||
assert e.in[5].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.a 1
|
||||
set e.out.v 1
|
||||
cycle
|
||||
assert e.in[5].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 1 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 1
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 1
|
||||
assert e.in[1].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.v 1
|
||||
set e.out.a 1
|
||||
cycle
|
||||
assert e.in[1].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 5 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 1
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 5
|
||||
assert e.in[5].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.a 1
|
||||
set e.out.v 1
|
||||
cycle
|
||||
assert e.in[5].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 1 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 1
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 1
|
||||
assert e.in[1].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.v 1
|
||||
set e.out.a 1
|
||||
cycle
|
||||
assert e.in[1].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 5 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 1
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 5
|
||||
assert e.in[5].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.a 1
|
||||
set e.out.v 1
|
||||
cycle
|
||||
assert e.in[5].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 1 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 1
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 1
|
||||
assert e.in[1].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.v 1
|
||||
set e.out.a 1
|
||||
cycle
|
||||
assert e.in[1].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 6 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 1
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 6
|
||||
assert e.in[6].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.a 1
|
||||
set e.out.v 1
|
||||
cycle
|
||||
assert e.in[6].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
system "echo '[] Neuron 1 spikes'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 1
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
cycle
|
||||
assert-qdi-channel-valid "e.out" 3 1
|
||||
assert e.in[1].a 1
|
||||
|
||||
system "echo '[] remove data and give ack'"
|
||||
set e.in[0].r 0
|
||||
set e.in[1].r 0
|
||||
set e.in[2].r 0
|
||||
set e.in[3].r 0
|
||||
set e.in[4].r 0
|
||||
set e.in[5].r 0
|
||||
set e.in[6].r 0
|
||||
|
||||
set e.out.v 1
|
||||
set e.out.a 1
|
||||
cycle
|
||||
assert e.in[1].a 0
|
||||
assert-qdi-channel-neutral "e.out" 3
|
||||
set e.out.a 0
|
||||
set e.out.v 0
|
||||
|
||||
Loading…
Reference in New Issue