trying to fix possible lockup in reg lol
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alexmadison
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87499f834a
commit
a5a378fe6c
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@ -54,7 +54,7 @@ defproc buffer_register(avMx1of2<N> in; Mx1of2<N> out; bool? out_v, flush,
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//control
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bool _en, _reset_BX,_reset_BXX[N];
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bool _en, _reset_BX[N];
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bool _in_aB;
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bool _reset;
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@ -63,11 +63,10 @@ bool _resetX[N];
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// Reset sigs
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INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss);
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sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply);
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BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd, .vss=supply.vss);
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sigbuf<N> resetB_bufarray(.in=_reset_BX, .out=_reset_BXX);
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sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
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A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB,
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.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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.pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss);
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INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss);
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@ -77,7 +76,6 @@ INV_X1 flush_inv(.a = flush, .y = _flushB);
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sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply);
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_en = _in_aB;
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//validity
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bool _in_v;
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vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
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@ -85,11 +83,8 @@ BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
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//function
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bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B;
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// bool _en_X_t[N],_en_X_f[N];
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A_1C2N_SB_X4 f_buf_func[N];
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A_1C2N_RB_X4 t_buf_func[N];
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// sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
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// sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
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sigbuf<N*2> en_buf(.in=_en, .supply=supply);
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(i:N:
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f_buf_func[i].y=out.d[i].f;
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@ -108,23 +103,21 @@ sigbuf<N*2> en_buf(.in=_en, .supply=supply);
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t_buf_func[i].vss=supply.vss;
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f_buf_func[i].pr = _resetX[i];
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f_buf_func[i].sr = _resetX[i];
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t_buf_func[i].pr_B = _reset_BXX[i];
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t_buf_func[i].sr_B = _reset_BXX[i];
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t_buf_func[i].pr_B = _reset_BX[i];
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t_buf_func[i].sr_B = _reset_BX[i];
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)
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}
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/**
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* A single register made out of A cells.
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* last bit is whether to read or write.
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* MSB is whether to read or write.
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* Currently only handles writing.
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*/
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export template<pint N>
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defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out;
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bool? reset_B; power supply) {
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// BIG TODO
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// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
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bool _en2;
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bool _w;
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@ -189,65 +182,71 @@ AND2_X1 gandalf_f[N];
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* Input packets should be
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* [-addr-][-word-][r/w]
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*/
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export template<pint NcA, NcW, M>
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defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
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bool? reset_B; power supply) {
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// BIG TODO
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// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
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vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
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.supply = supply);
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// UNUSED
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// UNUSED
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// UNUSED
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// UNUSED
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// export template<pint NcA, NcW, M>
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// defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
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// bool? reset_B; power supply) {
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// // BIG TODO
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// // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
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// vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
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// .supply = supply);
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// Address decoder
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decoder_dualrail<NcA, M> decoder(.supply = supply);
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(i:NcA:
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decoder.in.d[i] = in.d.d[i];
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)
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// // Address decoder
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// decoder_dualrail<NcA, M> decoder(.supply = supply);
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// (i:NcA:
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// decoder.in.d[i] = in.d.d[i];
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// )
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// OrTree over acks from all registers
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ortree<M> ack_ortree(.supply = supply);
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// // OrTree over acks from all registers
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// ortree<M> ack_ortree(.supply = supply);
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// C element handling in ack
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A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
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.vss = supply.vss, .vdd = supply.vdd);
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// // C element handling in ack
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// A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
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// .vss = supply.vss, .vdd = supply.vdd);
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// Write bit selector
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bool _w = in.d.d[NcA+NcW].t;
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A_2C_B_X1 write_selectors[M];
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(i:M:
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write_selectors[i].c1 = _w;
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write_selectors[i].c2 = decoder.out[i];
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write_selectors[i].vdd = supply.vdd;
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write_selectors[i].vss = supply.vss;
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)
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// // Write bit selector
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// bool _w = in.d.d[NcA+NcW].t;
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// A_2C_B_X1 write_selectors[M];
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// (i:M:
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// write_selectors[i].c1 = _w;
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// write_selectors[i].c2 = decoder.out[i];
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// write_selectors[i].vdd = supply.vdd;
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// write_selectors[i].vss = supply.vss;
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// )
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// Registers
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register_acells<NcW> registers[M];
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TIELO_X1 tielow_writebit_f[M];
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(i:M:
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// Connect each register to word inputs.
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(j:NcW:
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registers[i].in.d.d[j] = in.d.d[j + NcA];
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)
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// // Registers
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// register_acells<NcW> registers[M];
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// TIELO_X1 tielow_writebit_f[M];
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// (i:M:
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// // Connect each register to word inputs.
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// (j:NcW:
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// registers[i].in.d.d[j] = in.d.d[j + NcA];
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// )
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// Connect the (selected) write bit
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registers[i].in.d.d[NcW].t = write_selectors[i].y;
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tielow_writebit_f[i].vdd = supply.vdd;
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tielow_writebit_f[i].vss = supply.vss;
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registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
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// // Connect the (selected) write bit
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// registers[i].in.d.d[NcW].t = write_selectors[i].y;
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// tielow_writebit_f[i].vdd = supply.vdd;
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// tielow_writebit_f[i].vss = supply.vss;
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// registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
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// Connect to ack ortree
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registers[i].in.a = ack_ortree.in[i];
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// // Connect to ack ortree
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// registers[i].in.a = ack_ortree.in[i];
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// Connect outputs
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data[i] = registers[i].out;
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// // Connect outputs
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// data[i] = registers[i].out;
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registers[i].supply = supply;
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registers[i].reset_B = reset_B;
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)
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// registers[i].supply = supply;
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// registers[i].reset_B = reset_B;
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// )
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}
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// }
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/**
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* Array of registers made out of A-cells
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@ -287,8 +286,9 @@ A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ac
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// Bit to join the acks either from read or write
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bool _read_ack;
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_read_ack = out.a;
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OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack, .y = in.a,
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OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack,
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.vdd = supply.vdd, .vss = supply.vss);
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A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
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// Write bit selector
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bool _w = in.d.d[NcA+NcW].t;
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