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Merge remote-tracking branch 'origin/dev' into dev

This commit is contained in:
Greatorex 2022-04-12 10:24:44 +02:00
parent aea3bcae6e a5a378fe6c
commit 432ea397d1
9 changed files with 6879 additions and 81 deletions
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2
dataflow_neuro/chips.act
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@ -106,7 +106,7 @@ defproc chip_texel (bd<N_IN> in, out;
NC_NRN = NC_NRN_X + NC_NRN_Y; NC_NRN = NC_NRN_X + NC_NRN_Y;
nrn_hs_2d_array<N_NRN_X,N_NRN_Y,N_LINE_PD_DLY> nrn_grid(.in = neurons, nrn_hs_2d_array<N_NRN_X,N_NRN_Y,N_LINE_PD_DLY> nrn_grid(.in = neurons,
.supply = supply, .reset_B = reset_B); .supply = supply, .reset_B = reset_B);
encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, 16> encoder( encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y> encoder(
.inx = nrn_grid.outx, .inx = nrn_grid.outx,
.iny = nrn_grid.outy, .iny = nrn_grid.outy,
.reset_B = reset_B, .supply = supply .reset_B = reset_B, .supply = supply

69
dataflow_neuro/coders.act
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@ -774,7 +774,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
} }
export template<pint NxC, NyC, Nx, Ny, ACK_STRENGTH> export template<pint NxC, NyC, Nx, Ny>
defproc encoder2d_simple(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out; defproc encoder2d_simple(a1of1 inx[Nx]; a1of1 iny[Ny]; avMx1of2<(NxC + NyC)> out;
power supply; bool reset_B) { power supply; bool reset_B) {
@ -827,6 +827,42 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
} }
export template<pint Nc, N>
defproc encoder1d_simple(a1of1 in[N]; avMx1of2<Nc> out;
power supply; bool reset_B) {
bool _a_x, _r_x;
bool _r_x_B;
buffer<Nc> buf(.out = out, .supply = supply, .reset_B = reset_B);
// Arbiters
arbtree<N> Xarb(.supply = supply);
Xarb.out.a = _a_x;
Xarb.out.r = _r_x;
// Encoders
dualrail_encoder<Nc, N> Xenc(.supply = supply);
// Wire up inputs to encoders and arb
(i:N:
Xarb.in[i].r = in[i].r;
Xarb.in[i].a = in[i].a;
Xenc.in[i] = in[i].a;
)
INV_X2 inv_buf(.a = buf.in.a, .vdd = supply.vdd, .vss = supply.vss);
A_2C_RB_X1 a_x_Cel(.c1 = inv_buf.y, .c2 = _r_x, .y = _a_x,
.sr_B = reset_B, .pr_B = reset_B, .vdd = supply.vdd, .vss = supply.vss);
// Wire up encoder to buffer
(i:Nc:
Xenc.out.d[i] = buf.in.d.d[i];
)
}
/** /**
* Neuron handshaking. * Neuron handshaking.
@ -840,13 +876,6 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
bool _en, _req; bool _en, _req;
// A_1C2N_RB_X1 A_ack(.c1 = _en, .n1 = _req, .n2 = in.r, .y = in.a,
// .pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
// Switched it back
// Because had the problem that if the req was not removed in time,
// it would be recounted as a double spike,
// since in.req is still high after the out has been dealt with.
A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = _req, .y = in.a, A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = _req, .y = in.a,
.pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd); .pr_B = _reset_BX, .sr_B = _reset_BX, .vss = supply.vss, .vdd = supply.vdd);
@ -858,19 +887,23 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
INV_X2 inv_x(.a = outx.a, .y = _x_a_B, .vss = supply.vss, .vdd = supply.vdd); INV_X2 inv_x(.a = outx.a, .y = _x_a_B, .vss = supply.vss, .vdd = supply.vdd);
INV_X2 inv_y(.a = outy.a, .y = _y_a_B, .vss = supply.vss, .vdd = supply.vdd); INV_X2 inv_y(.a = outy.a, .y = _y_a_B, .vss = supply.vss, .vdd = supply.vdd);
// WARNUNG WARNUNG WARNUNG //
// This neuron hs design has a fat timing assumption.
// Say that the neuron has sent out both reqs, and is now receiving the acks.
// _x_a_B and _y_a_B are then low, and _req starts to be pulled down to reset the hs.
// However, if the line pull downs at the end of the neuron row/column are fast enough,
// then seeing the high acks, they will pull the ack lines down. If the arbiter tree
// is sufficiently fast enough, then it will remove the ack lines.
// If this cell were rather tardy, then _req's pd would be cancelled midway,
// it missed its window of opportunity to switch, and would probably make the system hang.
// Or starts oscillating with the line pull down and goes brrrrapppppppp.
// This issue may be somewhat unavoidable, as from a black box perspective,
// we are giving the neuron acks, but then not listening to it at all to check
// that it has had time to act upon these acks.
A_2C1P1N_RB_X1 A_req(.p1 = _x_a_B, .c1 = _en, .c2 = _y_a_B, .n1 = in.r, .y = _req, A_2C1P1N_RB_X1 A_req(.p1 = _x_a_B, .c1 = _en, .c2 = _y_a_B, .n1 = in.r, .y = _req,
.pr_B = _reset_BX, .sr_B = _reset_BX, .vdd = supply.vdd, .vss = supply.vss); .pr_B = _reset_BX, .sr_B = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
// // y_req pull up
// NAND2_X1 nand_y(.a = _y_a_B, .b = _req, .vdd = supply.vdd, .vss = supply.vss);
// A_1P_U_X4 pu_y(.a = nand_y.y, .y = outy.r, .vdd = supply.vdd, .vss = supply.vss);
// // x_req pull up
// NAND3_X1 nand_x(.a = _x_a_B, .b = _req, .c = outy.a, .vdd = supply.vdd, .vss = supply.vss);
// A_1P_U_X4 pu_x(.a = nand_x.y, .y = outx.r, .vdd = supply.vdd, .vss = supply.vss);
// Better version with fewer timing assumptions
// Core change is that the out acks stop the pullups without any delay.
// y_req pull up // y_req pull up
bool _reqB; bool _reqB;
INV_X1 req_inv(.a = _req, .y = _reqB, .vdd= supply.vdd, .vss = supply.vss); INV_X1 req_inv(.a = _req, .y = _reqB, .vdd= supply.vdd, .vss = supply.vss);

122
dataflow_neuro/registers.act
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@ -54,7 +54,7 @@ defproc buffer_register(avMx1of2<N> in; Mx1of2<N> out; bool? out_v, flush,
//control //control
bool _en, _reset_BX,_reset_BXX[N]; bool _en, _reset_BX[N];
bool _in_aB; bool _in_aB;
bool _reset; bool _reset;
@ -63,11 +63,10 @@ bool _resetX[N];
// Reset sigs // Reset sigs
INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss); INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply); sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd, .vss=supply.vss); sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
sigbuf<N> resetB_bufarray(.in=_reset_BX, .out=_reset_BXX);
A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB, A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB,
.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); .pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss);
INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss); INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss);
@ -77,7 +76,6 @@ INV_X1 flush_inv(.a = flush, .y = _flushB);
sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply); sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply);
_en = _in_aB; _en = _in_aB;
//validity //validity
bool _in_v; bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply); vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
@ -85,11 +83,8 @@ BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function //function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B; bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B;
// bool _en_X_t[N],_en_X_f[N];
A_1C2N_SB_X4 f_buf_func[N]; A_1C2N_SB_X4 f_buf_func[N];
A_1C2N_RB_X4 t_buf_func[N]; A_1C2N_RB_X4 t_buf_func[N];
// sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
// sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
sigbuf<N*2> en_buf(.in=_en, .supply=supply); sigbuf<N*2> en_buf(.in=_en, .supply=supply);
(i:N: (i:N:
f_buf_func[i].y=out.d[i].f; f_buf_func[i].y=out.d[i].f;
@ -108,23 +103,21 @@ sigbuf<N*2> en_buf(.in=_en, .supply=supply);
t_buf_func[i].vss=supply.vss; t_buf_func[i].vss=supply.vss;
f_buf_func[i].pr = _resetX[i]; f_buf_func[i].pr = _resetX[i];
f_buf_func[i].sr = _resetX[i]; f_buf_func[i].sr = _resetX[i];
t_buf_func[i].pr_B = _reset_BXX[i]; t_buf_func[i].pr_B = _reset_BX[i];
t_buf_func[i].sr_B = _reset_BXX[i]; t_buf_func[i].sr_B = _reset_BX[i];
) )
} }
/** /**
* A single register made out of A cells. * A single register made out of A cells.
* last bit is whether to read or write. * MSB is whether to read or write.
* Currently only handles writing. * Currently only handles writing.
*/ */
export template<pint N> export template<pint N>
defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out; defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out;
bool? reset_B; power supply) { bool? reset_B; power supply) {
// BIG TODO
// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
bool _en2; bool _en2;
bool _w; bool _w;
@ -189,65 +182,71 @@ AND2_X1 gandalf_f[N];
* Input packets should be * Input packets should be
* [-addr-][-word-][r/w] * [-addr-][-word-][r/w]
*/ */
export template<pint NcA, NcW, M>
defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
bool? reset_B; power supply) {
// BIG TODO // UNUSED
// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET // UNUSED
vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v, // UNUSED
.supply = supply); // UNUSED
// export template<pint NcA, NcW, M>
// defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
// bool? reset_B; power supply) {
// // BIG TODO
// // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
// vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
// .supply = supply);
// Address decoder // // Address decoder
decoder_dualrail<NcA, M> decoder(.supply = supply); // decoder_dualrail<NcA, M> decoder(.supply = supply);
(i:NcA: // (i:NcA:
decoder.in.d[i] = in.d.d[i]; // decoder.in.d[i] = in.d.d[i];
) // )
// OrTree over acks from all registers // // OrTree over acks from all registers
ortree<M> ack_ortree(.supply = supply); // ortree<M> ack_ortree(.supply = supply);
// C element handling in ack // // C element handling in ack
A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a, // A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
.vss = supply.vss, .vdd = supply.vdd); // .vss = supply.vss, .vdd = supply.vdd);
// Write bit selector // // Write bit selector
bool _w = in.d.d[NcA+NcW].t; // bool _w = in.d.d[NcA+NcW].t;
A_2C_B_X1 write_selectors[M]; // A_2C_B_X1 write_selectors[M];
(i:M: // (i:M:
write_selectors[i].c1 = _w; // write_selectors[i].c1 = _w;
write_selectors[i].c2 = decoder.out[i]; // write_selectors[i].c2 = decoder.out[i];
write_selectors[i].vdd = supply.vdd; // write_selectors[i].vdd = supply.vdd;
write_selectors[i].vss = supply.vss; // write_selectors[i].vss = supply.vss;
) // )
// Registers // // Registers
register_acells<NcW> registers[M]; // register_acells<NcW> registers[M];
TIELO_X1 tielow_writebit_f[M]; // TIELO_X1 tielow_writebit_f[M];
(i:M: // (i:M:
// Connect each register to word inputs. // // Connect each register to word inputs.
(j:NcW: // (j:NcW:
registers[i].in.d.d[j] = in.d.d[j + NcA]; // registers[i].in.d.d[j] = in.d.d[j + NcA];
) // )
// Connect the (selected) write bit // // Connect the (selected) write bit
registers[i].in.d.d[NcW].t = write_selectors[i].y; // registers[i].in.d.d[NcW].t = write_selectors[i].y;
tielow_writebit_f[i].vdd = supply.vdd; // tielow_writebit_f[i].vdd = supply.vdd;
tielow_writebit_f[i].vss = supply.vss; // tielow_writebit_f[i].vss = supply.vss;
registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y; // registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
// Connect to ack ortree // // Connect to ack ortree
registers[i].in.a = ack_ortree.in[i]; // registers[i].in.a = ack_ortree.in[i];
// Connect outputs // // Connect outputs
data[i] = registers[i].out; // data[i] = registers[i].out;
registers[i].supply = supply; // registers[i].supply = supply;
registers[i].reset_B = reset_B; // registers[i].reset_B = reset_B;
) // )
} // }
/** /**
* Array of registers made out of A-cells * Array of registers made out of A-cells
@ -287,8 +286,9 @@ A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ac
// Bit to join the acks either from read or write // Bit to join the acks either from read or write
bool _read_ack; bool _read_ack;
_read_ack = out.a; _read_ack = out.a;
OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack, .y = in.a, OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack,
.vdd = supply.vdd, .vss = supply.vss); .vdd = supply.vdd, .vss = supply.vss);
A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
// Write bit selector // Write bit selector
bool _w = in.d.d[NcA+NcW].t; bool _w = in.d.d[NcA+NcW].t;

5
test/repeat_unit.sh
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@ -55,7 +55,10 @@ fi
cd "unit_tests" cd "unit_tests"
# run all test except single one is specified # run all test except single one is specified
if [ ! -z $2 ]; then if [ ! -z $3 ]; then
numberofruns=$2+$3
iteration=$3
elif [ ! -z $2 ]; then
numberofruns=$2 numberofruns=$2
fi fi

268
test/unit_tests/encoder1d_7/run/prsim.in Normal file
View File

@ -0,0 +1,268 @@
random_seed 99
initialize
load-scm "helper.scm"
random
set GND 0
set Vdd 1
set Reset 1
mode reset
cycle
status U
watchall
system "echo '[] Set Reset 1'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 0
set e.out.v 0
set Reset 1
cycle
status X
system "echo '[] Set Reset 0'"
set Reset 0
cycle
status X
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 6 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 1
cycle
assert-qdi-channel-valid "e.out" 3 6
assert e.in[6].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[6].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0

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test/unit_tests/encoder1d_7/test.act Normal file
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@ -0,0 +1,54 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/coders.act";
import globals;
import std::data;
open std::data;
open tmpl::dataflow_neuro;
defproc encoder1d_simple_test(a1of1 in[7]; avMx1of2<3> out){
power supply;
supply.vss = GND;
supply.vdd = Vdd;
bool _reset_B;
prs {
Reset => _reset_B-
}
encoder1d_simple<3,7> e(.in = in, .supply = supply, .reset_B = _reset_B);
fifo<3, 5> fifo_post(.in = e.out, .out = out, .supply = supply, .reset_B = _reset_B);
}
encoder1d_simple_test e;

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watchall
system "echo '[] Set Reset 1'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 0
set e.out.v 0
set Reset 1
cycle
status X
system "echo '[] Set Reset 0'"
set Reset 0
cycle
status X
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 5 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 1
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 5
assert e.in[5].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[5].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 6 spikes'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 1
cycle
assert-qdi-channel-valid "e.out" 3 6
assert e.in[6].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.a 1
set e.out.v 1
cycle
assert e.in[6].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0
system "echo '[] Neuron 1 spikes'"
set e.in[0].r 0
set e.in[1].r 1
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
cycle
assert-qdi-channel-valid "e.out" 3 1
assert e.in[1].a 1
system "echo '[] remove data and give ack'"
set e.in[0].r 0
set e.in[1].r 0
set e.in[2].r 0
set e.in[3].r 0
set e.in[4].r 0
set e.in[5].r 0
set e.in[6].r 0
set e.out.v 1
set e.out.a 1
cycle
assert e.in[1].a 0
assert-qdi-channel-neutral "e.out" 3
set e.out.a 0
set e.out.v 0