first tests passed
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@ -89,7 +89,7 @@ defproc chip_texel (bd<N_IN> in, out;
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NC_SYN = NC_SYN_X + NC_SYN_Y;
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NC_SYN = NC_SYN_X + NC_SYN_Y;
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slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
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slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
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fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = reset_B, .supply = supply);
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fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = reset_B, .supply = supply);
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decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.in,
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decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
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.out = synapses,
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.out = synapses,
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.hs_en = register.data[0].d[0].f, // Defaults to handshake disable
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.hs_en = register.data[0].d[0].f, // Defaults to handshake disable
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.supply = supply, .reset_B = reset_B);
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.supply = supply, .reset_B = reset_B);
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@ -121,7 +121,7 @@ defproc chip_texel (bd<N_IN> in, out;
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// qdi2bd
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// qdi2bd
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fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_loop8mrg.out,
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fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_loop8mrg.out,
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.reset_B = reset_B, .supply = supply);
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.reset_B = reset_B, .supply = supply);
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qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2b(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
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qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
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.reset_B = reset_B, .supply = supply);
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.reset_B = reset_B, .supply = supply);
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}
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}
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Load Diff
@ -1,22 +1,26 @@
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watchall
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watchall
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# set-bool-array "c.bd_dly_cfg" 4 15
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set c.bd_dly_cfg[0] 1
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set c.bd_dly_cfg[0] 1
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set c.bd_dly_cfg[1] 1
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set c.bd_dly_cfg[1] 1
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set c.bd_dly_cfg[2] 1
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set c.bd_dly_cfg[2] 1
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set c.bd_dly_cfg[3] 1
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set c.bd_dly_cfg[3] 1
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set-bd-channel-neutral "c.in" 14
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set-bd-channel-neutral "c.in" 14
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set-bd-channel-neutral "c.out" 14
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# set-bd-channel-neutral "c.out" 14
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set c.out.a 0
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set c.loopback_en 1
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set c.loopback_en 1
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set Reset 1
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set Reset 1
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cycle
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cycle
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mode run
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mode run
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status X
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system "echo '[] Set reset 0'"
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system "echo '[] Set reset 0'"
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status X
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status X
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set Reset 0
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set Reset 0
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cycle
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cycle
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set-bd-channel-valid "c.in" 14 16128
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cycle
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assert-bd-channel-valid "c.out" 14 16128
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