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added second delaycfg to bd2qdi

This commit is contained in:
alexmadison 2022-04-05 19:17:54 +02:00
parent 41d76de718
commit 74c5b8703f
5 changed files with 7848 additions and 9 deletions
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6
dataflow_neuro/chips.act
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@ -49,19 +49,19 @@ N_SYN_DLY_CFG,
N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
N_BUFFERS,
N_LINE_PD_DLY, // Number of dummy delays to add line pull down
N_BD_DLY_CFG,
N_BD_DLY_CFG, N_BD_DLY_CFG2,
REG_NCA, REG_NCW, REG_M>
defproc chip_texel (bd<N_IN> in, out;
Mx1of2<REG_NCW> reg_data[REG_M];
a1of1 synapses[N_SYN_X * N_SYN_Y];
a1of1 neurons[N_NRN_X * N_NRN_Y];
bool? bd_dly_cfg[N_BD_DLY_CFG];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B){
bd2qdi<N_IN, N_BD_DLY_CFG> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg,
bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
.reset_B = reset_B, .supply = supply);
fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = reset_B, .supply = supply);

22
dataflow_neuro/interfaces.act
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@ -48,8 +48,10 @@ namespace tmpl {
* quasi delay insensitive channel (dual rail).
* Basically a buffer with a bitwise conversion in front of it.
*/
export template<pint N, N_dly_cfg>
defproc bd2qdi(bd<N> in; avMx1of2<N> out; bool? dly_cfg[N_dly_cfg]; power supply; bool? reset_B) {
export template<pint N, N_dly_cfg, N_dly_cfg2>
defproc bd2qdi(bd<N> in; avMx1of2<N> out; bool? dly_cfg[N_dly_cfg], dly_cfg2[N_dly_cfg2];
power supply; bool? reset_B) {
// Delay on req_in
bool _req;
delayprog<N_dly_cfg> dly(.in = in.r, .out = _req, .s = dly_cfg, .supply = supply);
@ -60,12 +62,20 @@ namespace tmpl {
sigbuf<N> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
// sig buff the req
bool _reqX, _reqXX[N+1];
bool _reqX, _reqXX[N];
BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss);
sigbuf<N+1> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
sigbuf<N> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
// For reasons of pure spice, the control circuitry
// requires a req signal that FALLS SLOWER than the req going to the function block.
// Thus need another delay prog.
bool _req_slowfall;
delayprog<N_dly_cfg2> dly2(.in = _reqX, .s = dly_cfg2, .supply = supply);
OR2_X1 req_dly_or(.a = _reqX, .b = dly2.out, .y = _req_slowfall,
.vss = supply.vss, .vdd = supply.vdd);
// bd2qdi conversion
// Each line goes to a t pin, its not to a f.
// Each line goes to a t pin, its not to an f.
bool _inB[N];
INV_X1 input_invs[N];
(i:N:
@ -89,7 +99,7 @@ namespace tmpl {
//control
bool _en;
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_reqXX[N],.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_req_slowfall,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
//function

7798
test/unit_tests/chip_nomap/run/prsim.out
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test/unit_tests/chip_nomap/run/prsim.pdf Normal file
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31
test/unit_tests/chip_nomap/test.prsim
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@ -114,5 +114,36 @@ set c.in.r 1
cycle
assert c.in.a 1
# Remove input
set-bd-channel-neutral "c.in" 14
cycle
assert c.in.a 0
# Receiving output 68 from register 1
assert-bd-channel-valid "c.out" 14 1089
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 14
set c.out.a 0
cycle
# Sending spike to synapse [0,1]
set c.in.d[0] 0
set c.in.d[1] 1
set c.in.d[2] 0
set c.in.d[3] 0
set c.in.d[4] 0
set c.in.d[5] 0
set c.in.d[6] 0
set c.in.d[7] 0
set c.in.d[8] 0
set c.in.d[9] 0
set c.in.d[10] 0
set c.in.d[11] 0
set c.in.d[12] 0
set c.in.d[13] 0
cycle
set c.in.r 1
cycle
assert c.in.a 1