added second delaycfg to bd2qdi
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test/unit_tests/chip_nomap/run/prsim.pdf
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test/unit_tests/chip_nomap/run/prsim.pdf
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@ -114,5 +114,36 @@ set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output 68 from register 1
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assert-bd-channel-valid "c.out" 14 1089
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Sending spike to synapse [0,1]
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set c.in.d[0] 0
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set c.in.d[1] 1
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set c.in.d[2] 0
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set c.in.d[3] 0
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set c.in.d[4] 0
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set c.in.d[5] 0
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set c.in.d[6] 0
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set c.in.d[7] 0
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set c.in.d[8] 0
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set c.in.d[9] 0
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set c.in.d[10] 0
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set c.in.d[11] 0
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set c.in.d[12] 0
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set c.in.d[13] 0
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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