added second delaycfg to bd2qdi

test/unit_tests/chip_nomap/test.prsim

@@ -114,5 +114,36 @@ set c.in.r 1
 cycle
 assert c.in.a 1
 
+ # Remove input
+set-bd-channel-neutral "c.in" 14
+cycle
+assert c.in.a 0
 
+
+# Receiving output 68 from register 1
 assert-bd-channel-valid "c.out" 14 1089
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 14
+set c.out.a 0
+cycle
+
+# Sending spike to synapse [0,1]
+set c.in.d[0] 0
+set c.in.d[1] 1
+set c.in.d[2] 0
+set c.in.d[3] 0
+set c.in.d[4] 0
+set c.in.d[5] 0
+set c.in.d[6] 0
+set c.in.d[7] 0
+set c.in.d[8] 0
+set c.in.d[9] 0
+set c.in.d[10] 0
+set c.in.d[11] 0
+set c.in.d[12] 0
+set c.in.d[13] 0
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1