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added DLY4 cell

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alexmadison 2022-03-01 15:28:22 +01:00
parent 233c9a7d10
commit 79a96ed511
1 changed files with 12 additions and 0 deletions
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12
dataflow_neuro/cell_lib_std.act
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@ -99,6 +99,18 @@ namespace tmpl {
sizing { _y {-6,2}; y {-12,4} } sizing { _y {-6,2}; y {-12,4} }
} }
/*-- delay cells --*/
// TODO properly
export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
{
bool _y;
prs {
a => _y-
_y => y-
}
}
/*-- simple gates --*/ /*-- simple gates --*/