dummy neuron block init

This commit is contained in:
alexmadison 2022-05-05 14:56:59 +02:00
parent 10f4821eaa
commit 7e895605da
1 changed files with 89 additions and 0 deletions

89
dataflow_neuro/dummy.act Normal file
View File

@ -0,0 +1,89 @@
/*************************************************************************
*
* This file is part of ACT dataflow neuro library
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/cell_lib_async.act";
import "../../dataflow_neuro/cell_lib_std.act";
import "../../dataflow_neuro/treegates.act";
import "../../dataflow_neuro/primitives.act";
// import tmpl::dataflow_neuro;
// import tmpl::dataflow_neuro;
import std::channel;
open std::channel;
namespace tmpl {
namespace dataflow_neuro {
/**
* Creates a synapse-neuron dummy block,
* where any synapse being triggered makes the neuron "spike".
*/
export template<pint N_SYN>
defproc dummy_neuron_block (a1of1 synapses[N_SYN], neuron; power supply){
// OR over reqs from syn in to neuron out
ortree<N_SYN> _ortree(.out = neuron.r, .supply = supply);
(i:N_SYN: _ortree.in[i] = synapses[i].r;)
// ANDs piping the ack back to the proper synapse
AND2_X1 ands[N_SYN];
(i:N_SYN:
ands[i].a = neuron.a;
ands[i].b = synapses[i].r;
ands[i].y = synapses[i].a;
ands[i].vss = supply.vss;
ands[i].vdd = supply.vdd;
)
}
/**
* Create an array of neuron dummy blocks.
*/
export template<pint N_SYN_PER_NRN, N_NRN, N_NRN_X>
defproc dummy_neuron_core (a1of1 synapses[N_SYN_PER_NRN * N_NRN], neurons[N_NRN]; power supply){
dummy_neuron_block<N_SYN_PER_NRN> blocks[N_NRN];
pint Xn, Yn, Xs, Ys;
(i:N_NRN:
Yn = i/N_NRN_X;
Xn = i-Yn*N_NRN_X;
neurons[i] = blocks[i].neuron;
blocks[i].supply = supply;
(j:N_SYN_PER_NRN: // moron, need to think about neuron indexxing too
Xs = Xn;
Ys = Yn*N_SYN_PER_NRN + j;
blocks[i].synapses[j] = synapses[Ys*N_NRN_X + Xs];
)
)
}
}
}