added improved registers
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alexmadison
parent
2ea83f3472
commit
87577268e5
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@ -204,6 +204,19 @@ namespace tmpl {
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y {-4}; _y{-1}}
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}
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export defcell A_2C1N_SB_X4 (bool! y; bool? c1, c2, n1, pr, sr; bool vdd, vss)
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{
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bool _y;
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prs{
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~c1 & ~c2 & ~sr-> _y+
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c1&c2&n1 | pr -> _y-
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_y => y-
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}
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sizing {leak_adjust <- 1;
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p_n_mode <- 1;
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y {-4}; _y{-1}}
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}
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export defcell A_1C2P1N_X1 (bool! y; bool? c1, p1, p2, n1; bool vdd, vss)
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{
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@ -172,82 +172,83 @@ AND2_X1 gandalf_f[N];
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}
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/**
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* Array of registers made out of A-cells
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* params:
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* NcW: number of bits in Words to be stored in buffers
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* NcA: number of bits in Address
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* M: number of registers. M = 2^Nc_addr would be a natural choice.
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* Input packets should be
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* [-addr-][-word-][r/w]
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/**
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* A single register made out of A cells.
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* MSB is whether to read or write.
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* Currently only handles writing.
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* NOTE: this does not handle in.v properly, and instead has in.v = in.a
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*/
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export template<pint N>
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defproc register_acells_improved(avMx1of2<N+1> in; Mx1of2<N> out;
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bool? reset_B; power supply) {
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// UNUSED
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// UNUSED
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// UNUSED
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// UNUSED
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bool _resetX[N], _reset_BX[N];
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bool _en, _enBX;
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bool _flush, _flushBX;
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bool _out_v, _out_vB;
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bool _w = in.d.d[N].t;
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// export template<pint NcA, NcW, M>
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// defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
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// bool? reset_B; power supply) {
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INV_X2 out_val_inv(.a = _out_v, .y = _out_vB,
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.vdd = supply.vdd, .vss= supply.vss);
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// // BIG TODO
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// // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
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// vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
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// .supply = supply);
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// Reset sigs
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INV_X1 reset_inv(.a = reset_B, .vdd = supply.vdd, .vss = supply.vss);
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sigbuf<N> reset_sb(.in = reset_inv.y, .out = _resetX, .supply = supply);
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sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
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A_2C1N_RB_X1 A_flush(.c1 = _en, .c2 = _out_v, .n1 = _w, .y = _flush,
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.vdd = supply.vdd, .vss = supply.vss, .pr_B = _reset_BX[0], .sr_B = _reset_BX[0]);
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A_2C_X1 A_en(.c1 = _w, .c2 = _out_vB, .y = _en,
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.vdd = supply.vdd, .vss = supply.vss);
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INV_X1 flush_inv(.a = _flush, .vdd = supply.vdd, .vss = supply.vss);
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sigbuf<N*2> sb_flushB(.in = flush_inv.y, .supply = supply);
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sb_flushB.out[0] = _flushBX;
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INV_X1 en_inv(.a = _en, .vdd = supply.vdd, .vss = supply.vss);
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sigbuf<N*2> sb_enB(.in = en_inv.y, .supply = supply);
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sb_enB.out[0] = _enBX;
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vtree<N> vc(.in = out, .out = _out_v, .supply = supply);
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// WARNING WARNING
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in.v = in.a;
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A_1C1P_X1 A_ack(.c1 = _en, .p1 = _out_vB, .y = in.a,
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.vdd = supply.vdd, .vss = supply.vss);
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//function
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A_2C1N_SB_X4 f_buf_func[N];
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A_2C1N_RB_X4 t_buf_func[N];
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(i:N:
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f_buf_func[i].y=out.d[i].f;
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t_buf_func[i].y=out.d[i].t;
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f_buf_func[i].c1=_flushBX;
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t_buf_func[i].c1=_flushBX;
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f_buf_func[i].c2=_enBX;
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t_buf_func[i].c2=_enBX;
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f_buf_func[i].n1=in.d.d[i].f;
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t_buf_func[i].n1=in.d.d[i].t;
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f_buf_func[i].vdd=supply.vdd;
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t_buf_func[i].vdd=supply.vdd;
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f_buf_func[i].vss=supply.vss;
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t_buf_func[i].vss=supply.vss;
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f_buf_func[i].pr = _resetX[i];
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f_buf_func[i].sr = _resetX[i];
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t_buf_func[i].pr_B = _reset_BX[i];
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t_buf_func[i].sr_B = _reset_BX[i];
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)
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}
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// // Address decoder
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// decoder_dualrail<NcA, M> decoder(.supply = supply);
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// (i:NcA:
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// decoder.in.d[i] = in.d.d[i];
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// )
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// // OrTree over acks from all registers
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// ortree<M> ack_ortree(.supply = supply);
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// // C element handling in ack
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// A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
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// .vss = supply.vss, .vdd = supply.vdd);
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// // Write bit selector
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// bool _w = in.d.d[NcA+NcW].t;
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// A_2C_B_X1 write_selectors[M];
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// (i:M:
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// write_selectors[i].c1 = _w;
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// write_selectors[i].c2 = decoder.out[i];
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// write_selectors[i].vdd = supply.vdd;
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// write_selectors[i].vss = supply.vss;
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// )
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// // Registers
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// register_acells<NcW> registers[M];
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// TIELO_X1 tielow_writebit_f[M];
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// (i:M:
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// // Connect each register to word inputs.
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// (j:NcW:
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// registers[i].in.d.d[j] = in.d.d[j + NcA];
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// )
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// // Connect the (selected) write bit
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// registers[i].in.d.d[NcW].t = write_selectors[i].y;
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// tielow_writebit_f[i].vdd = supply.vdd;
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// tielow_writebit_f[i].vss = supply.vss;
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// registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
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// // Connect to ack ortree
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// registers[i].in.a = ack_ortree.in[i];
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// // Connect outputs
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// data[i] = registers[i].out;
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// registers[i].supply = supply;
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// registers[i].reset_B = reset_B;
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// )
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// }
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/**
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* Array of registers made out of A-cells
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@ -303,7 +304,7 @@ A_2C_B_X1 write_selectors[M];
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// Registers
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register_acells<NcW> registers[M];
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register_acells_improved<NcW> registers[M];
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TIELO_X1 tielow_writebit_f[M];
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(i:M:
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// Connect each register to word inputs.
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