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trying to fix possible lockup in reg lol

This commit is contained in:
alexmadison 2022-04-12 10:24:26 +02:00
parent 87499f834a
commit a5a378fe6c
1 changed files with 61 additions and 61 deletions
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122
dataflow_neuro/registers.act
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@ -54,7 +54,7 @@ defproc buffer_register(avMx1of2<N> in; Mx1of2<N> out; bool? out_v, flush,
//control //control
bool _en, _reset_BX,_reset_BXX[N]; bool _en, _reset_BX[N];
bool _in_aB; bool _in_aB;
bool _reset; bool _reset;
@ -63,11 +63,10 @@ bool _resetX[N];
// Reset sigs // Reset sigs
INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss); INV_X1 reset_inv(.a = reset_B, .y = _reset, .vdd = supply.vdd, .vss = supply.vss);
sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply); sigbuf<N> reset_sb(.in = _reset, .out = _resetX, .supply = supply);
BUF_X1 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd, .vss=supply.vss); sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
sigbuf<N> resetB_bufarray(.in=_reset_BX, .out=_reset_BXX);
A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB, A_2C1N_R_X1 inack_ctl(.c1=_in_aB,.c2=in.v,.n1=out_v,.y=_in_aB,
.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss); .pr_B=_reset_BX[0],.sr_B=_reset_BX[0],.vdd=supply.vdd,.vss=supply.vss);
INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss); INV_X1 inack_inv(.a = _in_aB, .y = in.a, .vdd = supply.vdd, .vss = supply.vss);
@ -77,7 +76,6 @@ INV_X1 flush_inv(.a = flush, .y = _flushB);
sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply); sigbuf<N*2> flushB_sb(.in = _flushB, .out = _flushBX, .supply = supply);
_en = _in_aB; _en = _in_aB;
//validity //validity
bool _in_v; bool _in_v;
vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply); vtree<N> vc(.in=in.d,.out=_in_v,.supply=supply);
@ -85,11 +83,8 @@ BUF_X4 in_v_buf(.a=_in_v, .y=in.v,.vdd=supply.vdd,.vss=supply.vss);
//function //function
bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B; bool _out_a_BX_t[N],_out_a_BX_f[N],_out_a_B;
// bool _en_X_t[N],_en_X_f[N];
A_1C2N_SB_X4 f_buf_func[N]; A_1C2N_SB_X4 f_buf_func[N];
A_1C2N_RB_X4 t_buf_func[N]; A_1C2N_RB_X4 t_buf_func[N];
// sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
// sigbuf<N> en_buf_t(.in=_en, .out=_en_X_t, .supply=supply);
sigbuf<N*2> en_buf(.in=_en, .supply=supply); sigbuf<N*2> en_buf(.in=_en, .supply=supply);
(i:N: (i:N:
f_buf_func[i].y=out.d[i].f; f_buf_func[i].y=out.d[i].f;
@ -108,23 +103,21 @@ sigbuf<N*2> en_buf(.in=_en, .supply=supply);
t_buf_func[i].vss=supply.vss; t_buf_func[i].vss=supply.vss;
f_buf_func[i].pr = _resetX[i]; f_buf_func[i].pr = _resetX[i];
f_buf_func[i].sr = _resetX[i]; f_buf_func[i].sr = _resetX[i];
t_buf_func[i].pr_B = _reset_BXX[i]; t_buf_func[i].pr_B = _reset_BX[i];
t_buf_func[i].sr_B = _reset_BXX[i]; t_buf_func[i].sr_B = _reset_BX[i];
) )
} }
/** /**
* A single register made out of A cells. * A single register made out of A cells.
* last bit is whether to read or write. * MSB is whether to read or write.
* Currently only handles writing. * Currently only handles writing.
*/ */
export template<pint N> export template<pint N>
defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out; defproc register_acells(avMx1of2<N+1> in; Mx1of2<N> out;
bool? reset_B; power supply) { bool? reset_B; power supply) {
// BIG TODO
// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
bool _en2; bool _en2;
bool _w; bool _w;
@ -189,65 +182,71 @@ AND2_X1 gandalf_f[N];
* Input packets should be * Input packets should be
* [-addr-][-word-][r/w] * [-addr-][-word-][r/w]
*/ */
export template<pint NcA, NcW, M>
defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
bool? reset_B; power supply) {
// BIG TODO // UNUSED
// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET // UNUSED
vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v, // UNUSED
.supply = supply); // UNUSED
// export template<pint NcA, NcW, M>
// defproc register_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
// bool? reset_B; power supply) {
// // BIG TODO
// // I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
// vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
// .supply = supply);
// Address decoder // // Address decoder
decoder_dualrail<NcA, M> decoder(.supply = supply); // decoder_dualrail<NcA, M> decoder(.supply = supply);
(i:NcA: // (i:NcA:
decoder.in.d[i] = in.d.d[i]; // decoder.in.d[i] = in.d.d[i];
) // )
// OrTree over acks from all registers // // OrTree over acks from all registers
ortree<M> ack_ortree(.supply = supply); // ortree<M> ack_ortree(.supply = supply);
// C element handling in ack // // C element handling in ack
A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a, // A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
.vss = supply.vss, .vdd = supply.vdd); // .vss = supply.vss, .vdd = supply.vdd);
// Write bit selector // // Write bit selector
bool _w = in.d.d[NcA+NcW].t; // bool _w = in.d.d[NcA+NcW].t;
A_2C_B_X1 write_selectors[M]; // A_2C_B_X1 write_selectors[M];
(i:M: // (i:M:
write_selectors[i].c1 = _w; // write_selectors[i].c1 = _w;
write_selectors[i].c2 = decoder.out[i]; // write_selectors[i].c2 = decoder.out[i];
write_selectors[i].vdd = supply.vdd; // write_selectors[i].vdd = supply.vdd;
write_selectors[i].vss = supply.vss; // write_selectors[i].vss = supply.vss;
) // )
// Registers // // Registers
register_acells<NcW> registers[M]; // register_acells<NcW> registers[M];
TIELO_X1 tielow_writebit_f[M]; // TIELO_X1 tielow_writebit_f[M];
(i:M: // (i:M:
// Connect each register to word inputs. // // Connect each register to word inputs.
(j:NcW: // (j:NcW:
registers[i].in.d.d[j] = in.d.d[j + NcA]; // registers[i].in.d.d[j] = in.d.d[j + NcA];
) // )
// Connect the (selected) write bit // // Connect the (selected) write bit
registers[i].in.d.d[NcW].t = write_selectors[i].y; // registers[i].in.d.d[NcW].t = write_selectors[i].y;
tielow_writebit_f[i].vdd = supply.vdd; // tielow_writebit_f[i].vdd = supply.vdd;
tielow_writebit_f[i].vss = supply.vss; // tielow_writebit_f[i].vss = supply.vss;
registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y; // registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
// Connect to ack ortree // // Connect to ack ortree
registers[i].in.a = ack_ortree.in[i]; // registers[i].in.a = ack_ortree.in[i];
// Connect outputs // // Connect outputs
data[i] = registers[i].out; // data[i] = registers[i].out;
registers[i].supply = supply; // registers[i].supply = supply;
registers[i].reset_B = reset_B; // registers[i].reset_B = reset_B;
) // )
} // }
/** /**
* Array of registers made out of A-cells * Array of registers made out of A-cells
@ -287,8 +286,9 @@ A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ac
// Bit to join the acks either from read or write // Bit to join the acks either from read or write
bool _read_ack; bool _read_ack;
_read_ack = out.a; _read_ack = out.a;
OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack, .y = in.a, OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack,
.vdd = supply.vdd, .vss = supply.vss); .vdd = supply.vdd, .vss = supply.vss);
A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
// Write bit selector // Write bit selector
bool _w = in.d.d[NcA+NcW].t; bool _w = in.d.d[NcA+NcW].t;