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changed write bit selectors from ands to Cels, to avoid selector hazards

This commit is contained in:
alexmadison 2022-04-02 17:37:56 +02:00
parent eda9e2a98b
commit b59a57c324
1 changed files with 4 additions and 3 deletions
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7
dataflow_neuro/registers.act
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@ -422,6 +422,7 @@ defproc registerA_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
.supply = supply);
// Address decoder
decoder_dualrail<NcA, M> decoder(.supply = supply);
(i:NcA:
@ -437,10 +438,10 @@ A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
// Write bit selector
bool _w = in.d.d[NcA+NcW].t;
AND2_X1 write_selectors[M];
A_2C_B_X1 write_selectors[M];
(i:M:
write_selectors[i].a = _w;
write_selectors[i].b = decoder.out[i];
write_selectors[i].c1 = _w;
write_selectors[i].c2 = decoder.out[i];
write_selectors[i].vdd = supply.vdd;
write_selectors[i].vss = supply.vss;
)