Added new version of Register_rw (still not properly working)

dataflow_neuro/cell_lib_std.act

@@ -373,7 +373,7 @@ namespace tmpl {
       }
       sizing { _en{-2}; y{-2,2} }
     }
-    export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q; bool? vdd,vss)
+    export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q,q_B; bool? vdd,vss)
     {
       bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;
       prs {
@@ -393,6 +393,8 @@ namespace tmpl {
         _sqib => _sqi-
         _sqib => q-
 
+        q => q_B-
+
 
       }
     } 

dataflow_neuro/registers.act

@@ -62,9 +62,9 @@ defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supp
     // Generation of the fake clock pulse (inverted because the ff clocks are low_active)
     delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
     INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
-    sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
+    sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
     // Sending back to the ackowledge
-    delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
+    delayprog<N_dly_cfg> ack_dly(.in = _clock_temp_inv, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
     sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
     //Reset Buffers
     bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
@@ -127,61 +127,65 @@ defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supp
 // data -> the data saved in the flip flop, sized wl x nw
 export template<pint lognw,wl,N_dly_cfg>
 defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
-    bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
-    bool _ff_v;
     pint nw = 1<<lognw;
+    bool _in_v_temp,_in_a_temp,_clock_temp,_clock[nw],_clock_temp_inv, _in_a_write, _in_a_read;
     //Validation of the input 
-    avMx1of2<lognw+wl> _in_temp2,_in_read,_in_write;
+    vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
-    avMx1of2<1>_in_flag;
+    sigbuf_1output<12> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
-    // Read or write?
+    // Acknowledgment
-    AND2_X1 ack_and(.a = _in_temp2.a,.b = _ff_v,.y = in.a,.vdd = supply.vdd,.vss = supply.vss);
+    OR2_X1 ack_readwrite(.a = _in_a_write,.b = _in_a_read,.y =  _in_a_temp,.vdd = supply.vdd,.vss = supply.vss);
-    in.v = _in_temp2.v;
+    sigbuf_1output<12> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
-    _in_flag.d.d[0] = in.d.d[lognw+wl];
+    // WRITE
-    (i:lognw+wl:_in_temp2.d.d[i] = in.d.d[i];)
+        // Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active)
-    demux<lognw+wl> read_write_demux(.in = _in_temp2,.out1 = _in_read, .out2 = _in_write, .cond = _in_flag,.reset_B = reset_B);
+        bool _in_v_temp_write;
-    read_write_demux.supply= supply;
+        AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f, .y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
-    //WRITE PATH
+        delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply);
-        // Validation
-        Mx1of2<lognw+wl> _in_write_temp;
-        (i:lognw+wl:_in_write_temp.d[i] = _in_write.d.d[i];)
-        vtree<lognw+wl> val_input_write(.in = _in_write_temp,.out = _in_write.v, .supply = supply);
-        // Acknowledgment
-        delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_write.a,.s = dly_cfg, .supply = supply);
-        // Generation of the fake clock pulse (inverted because the ff clocks are low_active)
-        delayprog<N_dly_cfg> clk_dly(.in = _in_write.v, .out = _clock_temp,.s = dly_cfg, .supply = supply);
         INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
-        sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
+        sigbuf<nw> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
-    //READ PATH
+        sigbuf<wl> clock_buffer[nw];
-        //Validation
+        bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
-        Mx1of2<lognw+wl> _in_read_temp;
+        // Sending back to the ackowledge
-        (i:lognw+wl:_in_read_temp.d[i] = _in_read.d.d[i];)
+        bool _in_a_write_temp;
-        vtree<lognw+wl> val_input_read(.in = _in_read_temp,.out = _in_read.v, .supply = supply);
+        delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply);
-        vtree<wl> ff_validator;
+        AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss);
-        Mx1of2<wl> _out_temp;
+    // READ
-        (i:wl:_out_temp.d[i] = out.d.d[i];)
+        //Outputing the word to read
-        ff_validator.in = _out_temp;
+        AND2_X1 word_to_read[nw];
-        ff_validator.out = _ff_v;
+        sigbuf<wl*2> word_to_read_X[nw];
-        ff_validator.supply = supply;
+        ortree<nw> bitselector_t[wl];
-        // Acknowledgment
+        ortree<nw> bitselector_f[wl];
-        _in_read.a = _ff_v; //The circuit is ack when flip flop data are valid
+        AND2_X1 word_selector_t[nw*wl];
+        AND2_X1 word_selector_f[nw*wl];
+        bool _out_word_to_read[2*nw*wl];
+        buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B);
+        AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw];
+        // Outputting the address if the read is true
+        (i:lognw:
+            address_propagator_t[i].a = in.d.d[lognw+wl].t;
+            address_propagator_t[i].b = in.d.d[i+wl].t;
+            address_propagator_t[i].y = output_buf.in.d.d[i+wl].t;
+            address_propagator_t[i].vdd = supply.vdd;
+            address_propagator_t[i].vss = supply.vss;
             
+            address_propagator_f[i].a = in.d.d[lognw+wl].t;
+            address_propagator_f[i].b = in.d.d[i+wl].f;
+            address_propagator_f[i].y = output_buf.in.d.d[i+wl].f;
+            address_propagator_f[i].vdd = supply.vdd;
+            address_propagator_f[i].vss = supply.vss;
+        )
+        AND2_X1 ack_read_and(.a = in.d.d[lognw+wl].t,.b = output_buf.in.a,.y = _in_a_read,.vdd = supply.vdd, .vss = supply.vss);
     //Reset Buffers
-    bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl*2];
+    bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
     BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
     BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
-    sigbuf<nw*wl*2> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
+    sigbuf<nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
-    // Creating the different flip flop arrays
+    //Creating the encoder
-    bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
     andtree<lognw> atree[nw];
-    d1of<wl> _data_f;
     AND2_X1 and_encoder[nw];
-    AND3_X1 reading_activator_t[nw*wl],reading_activator_f[nw*wl];
+    // Creating the different flip flop arrays
-
+    bool _out_encoder[nw];
-    sigbuf<wl*2> clock_buffer[nw];
+    DFFQ_R_X1 ff[nw*wl];
-    DFFQ_R_X1 ff_t[nw*wl],ff_f[nw*wl];
+    // For loop for assigning the different components
-    OR2_X1 ff_val[wl];
-    (i:wl..lognw:out.d.d[i] = in.d.d[i];)
-    bool __ffout_dualrail[nw*wl];
     pint bitval;
     (k:nw:atree[k].supply = supply;)
     (word_idx:nw:
@@ -195,50 +199,50 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
             []bitval >= 2 -> {false : "fuck"};
             ]
         )
-        // Encode which work is the right one
-        atree[word_idx].out = _out_encoder[word_idx];    
-        // READ: use the encoder selection to read the value
-
         // WRITE: Activating the fake clock for the right word
+        atree[word_idx].out = _out_encoder[word_idx];    
         and_encoder[word_idx].a = _out_encoder[word_idx];
-        and_encoder[word_idx].b = _clock;
+        and_encoder[word_idx].b = _clock[word_idx];
         and_encoder[word_idx].y = _clock_word_temp[word_idx];
         and_encoder[word_idx].vdd = supply.vdd;
         and_encoder[word_idx].vss = supply.vss;
         clock_buffer[word_idx].in = _clock_word_temp[word_idx];
         clock_buffer[word_idx].supply = supply;
-        // Describing all the FF and their connection
+        // READ: Selecting the right word to read if read is high
+        word_to_read[word_idx].a = in.d.d[lognw+wl].t;
+        word_to_read[word_idx].b = _out_encoder[word_idx];
+        word_to_read[word_idx].y = word_to_read_X[word_idx].in;
+        word_to_read[word_idx].vdd = supply.vdd;
+        word_to_read[word_idx].vss = supply.vss;
+        word_to_read_X[word_idx].supply = supply;
+
+
+        
         (bit_idx:wl:
-            ff_t[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
+            // Describing all the FF and their connection
-            ff_t[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
+            ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
-            ff_t[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
+            ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
-            ff_t[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
+            ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
-            ff_t[bit_idx+word_idx*(wl)].vdd = supply.vdd;
+            ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
-            ff_t[bit_idx+word_idx*(wl)].vss = supply.vss;
+            ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
-            
+            ff[bit_idx+word_idx*(wl)].vss = supply.vss;
-            ff_f[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx+wl-1];
+            // READ: creating the selectors for propagating the right word
-            ff_f[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].f;
+            word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+word_idx*(wl)].a;
-            ff_f[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)+nw-1];
+            word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+word_idx*(wl)].a;
-            ff_f[bit_idx+word_idx*(wl)].vdd = supply.vdd;
+            word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q;
-            ff_f[bit_idx+word_idx*(wl)].vss = supply.vss;
+            word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx];
-
+            word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q_B;
-            reading_activator_t[bit_idx+word_idx*(wl)].a = _in_flag.d.d[0].t;
+            word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx];
-            reading_activator_t[bit_idx+word_idx*(wl)].b = ff_t[bit_idx+word_idx*(wl)].q;
+            bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t;
-            reading_activator_t[bit_idx+word_idx*(wl)].c = _out_encoder[word_idx];
+            bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f;
-            reading_activator_t[bit_idx+word_idx*(wl)].y = out.d.d[bit_idx].t;
+            bitselector_t[bit_idx].supply = supply;
-            reading_activator_t[bit_idx+word_idx*(wl)].vdd = supply.vdd;
+            bitselector_f[bit_idx].supply = supply;
-            reading_activator_t[bit_idx+word_idx*(wl)].vss = supply.vss;
-
-            reading_activator_f[bit_idx+word_idx*(wl)].a = _in_flag.d.d[0].f;
-            reading_activator_f[bit_idx+word_idx*(wl)].b = ff_f[bit_idx+word_idx*(wl)].q;
-            reading_activator_f[bit_idx+word_idx*(wl)].y = out.d.d[bit_idx].f;
-            reading_activator_f[bit_idx+word_idx*(wl)].vdd = supply.vdd;
-            reading_activator_f[bit_idx+word_idx*(wl)].vss = supply.vss;
-            reading_activator_f[bit_idx+word_idx*(wl)].c = _out_encoder[word_idx];
-
         )
     )
     }
 
+
+
+
 }}
 

test/unit_tests/register_wrw/test.prsim

@@ -1,4 +1,4 @@
-#watchall
+watchall
 system "echo '[0] start test'"
 system "echo '----------------------------------------------------------'"
 
@@ -7,12 +7,18 @@ set t.data[0].d[0] 0
 set t.data[0].d[1] 0
 set t.data[1].d[0] 0
 set t.data[1].d[1] 0
+set t.dly_cfg[0] 1
+set t.dly_cfg[1] 1
 set t.out.a 0
+set t.out.v 0
+#set t.registers._in_write.a 0
 set Reset 0
 cycle
 status X
-mode run
+#mode run
-assert-qdi-channel-neutral "t.in" 5
+cycle
+
+assert-qdi-channel-neutral "t.out" 4
 assert t.data[0].d[0] 0
 assert t.data[0].d[1] 0
 assert t.data[1].d[0] 0
@@ -22,28 +28,44 @@ system "echo '[1] reset completed'"
 system "echo '----------------------------------------------------------'"
 
 # Set delay config lines
-set t.dly_cfg[0] 1
+
-set t.dly_cfg[1] 1
 cycle
 system "echo '[2] delay line set'"
 system "echo '----------------------------------------------------------'"
 
+
 set-qdi-channel-valid "t.in" 5 3
+# 3 -> 00011 -> writing mode, address 00, word 11
 cycle
-assert-qdi-channel-valid "t.registers._in_write" 4 3
+assert t.in.a 1
-assert t.registers._clock 0
+assert-qdi-channel-neutral "t.out" 4
-assert t.registers._out_encoder[0] 1
-assert t.registers._out_encoder[1] 0
-assert t.registers._out_encoder[2] 0
-assert t.registers._out_encoder[3] 0
-cycle
 set-qdi-channel-neutral "t.in" 5
 cycle
-assert t.registers._clock 1
+assert t.registers.ff[0].q 1
-assert t.registers.ff_t[0].q 1
+assert t.registers.ff[1].q 1
-assert t.registers.ff_t[1].q 1
+assert t.registers.ff[2].q 0
+assert t.registers.ff[3].q 0
+
 system "echo '[3] first writing done'"
 system "echo '----------------------------------------------------------'"
 
+set-qdi-channel-valid "t.in" 5 16
+# 16 -> 10000 -> reading mode, address 00, word 00 (word doesn't needed here)
+cycle
+assert-qdi-channel-valid "t.out" 4 3
+set t.out.v 1
+cycle
+set t.out.a 1
+cycle
+assert t.in.a 1
+set-qdi-channel-neutral "t.in" 5
+cycle
+assert t.registers.ff[0].q 1
+assert t.registers.ff[1].q 1
+assert t.registers.ff[2].q 0
+assert t.registers.ff[3].q 0
+assert-qdi-channel-neutral "t.out" 4
+system "echo '[4] reading done'"
+system "echo '----------------------------------------------------------'"